diff options
| author | Ashay Jaiswal <ashayj@codeaurora.org> | 2017-03-21 22:46:06 +0530 |
|---|---|---|
| committer | Ashay Jaiswal <ashayj@codeaurora.org> | 2017-04-05 10:02:39 +0530 |
| commit | ef45c30bc84a0ba83be48f0aa59e7170bf5058a8 (patch) | |
| tree | c479136fd548f5f296d25f514fab4b8922ec3fd3 | |
| parent | f521128115ac89264850f7a52fe42b62c052600d (diff) | |
qcom: smb2: disable h/w autonomous parallel control
The charger driver ensures that parallel charging remains
disabled as long as AICL is below threshole (1400mA) using
it's software voting mechanism(USBIN_I_VOTER), thus disable
hardware's autonomous control of input current based parallel
charging.
CRs-Fixed: 2014572
Change-Id: Ie991e0c1d16d63b6def6fb3379019114d20d60f7
Signed-off-by: Ashay Jaiswal <ashayj@codeaurora.org>
Signed-off-by: Abhijeet Dharmapurikar <adharmap@codeaurora.org>
| -rw-r--r-- | drivers/power/supply/qcom/qpnp-smb2.c | 10 | ||||
| -rw-r--r-- | drivers/power/supply/qcom/smb-reg.h | 1 |
2 files changed, 11 insertions, 0 deletions
diff --git a/drivers/power/supply/qcom/qpnp-smb2.c b/drivers/power/supply/qcom/qpnp-smb2.c index 92cdcb68ada6..0a0f1decf65e 100644 --- a/drivers/power/supply/qcom/qpnp-smb2.c +++ b/drivers/power/supply/qcom/qpnp-smb2.c @@ -1568,6 +1568,16 @@ static int smb2_init_hw(struct smb2 *chip) return rc; } + /* disable h/w autonomous parallel charging control */ + rc = smblib_masked_write(chg, MISC_CFG_REG, + STAT_PARALLEL_1400MA_EN_CFG_BIT, 0); + if (rc < 0) { + dev_err(chg->dev, + "Couldn't disable h/w autonomous parallel control rc=%d\n", + rc); + return rc; + } + /* configure float charger options */ switch (chip->dt.float_option) { case 1: diff --git a/drivers/power/supply/qcom/smb-reg.h b/drivers/power/supply/qcom/smb-reg.h index b79060094cf6..167666a8c548 100644 --- a/drivers/power/supply/qcom/smb-reg.h +++ b/drivers/power/supply/qcom/smb-reg.h @@ -919,6 +919,7 @@ enum { #define MISC_CFG_REG (MISC_BASE + 0x52) #define GSM_PA_ON_ADJ_SEL_BIT BIT(0) +#define STAT_PARALLEL_1400MA_EN_CFG_BIT BIT(3) #define TCC_DEBOUNCE_20MS_BIT BIT(5) #define SNARL_BARK_BITE_WD_CFG_REG (MISC_BASE + 0x53) |