diff options
| author | H Hartley Sweeten <hsweeten@visionengravers.com> | 2014-11-04 10:55:21 -0700 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2014-11-07 09:34:05 -0800 |
| commit | ee844c51ef0451ff7646a075710b9646e943f1e7 (patch) | |
| tree | ae37fe6031f2d79e9236886f8a72581e991f5734 | |
| parent | 0b7defa70227f7c7f313e0ea4f0eeb88c5de79a3 (diff) | |
staging: comedi: addi_apci_3120: move apci3120_init_dma() to driver
Move this function from the included source file to the main driver
source file.
Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Reviewed-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| -rw-r--r-- | drivers/staging/comedi/drivers/addi-data/hwdrv_apci3120.c | 32 | ||||
| -rw-r--r-- | drivers/staging/comedi/drivers/addi_apci_3120.c | 32 |
2 files changed, 32 insertions, 32 deletions
diff --git a/drivers/staging/comedi/drivers/addi-data/hwdrv_apci3120.c b/drivers/staging/comedi/drivers/addi-data/hwdrv_apci3120.c index 1799833cde32..a241368d79e1 100644 --- a/drivers/staging/comedi/drivers/addi-data/hwdrv_apci3120.c +++ b/drivers/staging/comedi/drivers/addi-data/hwdrv_apci3120.c @@ -26,38 +26,6 @@ static int apci3120_cancel(struct comedi_device *dev, return 0; } -static void apci3120_init_dma(struct comedi_device *dev, - struct apci3120_dmabuf *dmabuf) -{ - struct apci3120_private *devpriv = dev->private; - - /* AMCC - enable transfer count and reset A2P FIFO */ - outl(AGCSTS_TC_ENABLE | AGCSTS_RESET_A2P_FIFO, - devpriv->amcc + AMCC_OP_REG_AGCSTS); - - /* Add-On - enable transfer count and reset A2P FIFO */ - apci3120_addon_write(dev, AGCSTS_TC_ENABLE | AGCSTS_RESET_A2P_FIFO, - AMCC_OP_REG_AGCSTS); - - /* AMCC - enable transfers and reset A2P flags */ - outl(RESET_A2P_FLAGS | EN_A2P_TRANSFERS, - devpriv->amcc + AMCC_OP_REG_MCSR); - - /* Add-On - DMA start address */ - apci3120_addon_write(dev, dmabuf->hw, AMCC_OP_REG_AMWAR); - - /* Add-On - Number of acquisitions */ - apci3120_addon_write(dev, dmabuf->use_size, AMCC_OP_REG_AMWTC); - - /* AMCC - enable write complete (DMA) and set FIFO advance */ - outl(APCI3120_FIFO_ADVANCE_ON_BYTE_2 | AINT_WRITE_COMPL, - devpriv->amcc + AMCC_OP_REG_INTCSR); - - /* Add-On - enable DMA */ - outw(APCI3120_ADDON_CTRL_AMWEN_ENA | APCI3120_ADDON_CTRL_A2P_FIFO_ENA, - devpriv->addon + APCI3120_ADDON_CTRL_REG); -} - static void apci3120_setup_dma(struct comedi_device *dev, struct comedi_subdevice *s) { diff --git a/drivers/staging/comedi/drivers/addi_apci_3120.c b/drivers/staging/comedi/drivers/addi_apci_3120.c index dab81cbe79da..d66e91084bf7 100644 --- a/drivers/staging/comedi/drivers/addi_apci_3120.c +++ b/drivers/staging/comedi/drivers/addi_apci_3120.c @@ -177,6 +177,38 @@ static void apci3120_addon_write(struct comedi_device *dev, outw((val >> 16) & 0xffff, devpriv->addon + APCI3120_ADDON_DATA_REG); } +static void apci3120_init_dma(struct comedi_device *dev, + struct apci3120_dmabuf *dmabuf) +{ + struct apci3120_private *devpriv = dev->private; + + /* AMCC - enable transfer count and reset A2P FIFO */ + outl(AGCSTS_TC_ENABLE | AGCSTS_RESET_A2P_FIFO, + devpriv->amcc + AMCC_OP_REG_AGCSTS); + + /* Add-On - enable transfer count and reset A2P FIFO */ + apci3120_addon_write(dev, AGCSTS_TC_ENABLE | AGCSTS_RESET_A2P_FIFO, + AMCC_OP_REG_AGCSTS); + + /* AMCC - enable transfers and reset A2P flags */ + outl(RESET_A2P_FLAGS | EN_A2P_TRANSFERS, + devpriv->amcc + AMCC_OP_REG_MCSR); + + /* Add-On - DMA start address */ + apci3120_addon_write(dev, dmabuf->hw, AMCC_OP_REG_AMWAR); + + /* Add-On - Number of acquisitions */ + apci3120_addon_write(dev, dmabuf->use_size, AMCC_OP_REG_AMWTC); + + /* AMCC - enable write complete (DMA) and set FIFO advance */ + outl(APCI3120_FIFO_ADVANCE_ON_BYTE_2 | AINT_WRITE_COMPL, + devpriv->amcc + AMCC_OP_REG_INTCSR); + + /* Add-On - enable DMA */ + outw(APCI3120_ADDON_CTRL_AMWEN_ENA | APCI3120_ADDON_CTRL_A2P_FIFO_ENA, + devpriv->addon + APCI3120_ADDON_CTRL_REG); +} + /* * There are three timers on the board. They all use the same base * clock with a fixed prescaler for each timer. The base clock used |