ath10k: define structure for the copy engine register map

Instead of defining the copy engine register map as a macro,
Define a structure for the copy engine register map to avoid
the conditional compilation, code optimization and dynamic
configuration of the copy engine register map for respective
hardware bus interface.

Change-Id: I799794ed85b83e342c2aab3d12b2876fc28d680b
Signed-off-by: Sarada Prasanna Garnayak <sgarna@codeaurora.org>

8 files changed, 124 insertions, 103 deletions

diff --git a/drivers/net/wireless/ath/ath10k/ce.c b/drivers/net/wireless/ath/ath10k/ce.c
index b8ef3780c2ac..ad9ab56adb8f 100644
--- a/drivers/net/wireless/ath/ath10k/ce.c
+++ b/drivers/net/wireless/ath/ath10k/ce.c
@@ -64,7 +64,8 @@ static inline void ath10k_ce_dest_ring_write_index_set(struct ath10k *ar,
 {
 	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);
 
-	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + DST_WR_INDEX_ADDRESS, n);
+	ar_opaque->bus_ops->write32(ar,
+		ce_ctrl_addr + ar->hw_ce_regs->dst_wr_index_addr, n);
 }
 
 static inline u32 ath10k_ce_dest_ring_write_index_get(struct ath10k *ar,
@@ -72,8 +73,8 @@ static inline u32 ath10k_ce_dest_ring_write_index_get(struct ath10k *ar,
 {
 	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);
 
-	return ar_opaque->bus_ops->read32(ar, ce_ctrl_addr +
-					  DST_WR_INDEX_ADDRESS);
+	return ar_opaque->bus_ops->read32(ar,
+			ce_ctrl_addr + ar->hw_ce_regs->dst_wr_index_addr);
 }
 
 static inline void ath10k_ce_src_ring_write_index_set(struct ath10k *ar,
@@ -82,7 +83,8 @@ static inline void ath10k_ce_src_ring_write_index_set(struct ath10k *ar,
 {
 	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);
 
-	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + SR_WR_INDEX_ADDRESS, n);
+	ar_opaque->bus_ops->write32(ar,
+		ce_ctrl_addr + ar->hw_ce_regs->sr_wr_index_addr, n);
 }
 
 static inline u32 ath10k_ce_src_ring_write_index_get(struct ath10k *ar,
@@ -90,8 +92,8 @@ static inline u32 ath10k_ce_src_ring_write_index_get(struct ath10k *ar,
 {
 	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);
 
-	return ar_opaque->bus_ops->read32(ar, ce_ctrl_addr +
-					  SR_WR_INDEX_ADDRESS);
+	return ar_opaque->bus_ops->read32(ar,
+			ce_ctrl_addr + ar->hw_ce_regs->sr_wr_index_addr);
 }
 
 static inline u32 ath10k_ce_src_ring_read_index_get(struct ath10k *ar,
@@ -99,8 +101,8 @@ static inline u32 ath10k_ce_src_ring_read_index_get(struct ath10k *ar,
 {
 	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);
 
-	return ar_opaque->bus_ops->read32(ar, ce_ctrl_addr +
-					  CURRENT_SRRI_ADDRESS);
+	return ar_opaque->bus_ops->read32(ar,
+			ce_ctrl_addr + ar->hw_ce_regs->current_srri_addr);
 }
 
 static inline void ath10k_ce_shadow_src_ring_write_index_set(struct ath10k *ar,
@@ -130,7 +132,8 @@ static inline void ath10k_ce_src_ring_base_addr_set(struct ath10k *ar,
 {
 	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);
 
-	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + SR_BA_ADDRESS, addr);
+	ar_opaque->bus_ops->write32(ar,
+		ce_ctrl_addr + ar->hw_ce_regs->sr_base_addr, addr);
 }
 
 static inline void ath10k_ce_src_ring_size_set(struct ath10k *ar,
@@ -139,7 +142,8 @@ static inline void ath10k_ce_src_ring_size_set(struct ath10k *ar,
 {
 	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);
 
-	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + SR_SIZE_ADDRESS, n);
+	ar_opaque->bus_ops->write32(ar,
+		ce_ctrl_addr + ar->hw_ce_regs->sr_size_addr, n);
 }
 
 static inline void ath10k_ce_src_ring_dmax_set(struct ath10k *ar,
@@ -186,8 +190,8 @@ static inline u32 ath10k_ce_dest_ring_read_index_get(struct ath10k *ar,
 {
 	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);
 
-	return ar_opaque->bus_ops->read32(ar, ce_ctrl_addr +
-					  CURRENT_DRRI_ADDRESS);
+	return ar_opaque->bus_ops->read32(ar,
+			ce_ctrl_addr + ar->hw_ce_regs->current_drri_addr);
 }
 
 static inline void ath10k_ce_dest_ring_base_addr_set(struct ath10k *ar,
@@ -196,7 +200,8 @@ static inline void ath10k_ce_dest_ring_base_addr_set(struct ath10k *ar,
 {
 	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);
 
-	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + DR_BA_ADDRESS, addr);
+	ar_opaque->bus_ops->write32(ar,
+		ce_ctrl_addr + ar->hw_ce_regs->dr_base_addr, addr);
 }
 
 static inline void ath10k_ce_dest_ring_size_set(struct ath10k *ar,
@@ -205,7 +210,8 @@ static inline void ath10k_ce_dest_ring_size_set(struct ath10k *ar,
 {
 	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);
 
-	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + DR_SIZE_ADDRESS, n);
+	ar_opaque->bus_ops->write32(ar,
+		ce_ctrl_addr + ar->hw_ce_regs->dr_size_addr, n);
 }
 
 static inline void ath10k_ce_src_ring_highmark_set(struct ath10k *ar,
@@ -266,10 +272,11 @@ static inline void ath10k_ce_copy_complete_inter_enable(struct ath10k *ar,
 {
 	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);
 	u32 host_ie_addr = ar_opaque->bus_ops->read32(ar,
-					     ce_ctrl_addr + HOST_IE_ADDRESS);
+				ce_ctrl_addr + ar->hw_ce_regs->host_ie_addr);
 
-	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + HOST_IE_ADDRESS,
-			   host_ie_addr | HOST_IE_COPY_COMPLETE_MASK);
+	ar_opaque->bus_ops->write32(ar,
+			ce_ctrl_addr + ar->hw_ce_regs->host_ie_addr,
+			host_ie_addr | HOST_IE_COPY_COMPLETE_MASK);
 }
 
 static inline void ath10k_ce_copy_complete_intr_disable(struct ath10k *ar,
@@ -277,10 +284,11 @@ static inline void ath10k_ce_copy_complete_intr_disable(struct ath10k *ar,
 {
 	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);
 	u32 host_ie_addr = ar_opaque->bus_ops->read32(ar,
-					     ce_ctrl_addr + HOST_IE_ADDRESS);
+				ce_ctrl_addr + ar->hw_ce_regs->host_ie_addr);
 
-	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + HOST_IE_ADDRESS,
-			   host_ie_addr & ~HOST_IE_COPY_COMPLETE_MASK);
+	ar_opaque->bus_ops->write32(ar,
+			ce_ctrl_addr + ar->hw_ce_regs->host_ie_addr,
+			host_ie_addr & ~HOST_IE_COPY_COMPLETE_MASK);
 }
 
 static inline void ath10k_ce_watermark_intr_disable(struct ath10k *ar,
@@ -288,10 +296,11 @@ static inline void ath10k_ce_watermark_intr_disable(struct ath10k *ar,
 {
 	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);
 	u32 host_ie_addr = ar_opaque->bus_ops->read32(ar,
-					     ce_ctrl_addr + HOST_IE_ADDRESS);
+				ce_ctrl_addr + ar->hw_ce_regs->host_ie_addr);
 
-	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + HOST_IE_ADDRESS,
-			   host_ie_addr & ~CE_WATERMARK_MASK);
+	ar_opaque->bus_ops->write32(ar,
+			ce_ctrl_addr + ar->hw_ce_regs->host_ie_addr,
+			host_ie_addr & ~CE_WATERMARK_MASK);
 }
 
 static inline void ath10k_ce_error_intr_enable(struct ath10k *ar,
@@ -299,10 +308,11 @@ static inline void ath10k_ce_error_intr_enable(struct ath10k *ar,
 {
 	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);
 	u32 misc_ie_addr = ar_opaque->bus_ops->read32(ar,
-					     ce_ctrl_addr + MISC_IE_ADDRESS);
+			ce_ctrl_addr + ar->hw_ce_regs->misc_ie_addr);
 
-	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + MISC_IE_ADDRESS,
-			   misc_ie_addr | CE_ERROR_MASK);
+	ar_opaque->bus_ops->write32(ar,
+			ce_ctrl_addr + ar->hw_ce_regs->misc_ie_addr,
+			misc_ie_addr | CE_ERROR_MASK);
 }
 
 static inline void ath10k_ce_error_intr_disable(struct ath10k *ar,
@@ -310,10 +320,11 @@ static inline void ath10k_ce_error_intr_disable(struct ath10k *ar,
 {
 	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);
 	u32 misc_ie_addr = ar_opaque->bus_ops->read32(ar,
-					     ce_ctrl_addr + MISC_IE_ADDRESS);
+			ce_ctrl_addr + ar->hw_ce_regs->misc_ie_addr);
 
-	ar_opaque->bus_ops->write32(ar, ce_ctrl_addr + MISC_IE_ADDRESS,
-			   misc_ie_addr & ~CE_ERROR_MASK);
+	ar_opaque->bus_ops->write32(ar,
+			ce_ctrl_addr + ar->hw_ce_regs->misc_ie_addr,
+			misc_ie_addr & ~CE_ERROR_MASK);
 }
 
 static inline void ath10k_ce_engine_int_status_clear(struct ath10k *ar,
@@ -391,6 +402,21 @@ u32 shadow_dst_wr_ind_addr(struct ath10k *ar, u32 ctrl_addr)
 	return addr;
 }
 
+static inline void ath10k_ce_snoc_addr_config(struct ce_desc *sdesc,
+					      dma_addr_t buffer,
+					      unsigned int flags)
+{
+	__le32 *addr = (__le32 *)&sdesc->addr;
+
+	flags |= upper_32_bits(buffer) & CE_DESC_FLAGS_GET_MASK;
+	addr[0] = __cpu_to_le32(buffer);
+	addr[1] = flags;
+	if (flags & CE_SEND_FLAG_GATHER)
+		addr[1] |= CE_WCN3990_DESC_FLAGS_GATHER;
+	else
+		addr[1] &= ~CE_WCN3990_DESC_FLAGS_GATHER;
+}
+
 /*
  * Guts of ath10k_ce_send, used by both ath10k_ce_send and
  * ath10k_ce_sendlist_send.
@@ -434,17 +460,10 @@ int ath10k_ce_send_nolock(struct ath10k_ce_pipe *ce_state,
 	if (flags & CE_SEND_FLAG_BYTE_SWAP)
 		desc_flags |= CE_DESC_FLAGS_BYTE_SWAP;
 
-	if (QCA_REV_WCN3990(ar)) {
-		flags |= upper_32_bits(buffer) & CE_DESC_FLAGS_GET_MASK;
-		sdesc.addr_lo = __cpu_to_le32(buffer);
-		sdesc.addr_hi = flags;
-		if (flags & CE_SEND_FLAG_GATHER)
-			sdesc.addr_hi |= CE_WCN3990_DESC_FLAGS_GATHER;
-		else
-			sdesc.addr_hi &= ~CE_WCN3990_DESC_FLAGS_GATHER;
-	} else {
+	if (QCA_REV_WCN3990(ar))
+		ath10k_ce_snoc_addr_config(&sdesc, buffer, flags);
+	else
 		sdesc.addr   = __cpu_to_le32(buffer);
-	}
 
 	sdesc.nbytes = __cpu_to_le16(nbytes);
 	sdesc.flags  = __cpu_to_le16(desc_flags);
@@ -983,7 +1002,7 @@ void ath10k_ce_enable_per_ce_interrupts(struct ath10k *ar, unsigned int ce_id)
 	u32 ctrl_addr = ath10k_ce_base_address(ar, ce_id);
 	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);
 
-	offset = HOST_IE_ADDRESS + ctrl_addr;
+	offset = ar->hw_ce_regs->host_ie_addr + ctrl_addr;
 	ar_opaque->bus_ops->write32(ar, offset, 1);
 	ar_opaque->bus_ops->read32(ar, offset);
 }
@@ -994,7 +1013,7 @@ void ath10k_ce_disable_per_ce_interrupts(struct ath10k *ar, unsigned int ce_id)
 	u32 ctrl_addr = ath10k_ce_base_address(ar, ce_id);
 	struct bus_opaque *ar_opaque = ath10k_bus_priv(ar);
 
-	offset = HOST_IE_ADDRESS + ctrl_addr;
+	offset = ar->hw_ce_regs->host_ie_addr + ctrl_addr;
 	ar_opaque->bus_ops->write32(ar, offset, 0);
 	ar_opaque->bus_ops->read32(ar, offset);
 }
diff --git a/drivers/net/wireless/ath/ath10k/ce.h b/drivers/net/wireless/ath/ath10k/ce.h
index f4fa86b93082..365576ef08e9 100644
--- a/drivers/net/wireless/ath/ath10k/ce.h
+++ b/drivers/net/wireless/ath/ath10k/ce.h
@@ -58,13 +58,7 @@ struct ce_desc {
 };
 #else
 struct ce_desc {
-	union {
-		__le64 addr;
-		struct {
-			__le32 addr_lo;
-			__le32 addr_hi;
-		};
-	};
+	__le64 addr;
 	u16 nbytes; /* length in register map */
 	u16 flags; /* fw_metadata_high */
 	u32 toeplitz_hash_result;
@@ -363,12 +357,6 @@ struct ce_attr {
 };
 
 #ifndef CONFIG_ATH10K_SNOC
-#define SR_BA_ADDRESS		0x0000
-#define SR_SIZE_ADDRESS		0x0004
-#define DR_BA_ADDRESS		0x0008
-#define DR_SIZE_ADDRESS		0x000c
-#define CE_CMD_ADDRESS		0x0018
-
 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MSB	17
 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB	17
 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK	0x00020000
@@ -421,7 +409,6 @@ struct ce_attr {
 #define HOST_IE_COPY_COMPLETE_SET(x) \
 	(((0 | (x)) << HOST_IE_COPY_COMPLETE_LSB) & HOST_IE_COPY_COMPLETE_MASK)
 #define HOST_IE_COPY_COMPLETE_RESET		0
-#define HOST_IE_ADDRESS				0x002c
 
 #define HOST_IS_DST_RING_LOW_WATERMARK_MASK	0x00000010
 #define HOST_IS_DST_RING_HIGH_WATERMARK_MASK	0x00000008
@@ -430,8 +417,6 @@ struct ce_attr {
 #define HOST_IS_COPY_COMPLETE_MASK		0x00000001
 #define HOST_IS_ADDRESS				0x0030
 
-#define MISC_IE_ADDRESS				0x0034
-
 #define MISC_IS_AXI_ERR_MASK			0x00000400
 
 #define MISC_IS_DST_ADDR_ERR_MASK		0x00000200
@@ -442,14 +427,6 @@ struct ce_attr {
 
 #define MISC_IS_ADDRESS				0x0038
 
-#define SR_WR_INDEX_ADDRESS			0x003c
-
-#define DST_WR_INDEX_ADDRESS			0x0040
-
-#define CURRENT_SRRI_ADDRESS			0x0044
-
-#define CURRENT_DRRI_ADDRESS			0x0048
-
 #define SRC_WATERMARK_LOW_MSB			31
 #define SRC_WATERMARK_LOW_LSB			16
 #define SRC_WATERMARK_LOW_MASK			0xffff0000
@@ -542,26 +519,6 @@ struct ce_attr {
 #define WCN3990_CE11_BASE_ADDRESS \
 			WCN3990_CE11_SR_BA_LOW
 
-#define SR_BA_ADDRESS	(WCN3990_CE0_SR_BA_LOW\
-				- WCN3990_CE0_BASE_ADDRESS)
-#define SR_SIZE_ADDRESS		(WCN3990_CE0_SR_SIZE \
-					- WCN3990_CE0_BASE_ADDRESS)
-#define DR_BA_ADDRESS		(WCN3990_CE0_DR_BA_LOW\
-					- WCN3990_CE0_BASE_ADDRESS)
-#define DR_SIZE_ADDRESS		(WNC3990_CE0_DR_SIZE\
-					- WCN3990_CE0_BASE_ADDRESS)
-#define WCN3990_CE_DDR_ADDRESS_FOR_RRI_LOW \
-	(WCN3990_CE_WRAPPER_INDEX_BASE_LOW - WCN3990_CE_WRAPPER_BASE_ADDRESS)
-
-#define WCN3990_CE_DDR_ADDRESS_FOR_RRI_HIGH \
-	(WCN3990_CE_WRAPPER_INDEX_BASE_HIGH - WCN3990_CE_WRAPPER_BASE_ADDRESS)
-
-#define CE_RRI_LOW (WCN3990_CE_WRAPPER_BASE_ADDRESS \
-			 + WCN3990_CE_DDR_ADDRESS_FOR_RRI_LOW)
-
-#define CE_RRI_HIGH (WCN3990_CE_WRAPPER_BASE_ADDRESS  \
-			 + WCN3990_CE_DDR_ADDRESS_FOR_RRI_HIGH)
-
 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MSB	18
 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB	18
 
@@ -593,9 +550,6 @@ struct ce_attr {
 #define CE_CTRL1_ADDRESS	(WCN3990_CE0_CE_CTRL1 \
 					- WCN3990_CE0_BASE_ADDRESS)
 
-#define HOST_IE_ADDRESS		(WCN3990_CE0_HOST_IE\
-				- WCN3990_CE0_BASE_ADDRESS)
-
 #define HOST_IS_DST_RING_LOW_WATERMARK_MASK	0x00000010
 #define HOST_IS_DST_RING_HIGH_WATERMARK_MASK	0x00000008
 #define HOST_IS_SRC_RING_LOW_WATERMARK_MASK	0x00000004
@@ -603,8 +557,6 @@ struct ce_attr {
 #define HOST_IS_COPY_COMPLETE_MASK		0x00000001
 #define HOST_IS_ADDRESS		(WCN3990_CE0_HOST_IS \
 				- WCN3990_CE0_BASE_ADDRESS)
-#define MISC_IE_ADDRESS		(WCN3990_CE0_MISC_IE \
-			- WCN3990_CE0_BASE_ADDRESS)
 
 #define MISC_IS_AXI_ERR_MASK			0x00000100
 #define MISC_IS_DST_ADDR_ERR_MASK		0x00000200
@@ -615,14 +567,6 @@ struct ce_attr {
 #define MISC_IS_ADDRESS		(WCN3990_CE0_MISC_IS \
 				- WCN3990_CE0_BASE_ADDRESS)
 
-#define SR_WR_INDEX_ADDRESS		0x3C
-#define DST_WR_INDEX_ADDRESS		0x40
-
-#define CURRENT_SRRI_ADDRESS	(WCN3990_CE0_CURRENT_SRRI\
-					- WCN3990_CE0_BASE_ADDRESS)
-#define CURRENT_DRRI_ADDRESS	(WCN3990_CE0_CURRENT_DRRI\
-					- WCN3990_CE0_BASE_ADDRESS)
-
 #define SRC_WATERMARK_LOW_MSB			0
 #define SRC_WATERMARK_LOW_LSB			16
 
diff --git a/drivers/net/wireless/ath/ath10k/core.c b/drivers/net/wireless/ath/ath10k/core.c
index 052ebd7dd26b..d37ed66d767b 100644
--- a/drivers/net/wireless/ath/ath10k/core.c
+++ b/drivers/net/wireless/ath/ath10k/core.c
@@ -2324,28 +2324,34 @@ struct ath10k *ath10k_core_create(size_t priv_size, struct device *dev,
 	case ATH10K_HW_QCA988X:
 	case ATH10K_HW_QCA9887:
 		ar->regs = &qca988x_regs;
+		ar->hw_ce_regs = &qcax_ce_regs;
 		ar->hw_values = &qca988x_values;
 		break;
 	case ATH10K_HW_QCA6174:
 	case ATH10K_HW_QCA9377:
 		ar->regs = &qca6174_regs;
+		ar->hw_ce_regs = &qcax_ce_regs;
 		ar->hw_values = &qca6174_values;
 		break;
 	case ATH10K_HW_QCA99X0:
 	case ATH10K_HW_QCA9984:
 		ar->regs = &qca99x0_regs;
+		ar->hw_ce_regs = &qcax_ce_regs;
 		ar->hw_values = &qca99x0_values;
 		break;
 	case ATH10K_HW_QCA9888:
 		ar->regs = &qca99x0_regs;
+		ar->hw_ce_regs = &qcax_ce_regs;
 		ar->hw_values = &qca9888_values;
 		break;
 	case ATH10K_HW_QCA4019:
 		ar->regs = &qca4019_regs;
+		ar->hw_ce_regs = &qcax_ce_regs;
 		ar->hw_values = &qca4019_values;
 		break;
 	case ATH10K_HW_WCN3990:
 		ar->regs = &wcn3990_regs;
+		ar->hw_ce_regs = &wcn3990_ce_regs;
 		ar->hw_values = &wcn3990_values;
 		/* WCN3990 chip set is non bmi based */
 		ar->is_bmi = false;
diff --git a/drivers/net/wireless/ath/ath10k/core.h b/drivers/net/wireless/ath/ath10k/core.h
index dc4cefb1177f..21c63d5d3ead 100644
--- a/drivers/net/wireless/ath/ath10k/core.h
+++ b/drivers/net/wireless/ath/ath10k/core.h
@@ -740,6 +740,7 @@ struct ath10k {
 	struct completion target_suspend;
 
 	const struct ath10k_hw_regs *regs;
+	const struct ath10k_hw_ce_regs *hw_ce_regs;
 	const struct ath10k_hw_values *hw_values;
 	struct ath10k_shadow_reg_value *shadow_reg_value;
 	struct ath10k_shadow_reg_address *shadow_reg_address;
diff --git a/drivers/net/wireless/ath/ath10k/htt.h b/drivers/net/wireless/ath/ath10k/htt.h
index b2678984f2de..6dd396430f19 100644
--- a/drivers/net/wireless/ath/ath10k/htt.h
+++ b/drivers/net/wireless/ath/ath10k/htt.h
@@ -541,6 +541,7 @@ struct htt_rx_indication_hdr {
 #define HTT_RX_INDICATION_INFO2_SERVICE_LSB     24
 
 #define HTT_WCN3990_PADDR_MASK 0x1F
+#define HTT_WCN3990_ARCH_PADDR_MASK 0x1FFFFFFFFF
 
 enum htt_rx_legacy_rate {
 	HTT_RX_OFDM_48 = 0,
@@ -865,8 +866,7 @@ struct htt_rx_offload_ind {
 
 struct htt_rx_in_ord_msdu_desc {
 #ifdef CONFIG_ATH10K_SNOC
-	__le32 msdu_paddr_lo;
-	__le32 msdu_paddr_hi;
+	__le64 msdu_paddr;
 #else
 	__le32 msdu_paddr;
 #endif
diff --git a/drivers/net/wireless/ath/ath10k/htt_rx.c b/drivers/net/wireless/ath/ath10k/htt_rx.c
index cbb61267eb10..ddf097e3a143 100644
--- a/drivers/net/wireless/ath/ath10k/htt_rx.c
+++ b/drivers/net/wireless/ath/ath10k/htt_rx.c
@@ -429,9 +429,8 @@ static int ath10k_htt_rx_pop_paddr_list(struct ath10k_htt *htt,
 
 	while (msdu_count--) {
 #ifdef CONFIG_ATH10K_SNOC
-		paddr = __le32_to_cpu(msdu_desc->msdu_paddr_lo);
-		paddr |= ((u64)(msdu_desc->msdu_paddr_hi &
-				HTT_WCN3990_PADDR_MASK) << 32);
+		paddr = __le64_to_cpu(msdu_desc->msdu_paddr);
+		paddr &= HTT_WCN3990_ARCH_PADDR_MASK;
 #else
 		paddr = __le32_to_cpu(msdu_desc->msdu_paddr);
 #endif
diff --git a/drivers/net/wireless/ath/ath10k/hw.c b/drivers/net/wireless/ath/ath10k/hw.c
index 1a8f3a388ce2..72a99148f786 100644
--- a/drivers/net/wireless/ath/ath10k/hw.c
+++ b/drivers/net/wireless/ath/ath10k/hw.c
@@ -164,6 +164,37 @@ const struct ath10k_hw_regs wcn3990_regs = {
 	.pcie_intr_fw_mask			= 0x00100000,
 };
 
+struct ath10k_hw_ce_regs wcn3990_ce_regs = {
+	.sr_base_addr		= 0x00000000,
+	.sr_size_addr		= 0x00000008,
+	.dr_base_addr		= 0x0000000c,
+	.dr_size_addr		= 0x00000014,
+	.misc_ie_addr		= 0x00000034,
+	.sr_wr_index_addr	= 0x0000003c,
+	.dst_wr_index_addr	= 0x00000040,
+	.current_srri_addr	= 0x00000044,
+	.current_drri_addr	= 0x00000048,
+	.ddr_addr_for_rri_low	= 0x00000004,
+	.ddr_addr_for_rri_high	= 0x00000008,
+	.ce_rri_low		= 0x0024C004,
+	.ce_rri_high		= 0x0024C008,
+	.host_ie_addr		= 0x0000002c,
+};
+
+struct ath10k_hw_ce_regs qcax_ce_regs = {
+	.sr_base_addr		= 0x00000000,
+	.sr_size_addr		= 0x00000004,
+	.dr_base_addr		= 0x00000008,
+	.dr_size_addr		= 0x0000000c,
+	.ce_cmd_addr		= 0x00000018,
+	.misc_ie_addr		= 0x00000034,
+	.sr_wr_index_addr	= 0x0000003c,
+	.dst_wr_index_addr	= 0x00000040,
+	.current_srri_addr	= 0x00000044,
+	.current_drri_addr	= 0x00000048,
+	.host_ie_addr		= 0x0000002c,
+};
+
 const struct ath10k_hw_values qca988x_values = {
 	.rtc_state_val_on		= 3,
 	.ce_count			= 8,
diff --git a/drivers/net/wireless/ath/ath10k/hw.h b/drivers/net/wireless/ath/ath10k/hw.h
index ce87f8112928..3c2f1ee4b900 100644
--- a/drivers/net/wireless/ath/ath10k/hw.h
+++ b/drivers/net/wireless/ath/ath10k/hw.h
@@ -268,6 +268,27 @@ extern const struct ath10k_hw_regs qca99x0_regs;
 extern const struct ath10k_hw_regs qca4019_regs;
 extern const struct ath10k_hw_regs wcn3990_regs;
 
+struct ath10k_hw_ce_regs {
+	u32 sr_base_addr;
+	u32 sr_size_addr;
+	u32 dr_base_addr;
+	u32 dr_size_addr;
+	u32 ce_cmd_addr;
+	u32 misc_ie_addr;
+	u32 sr_wr_index_addr;
+	u32 dst_wr_index_addr;
+	u32 current_srri_addr;
+	u32 current_drri_addr;
+	u32 ddr_addr_for_rri_low;
+	u32 ddr_addr_for_rri_high;
+	u32 ce_rri_low;
+	u32 ce_rri_high;
+	u32 host_ie_addr;
+};
+
+extern struct ath10k_hw_ce_regs wcn3990_ce_regs;
+extern struct ath10k_hw_ce_regs qcax_ce_regs;
+
 extern struct fw_flag wcn3990_fw_flags;
 
 struct ath10k_hw_values {