diff options
| author | George Shen <sqiao@codeaurora.org> | 2016-08-19 10:25:52 -0700 |
|---|---|---|
| committer | George Shen <sqiao@codeaurora.org> | 2016-08-22 10:41:50 -0700 |
| commit | e190c549f71c6534fe52ec694b1cf7edaa967724 (patch) | |
| tree | 567ceaaa4c6d83a0dd4b191bd8f14b034cee75dc | |
| parent | c605e110ab18604981481a7b502da54640b620bc (diff) | |
ARM: dts: msm: Add GPU DCVS plan for msmcobalt V2
Add DCVS plan to support new GPU frequencies and voltage corners
on msmcobalt v2.
CRs-Fixed: 1056661
Change-Id: Ie0bde4d908189da86077b69be52c51f2a35596a8
Signed-off-by: George Shen <sqiao@codeaurora.org>
| -rw-r--r-- | arch/arm/boot/dts/qcom/msmcobalt-v2.dtsi | 85 |
1 files changed, 85 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom/msmcobalt-v2.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-v2.dtsi index 47b1ba078b7c..3aed2f924d28 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-v2.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-v2.dtsi @@ -485,3 +485,88 @@ <444000000 6000000>, <533000000 6000000>; }; + +/* GPU overrides */ +&msm_gpu { + /* Updated chip ID */ + qcom,chipid = <0x05040001>; + qcom,initial-pwrlevel = <6>; + + qcom,gpu-pwrlevels { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "qcom,gpu-pwrlevels"; + + qcom,gpu-pwrlevel@0 { + reg = <0>; + qcom,gpu-freq = <710000000>; + qcom,bus-freq = <12>; + qcom,bus-min = <12>; + qcom,bus-max = <12>; + }; + + qcom,gpu-pwrlevel@1 { + reg = <1>; + qcom,gpu-freq = <670000000>; + qcom,bus-freq = <12>; + qcom,bus-min = <11>; + qcom,bus-max = <12>; + }; + + qcom,gpu-pwrlevel@2 { + reg = <2>; + qcom,gpu-freq = <596000000>; + qcom,bus-freq = <11>; + qcom,bus-min = <9>; + qcom,bus-max = <12>; + }; + + qcom,gpu-pwrlevel@3 { + reg = <3>; + qcom,gpu-freq = <515000000>; + qcom,bus-freq = <11>; + qcom,bus-min = <9>; + qcom,bus-max = <12>; + }; + + qcom,gpu-pwrlevel@4 { + reg = <4>; + qcom,gpu-freq = <414000000>; + qcom,bus-freq = <9>; + qcom,bus-min = <8>; + qcom,bus-max = <11>; + }; + + qcom,gpu-pwrlevel@5 { + reg = <5>; + qcom,gpu-freq = <342000000>; + qcom,bus-freq = <8>; + qcom,bus-min = <5>; + qcom,bus-max = <9>; + }; + + qcom,gpu-pwrlevel@6 { + reg = <6>; + qcom,gpu-freq = <257000000>; + qcom,bus-freq = <5>; + qcom,bus-min = <3>; + qcom,bus-max = <8>; + }; + + qcom,gpu-pwrlevel@7 { + reg = <7>; + qcom,gpu-freq = <180000000>; + qcom,bus-freq = <3>; + qcom,bus-min = <1>; + qcom,bus-max = <5>; + }; + qcom,gpu-pwrlevel@8 { + reg = <8>; + qcom,gpu-freq = <27000000>; + qcom,bus-freq = <0>; + qcom,bus-min = <0>; + qcom,bus-max = <0>; + }; + }; +}; |