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authorAbhishek Singh <absingh@codeaurora.org>2016-12-30 15:28:21 +0530
committerAshish kumar goswami <agoswa@codeaurora.org>2017-01-09 15:03:25 +0530
commite138a6e46a5df9010655ad9ae00f11830b0ea935 (patch)
treed68de01e57d99d0ba29590f23c21272ecb2e84a2
parentbd146c07dec5b6653a73a8331ede7fa67c9f8994 (diff)
qcacld-2.0: Add support for separate tx and rx chain selection
Single chain mask ini parameter is used to set both tx and rx chain if per band chainmask is supported. Add new ini parameter to set the tx chain and use the existing ini parameter to set rx chain. Change-Id: I7fa9d084d8512e6708a8a6b4ac3933801306df91 CRs-Fixed: 1107890
-rw-r--r--CORE/HDD/inc/wlan_hdd_cfg.h64
-rw-r--r--CORE/HDD/src/wlan_hdd_cfg.c34
-rw-r--r--CORE/HDD/src/wlan_hdd_main.c59
-rw-r--r--CORE/SERVICES/WMA/wma.c8
-rw-r--r--CORE/SERVICES/WMA/wma.h6
5 files changed, 126 insertions, 45 deletions
diff --git a/CORE/HDD/inc/wlan_hdd_cfg.h b/CORE/HDD/inc/wlan_hdd_cfg.h
index 6f52b255b399..9c045ced48b9 100644
--- a/CORE/HDD/inc/wlan_hdd_cfg.h
+++ b/CORE/HDD/inc/wlan_hdd_cfg.h
@@ -1359,20 +1359,62 @@ typedef enum
#define CFG_ENABLE_VHT_DYNAMIC_STA_CHAINMASK_DEFAULT (0)
/*
+ * gChainMask_2g: to set RX chainmask for 2.4GH if
+ * per band chainmask is supported
+ *
+ * Valid chain mask values.
+ * 01 - enables chain0
+ * 02 - enables chain1
+ * 03 - enables both chain 0 and chain 1
+ */
+#define CFG_RX_CHAIN_MASK_2G "gChainMask_2g"
+#define CFG_RX_CHAIN_MASK_2G_MIN (1)
+#define CFG_RX_CHAIN_MASK_2G_MAX (3)
+#define CFG_RX_CHAIN_MASK_2G_DEFAULT (3)
+
+/*
+ * gChainMask_5g: to set RX chainmask for 5GH if
+ * per band chainmask is supported
+ *
+ * Valid chain mask values.
+ * 01 - enables chain0
+ * 02 - enables chain1
+ * 03 - enables both chain 0 and chain 1
+ */
+#define CFG_RX_CHAIN_MASK_5G "gChainMask_5g"
+#define CFG_RX_CHAIN_MASK_5G_MIN (1)
+#define CFG_RX_CHAIN_MASK_5G_MAX (3)
+#define CFG_RX_CHAIN_MASK_5G_DEFAULT (3)
+
+/*
+ * gChainMask_2g_tx: to set TX chainmask for 2.4GH if
+ * per band chainmask is supported
+ *
* Valid chain mask values.
* 01 - enables chain0
* 02 - enables chain1
* 03 - enables both chain 0 and chain 1
*/
-#define CFG_CHAIN_MASK_2G "gChainMask_2g"
-#define CFG_CHAIN_MASK_2G_MIN ( 1 )
-#define CFG_CHAIN_MASK_2G_MAX ( 3 )
-#define CFG_CHAIN_MASK_2G_DEFAULT ( 3 )
+#define CFG_TX_CHAIN_MASK_2G "gChainMask_2g_tx"
+#define CFG_TX_CHAIN_MASK_2G_MIN (1)
+#define CFG_TX_CHAIN_MASK_2G_MAX (3)
+#define CFG_TX_CHAIN_MASK_2G_DEFAULT (3)
+
+/*
+ * gChainMask_5g_tx: to set TX chainmask for 5GH if
+ * per band chainmask is supported
+ *
+ * Valid chain mask values.
+ * 01 - enables chain0
+ * 02 - enables chain1
+ * 03 - enables both chain 0 and chain 1
+ */
+#define CFG_TX_CHAIN_MASK_5G "gChainMask_5g_tx"
+#define CFG_TX_CHAIN_MASK_5G_MIN (1)
+#define CFG_TX_CHAIN_MASK_5G_MAX (3)
+#define CFG_TX_CHAIN_MASK_5G_DEFAULT (3)
+
-#define CFG_CHAIN_MASK_5G "gChainMask_5g"
-#define CFG_CHAIN_MASK_5G_MIN ( 1 )
-#define CFG_CHAIN_MASK_5G_MAX ( 3 )
-#define CFG_CHAIN_MASK_5G_DEFAULT ( 3 )
/*
* NSS cfg bit definition.
* STA BIT[0:1]
@@ -4793,8 +4835,10 @@ struct hdd_config {
v_U8_t vhtRxMCS2x2;
v_U8_t vhtTxMCS2x2;
v_BOOL_t enable2x2;
- uint8_t chain_mask_2g;
- uint8_t chain_mask_5g;
+ uint8_t chain_mask_2g_rx;
+ uint8_t chain_mask_5g_rx;
+ uint8_t chain_mask_2g_tx;
+ uint8_t chain_mask_5g_tx;
uint32_t vdev_type_nss_2g;
uint32_t vdev_type_nss_5g;
v_BOOL_t txchainmask1x1;
diff --git a/CORE/HDD/src/wlan_hdd_cfg.c b/CORE/HDD/src/wlan_hdd_cfg.c
index 573059929ca5..e43e3f40b1f7 100644
--- a/CORE/HDD/src/wlan_hdd_cfg.c
+++ b/CORE/HDD/src/wlan_hdd_cfg.c
@@ -2258,19 +2258,33 @@ REG_TABLE_ENTRY g_registry_table[] =
CFG_ENABLE_VHT_DYNAMIC_STA_CHAINMASK_MIN,
CFG_ENABLE_VHT_DYNAMIC_STA_CHAINMASK_MAX),
- REG_VARIABLE( CFG_CHAIN_MASK_2G, WLAN_PARAM_Integer,
- hdd_config_t, chain_mask_2g,
+ REG_VARIABLE( CFG_RX_CHAIN_MASK_2G, WLAN_PARAM_Integer,
+ hdd_config_t, chain_mask_2g_rx,
VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT,
- CFG_CHAIN_MASK_2G_DEFAULT,
- CFG_CHAIN_MASK_2G_MIN,
- CFG_CHAIN_MASK_2G_MAX ),
+ CFG_RX_CHAIN_MASK_2G_DEFAULT,
+ CFG_RX_CHAIN_MASK_2G_MIN,
+ CFG_RX_CHAIN_MASK_2G_MAX ),
- REG_VARIABLE( CFG_CHAIN_MASK_5G, WLAN_PARAM_Integer,
- hdd_config_t, chain_mask_5g,
+ REG_VARIABLE( CFG_RX_CHAIN_MASK_5G, WLAN_PARAM_Integer,
+ hdd_config_t, chain_mask_5g_rx,
VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT,
- CFG_CHAIN_MASK_5G_DEFAULT,
- CFG_CHAIN_MASK_5G_MIN,
- CFG_CHAIN_MASK_5G_MAX ),
+ CFG_RX_CHAIN_MASK_5G_DEFAULT,
+ CFG_RX_CHAIN_MASK_5G_MIN,
+ CFG_RX_CHAIN_MASK_5G_MAX ),
+
+ REG_VARIABLE( CFG_TX_CHAIN_MASK_2G, WLAN_PARAM_Integer,
+ hdd_config_t, chain_mask_2g_tx,
+ VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT,
+ CFG_TX_CHAIN_MASK_2G_DEFAULT,
+ CFG_TX_CHAIN_MASK_2G_MIN,
+ CFG_TX_CHAIN_MASK_2G_MAX ),
+
+ REG_VARIABLE( CFG_TX_CHAIN_MASK_5G, WLAN_PARAM_Integer,
+ hdd_config_t, chain_mask_5g_tx,
+ VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT,
+ CFG_TX_CHAIN_MASK_5G_DEFAULT,
+ CFG_TX_CHAIN_MASK_5G_MIN,
+ CFG_TX_CHAIN_MASK_5G_MAX ),
REG_VARIABLE( CFG_VDEV_TYPE_NSS_2G, WLAN_PARAM_Integer,
hdd_config_t, vdev_type_nss_2g,
diff --git a/CORE/HDD/src/wlan_hdd_main.c b/CORE/HDD/src/wlan_hdd_main.c
index bd89af3cd02f..7212d52b2149 100644
--- a/CORE/HDD/src/wlan_hdd_main.c
+++ b/CORE/HDD/src/wlan_hdd_main.c
@@ -8311,66 +8311,83 @@ static void hdd_update_chain_mask_vdev_nss(hdd_context_t *hdd_ctx,
struct hdd_tgt_services *cfg)
{
hdd_config_t *cfg_ini = hdd_ctx->cfg_ini;
- uint8_t chain_mask, ret;
+ uint8_t chain_mask_rx, chain_mask_tx, ret;
uint8_t max_supp_nss = 1;
cfg_ini->enable2x2 = 0;
- chain_mask = cfg->chain_mask_2g & cfg_ini->chain_mask_2g;
- if (!chain_mask)
- chain_mask = cfg->chain_mask_2g;
- hddLog(VOS_TRACE_LEVEL_INFO,
- "%s: set 2G chain mask value %d",
- __func__, chain_mask);
+ chain_mask_rx = cfg->chain_mask_2g & cfg_ini->chain_mask_2g_rx;
+ chain_mask_tx = cfg->chain_mask_2g & cfg_ini->chain_mask_2g_tx;
+ if (!chain_mask_rx)
+ chain_mask_rx = cfg->chain_mask_2g;
+ if (!chain_mask_tx)
+ chain_mask_tx = chain_mask_rx;
+ hddLog(LOG1,
+ FL("set 2G chain mask rx %d tx %d"),
+ chain_mask_rx, chain_mask_tx);
ret = process_wma_set_command(0, WMI_PDEV_PARAM_RX_CHAIN_MASK_2G,
- chain_mask, PDEV_CMD);
+ chain_mask_rx, PDEV_CMD);
if (0 != ret) {
hddLog(VOS_TRACE_LEVEL_ERROR,
"%s: set WMI_PDEV_PARAM_RX_CHAIN_MASK_2G failed %d",
__func__, ret);
}
ret = process_wma_set_command(0, WMI_PDEV_PARAM_TX_CHAIN_MASK_2G,
- chain_mask, PDEV_CMD);
+ chain_mask_tx, PDEV_CMD);
if (0 != ret) {
hddLog(VOS_TRACE_LEVEL_ERROR,
"%s: WMI_PDEV_PARAM_TX_CHAIN_MASK_2G set failed %d",
__func__, ret);
}
- max_supp_nss += ((chain_mask & 0x3) == 0x3);
+ if (((chain_mask_rx & 0x3) == 0x3) ||
+ ((chain_mask_tx & 0x3) == 0x3))
+ max_supp_nss++;
if (max_supp_nss == 2)
cfg_ini->enable2x2 = 1;
sme_update_vdev_type_nss(hdd_ctx->hHal, max_supp_nss,
cfg_ini->vdev_type_nss_2g, eCSR_BAND_24);
- hdd_ctx->supp_2g_chain_mask = chain_mask;
+
+ if (chain_mask_rx >= chain_mask_tx)
+ hdd_ctx->supp_2g_chain_mask = chain_mask_rx;
+ else
+ hdd_ctx->supp_2g_chain_mask = chain_mask_tx;
max_supp_nss = 1;
- chain_mask = cfg->chain_mask_5g & cfg_ini->chain_mask_5g;
- if (!chain_mask)
- chain_mask = cfg->chain_mask_5g;
- hddLog(VOS_TRACE_LEVEL_INFO,
- "%s: set 5G chain mask value %d",
- __func__, chain_mask);
+ chain_mask_rx = cfg->chain_mask_5g & cfg_ini->chain_mask_5g_rx;
+ chain_mask_tx = cfg->chain_mask_5g & cfg_ini->chain_mask_5g_tx;
+ if (!chain_mask_rx)
+ chain_mask_rx = cfg->chain_mask_5g;
+ if (!chain_mask_tx)
+ chain_mask_tx = chain_mask_rx;
+ hddLog(LOG1,
+ FL("set 5G chain mask rx %d tx %d"),
+ chain_mask_rx, chain_mask_tx);
ret = process_wma_set_command(0, WMI_PDEV_PARAM_RX_CHAIN_MASK_5G,
- chain_mask, PDEV_CMD);
+ chain_mask_rx, PDEV_CMD);
if (0 != ret) {
hddLog(VOS_TRACE_LEVEL_ERROR,
"%s: set WMI_PDEV_PARAM_RX_CHAIN_MASK_5G failed %d",
__func__, ret);
}
ret = process_wma_set_command(0, WMI_PDEV_PARAM_TX_CHAIN_MASK_5G,
- chain_mask, PDEV_CMD);
+ chain_mask_tx, PDEV_CMD);
if (0 != ret) {
hddLog(VOS_TRACE_LEVEL_ERROR,
"%s: WMI_PDEV_PARAM_TX_CHAIN_MASK_5G set failed %d",
__func__, ret);
}
- max_supp_nss += ((chain_mask & 0x3) == 0x3);
+ if (((chain_mask_rx & 0x3) == 0x3) ||
+ ((chain_mask_tx & 0x3) == 0x3))
+ max_supp_nss++;
if (max_supp_nss == 2)
cfg_ini->enable2x2 = 1;
sme_update_vdev_type_nss(hdd_ctx->hHal, max_supp_nss,
cfg_ini->vdev_type_nss_5g, eCSR_BAND_5G);
- hdd_ctx->supp_5g_chain_mask = chain_mask;
+ if (chain_mask_rx >= chain_mask_tx)
+ hdd_ctx->supp_5g_chain_mask = chain_mask_rx;
+ else
+ hdd_ctx->supp_5g_chain_mask = chain_mask_tx;
hddLog(LOG1, FL("Supported chain mask 2G: %d 5G: %d"),
hdd_ctx->supp_2g_chain_mask,
hdd_ctx->supp_5g_chain_mask);
diff --git a/CORE/SERVICES/WMA/wma.c b/CORE/SERVICES/WMA/wma.c
index b3000528e3df..aa91f0f7ecc3 100644
--- a/CORE/SERVICES/WMA/wma.c
+++ b/CORE/SERVICES/WMA/wma.c
@@ -16236,12 +16236,16 @@ static void wma_process_cli_set_cmd(tp_wma_handle wma,
wma->pdevconfig.rxchainmask = privcmd->param_value;
break;
case WMI_PDEV_PARAM_TX_CHAIN_MASK_2G:
+ wma->pdevconfig.chainmask_2g_tx = privcmd->param_value;
+ break;
case WMI_PDEV_PARAM_RX_CHAIN_MASK_2G:
- wma->pdevconfig.chainmask_2g = privcmd->param_value;
+ wma->pdevconfig.chainmask_2g_rx = privcmd->param_value;
break;
case WMI_PDEV_PARAM_TX_CHAIN_MASK_5G:
+ wma->pdevconfig.chainmask_5g_tx = privcmd->param_value;
+ break;
case WMI_PDEV_PARAM_RX_CHAIN_MASK_5G:
- wma->pdevconfig.chainmask_5g = privcmd->param_value;
+ wma->pdevconfig.chainmask_5g_rx = privcmd->param_value;
break;
case WMI_PDEV_PARAM_BURST_ENABLE:
wma->pdevconfig.burst_enable = privcmd->param_value;
diff --git a/CORE/SERVICES/WMA/wma.h b/CORE/SERVICES/WMA/wma.h
index d7197aaf3da8..d42030a99715 100644
--- a/CORE/SERVICES/WMA/wma.h
+++ b/CORE/SERVICES/WMA/wma.h
@@ -467,8 +467,10 @@ typedef struct {
u_int32_t txpow5g;
u_int32_t burst_enable;
u_int32_t burst_dur;
- u_int32_t chainmask_2g;
- u_int32_t chainmask_5g;
+ u_int32_t chainmask_2g_tx;
+ u_int32_t chainmask_5g_tx;
+ u_int32_t chainmask_2g_rx;
+ u_int32_t chainmask_5g_rx;
} pdev_cli_config_t;
typedef struct {