msm: mdss: Use DT offsets for post-processing

Change post-processing code to use device tree offsets when reading from
and writing to post-processing registers. The device tree defines the bases
of hardware blocks, and previously these bases were hardcoded. Now they are
parsed dynamically from the DT so that the post-processing code is scalable
for different targets

Change-Id: Ic503889459f7793ea68af4128d2d0955e6f6bef2
Signed-off-by: Carl Vanderlip <carlv@codeaurora.org>
Signed-off-by: Benet Clark <benetc@codeaurora.org>

1 files changed, 338 insertions, 315 deletions

diff --git a/drivers/video/fbdev/msm/mdss_mdp_pp.c b/drivers/video/fbdev/msm/mdss_mdp_pp.c
index b574d5d11fb8..6849edfc7f6c 100644
--- a/drivers/video/fbdev/msm/mdss_mdp_pp.c
+++ b/drivers/video/fbdev/msm/mdss_mdp_pp.c
@@ -256,36 +256,36 @@ struct mdss_pp_res_type {
 static DEFINE_MUTEX(mdss_pp_mutex);
 static struct mdss_pp_res_type *mdss_pp_res;
 
-static void pp_hist_read(char __iomem *v_base,
+static void pp_hist_read(char __iomem *v_addr,
 				struct pp_hist_col_info *hist_info);
 static int pp_histogram_setup(u32 *op, u32 block, struct mdss_mdp_mixer *mix);
 static int pp_histogram_disable(struct pp_hist_col_info *hist_info,
 					u32 done_bit, char __iomem *ctl_base);
-static void pp_update_pcc_regs(u32 offset,
+static void pp_update_pcc_regs(char __iomem *addr,
 				struct mdp_pcc_cfg_data *cfg_ptr);
 static void pp_update_igc_lut(struct mdp_igc_lut_data *cfg,
-				u32 offset, u32 blk_idx);
-static void pp_update_gc_one_lut(u32 offset,
+				char __iomem *addr, u32 blk_idx);
+static void pp_update_gc_one_lut(char __iomem *addr,
 				struct mdp_ar_gc_lut_data *lut_data,
 				uint8_t num_stages);
-static void pp_update_argc_lut(u32 offset,
+static void pp_update_argc_lut(char __iomem *addr,
 				struct mdp_pgc_lut_data *config);
 static void pp_update_hist_lut(char __iomem *base,
 				struct mdp_hist_lut_data *cfg);
-static void pp_pa_config(unsigned long flags, u32 base,
+static void pp_pa_config(unsigned long flags, char __iomem *addr,
 				struct pp_sts_type *pp_sts,
 				struct mdp_pa_cfg *pa_config);
-static void pp_pcc_config(unsigned long flags, u32 base,
+static void pp_pcc_config(unsigned long flags, char __iomem *addr,
 				struct pp_sts_type *pp_sts,
 				struct mdp_pcc_cfg_data *pcc_config);
-static void pp_igc_config(unsigned long flags, u32 base,
+static void pp_igc_config(unsigned long flags, char __iomem *addr,
 				struct pp_sts_type *pp_sts,
 				struct mdp_igc_lut_data *igc_config,
 				u32 pipe_num);
-static void pp_enhist_config(unsigned long flags, char __iomem *base,
+static void pp_enhist_config(unsigned long flags, char __iomem *addr,
 				struct pp_sts_type *pp_sts,
 				struct mdp_hist_lut_data *enhist_cfg);
-static void pp_sharp_config(char __iomem *offset,
+static void pp_sharp_config(char __iomem *addr,
 				struct pp_sts_type *pp_sts,
 				struct mdp_sharp_cfg *sharp_config);
 static int mdss_ad_init_checks(struct msm_fb_data_type *mfd);
@@ -297,7 +297,7 @@ static void pp_ad_cfg_write(struct mdss_ad_info *ad);
 static void pp_ad_init_write(struct mdss_ad_info *ad);
 static void pp_ad_input_write(struct mdss_ad_info *ad, u32 bl_lvl);
 static int mdss_mdp_ad_setup(struct msm_fb_data_type *mfd);
-static void pp_ad_cfg_lut(char __iomem *offset, u32 *data);
+static void pp_ad_cfg_lut(char __iomem *addr, u32 *data);
 
 static u32 last_sts, last_state;
 
@@ -305,7 +305,7 @@ int mdss_mdp_csc_setup_data(u32 block, u32 blk_idx, u32 tbl_idx,
 				   struct mdp_csc_cfg *data)
 {
 	int i, ret = 0;
-	char __iomem *base, *off;
+	char __iomem *base, *addr;
 	u32 val = 0;
 	struct mdss_data_type *mdata;
 	struct mdss_mdp_pipe *pipe;
@@ -348,33 +348,33 @@ int mdss_mdp_csc_setup_data(u32 block, u32 blk_idx, u32 tbl_idx,
 		return ret;
 	}
 
-	off = base + CSC_MV_OFF;
+	addr = base + CSC_MV_OFF;
 	for (i = 0; i < 9; i++) {
 		if (i & 0x1) {
 			val |= data->csc_mv[i] << 16;
-			writel_relaxed(val, off);
-			off += sizeof(u32 *);
+			writel_relaxed(val, addr);
+			addr += sizeof(u32 *);
 		} else {
 			val = data->csc_mv[i];
 		}
 	}
-	writel_relaxed(val, off); /* COEFF_33 */
+	writel_relaxed(val, addr); /* COEFF_33 */
 
-	off = base + CSC_BV_OFF;
+	addr = base + CSC_BV_OFF;
 	for (i = 0; i < 3; i++) {
-		writel_relaxed(data->csc_pre_bv[i], off);
-		writel_relaxed(data->csc_post_bv[i], off + CSC_POST_OFF);
-		off += sizeof(u32 *);
+		writel_relaxed(data->csc_pre_bv[i], addr);
+		writel_relaxed(data->csc_post_bv[i], addr + CSC_POST_OFF);
+		addr += sizeof(u32 *);
 	}
 
-	off = base + CSC_LV_OFF;
+	addr = base + CSC_LV_OFF;
 	for (i = 0; i < 6; i += 2) {
 		val = (data->csc_pre_lv[i] << 8) | data->csc_pre_lv[i+1];
-		writel_relaxed(val, off);
+		writel_relaxed(val, addr);
 
 		val = (data->csc_post_lv[i] << 8) | data->csc_post_lv[i+1];
-		writel_relaxed(val, off + CSC_POST_OFF);
-		off += sizeof(u32 *);
+		writel_relaxed(val, addr + CSC_POST_OFF);
+		addr += sizeof(u32 *);
 	}
 
 	return ret;
@@ -397,29 +397,29 @@ int mdss_mdp_csc_setup(u32 block, u32 blk_idx, u32 tbl_idx, u32 csc_type)
 }
 
 static void pp_gamut_config(struct mdp_gamut_cfg_data *gamut_cfg,
-				u32 base, struct pp_sts_type *pp_sts)
+				char __iomem *base, struct pp_sts_type *pp_sts)
 {
-	u32 offset;
+	char __iomem *addr;
 	int i, j;
 	if (gamut_cfg->flags & MDP_PP_OPS_WRITE) {
-		offset = base + MDSS_MDP_REG_DSPP_GAMUT_BASE;
+		addr = base + MDSS_MDP_REG_DSPP_GAMUT_BASE;
 		for (i = 0; i < MDP_GAMUT_TABLE_NUM; i++) {
 			for (j = 0; j < gamut_cfg->tbl_size[i]; j++)
-				MDSS_MDP_REG_WRITE(offset,
-					(u32)gamut_cfg->r_tbl[i][j]);
-			offset += 4;
+				writel_relaxed((u32)gamut_cfg->r_tbl[i][j],
+						addr);
+			addr += 4;
 		}
 		for (i = 0; i < MDP_GAMUT_TABLE_NUM; i++) {
 			for (j = 0; j < gamut_cfg->tbl_size[i]; j++)
-				MDSS_MDP_REG_WRITE(offset,
-					(u32)gamut_cfg->g_tbl[i][j]);
-			offset += 4;
+				writel_relaxed((u32)gamut_cfg->g_tbl[i][j],
+						addr);
+			addr += 4;
 		}
 		for (i = 0; i < MDP_GAMUT_TABLE_NUM; i++) {
 			for (j = 0; j < gamut_cfg->tbl_size[i]; j++)
-				MDSS_MDP_REG_WRITE(offset,
-					(u32)gamut_cfg->b_tbl[i][j]);
-			offset += 4;
+				writel_relaxed((u32)gamut_cfg->b_tbl[i][j],
+						addr);
+			addr += 4;
 		}
 		if (gamut_cfg->gamut_first)
 			pp_sts->gamut_sts |= PP_STS_GAMUT_FIRST;
@@ -431,19 +431,19 @@ static void pp_gamut_config(struct mdp_gamut_cfg_data *gamut_cfg,
 		pp_sts->gamut_sts |= PP_STS_ENABLE;
 }
 
-static void pp_pa_config(unsigned long flags, u32 base,
+static void pp_pa_config(unsigned long flags, char __iomem *addr,
 				struct pp_sts_type *pp_sts,
 				struct mdp_pa_cfg *pa_config)
 {
 	if (flags & PP_FLAGS_DIRTY_PA) {
 		if (pa_config->flags & MDP_PP_OPS_WRITE) {
-			MDSS_MDP_REG_WRITE(base, pa_config->hue_adj);
-			base += 4;
-			MDSS_MDP_REG_WRITE(base, pa_config->sat_adj);
-			base += 4;
-			MDSS_MDP_REG_WRITE(base, pa_config->val_adj);
-			base += 4;
-			MDSS_MDP_REG_WRITE(base, pa_config->cont_adj);
+			writel_relaxed(pa_config->hue_adj, addr);
+			addr += 4;
+			writel_relaxed(pa_config->sat_adj, addr);
+			addr += 4;
+			writel_relaxed(pa_config->val_adj, addr);
+			addr += 4;
+			writel_relaxed(pa_config->cont_adj, addr);
 		}
 		if (pa_config->flags & MDP_PP_OPS_DISABLE)
 			pp_sts->pa_sts &= ~PP_STS_ENABLE;
@@ -452,13 +452,13 @@ static void pp_pa_config(unsigned long flags, u32 base,
 	}
 }
 
-static void pp_pcc_config(unsigned long flags, u32 base,
+static void pp_pcc_config(unsigned long flags, char __iomem *addr,
 				struct pp_sts_type *pp_sts,
 				struct mdp_pcc_cfg_data *pcc_config)
 {
 	if (flags & PP_FLAGS_DIRTY_PCC) {
 		if (pcc_config->ops & MDP_PP_OPS_WRITE)
-			pp_update_pcc_regs(base, pcc_config);
+			pp_update_pcc_regs(addr, pcc_config);
 
 		if (pcc_config->ops & MDP_PP_OPS_DISABLE)
 			pp_sts->pcc_sts &= ~PP_STS_ENABLE;
@@ -467,7 +467,7 @@ static void pp_pcc_config(unsigned long flags, u32 base,
 	}
 }
 
-static void pp_igc_config(unsigned long flags, u32 base,
+static void pp_igc_config(unsigned long flags, char __iomem *addr,
 				struct pp_sts_type *pp_sts,
 				struct mdp_igc_lut_data *igc_config,
 				u32 pipe_num)
@@ -475,7 +475,7 @@ static void pp_igc_config(unsigned long flags, u32 base,
 	u32 tbl_idx;
 	if (flags & PP_FLAGS_DIRTY_IGC) {
 		if (igc_config->ops & MDP_PP_OPS_WRITE)
-			pp_update_igc_lut(igc_config, base, pipe_num);
+			pp_update_igc_lut(igc_config, addr, pipe_num);
 
 		if (igc_config->ops & MDP_PP_IGC_FLAG_ROM0) {
 			pp_sts->pcc_sts |= PP_STS_ENABLE;
@@ -494,13 +494,13 @@ static void pp_igc_config(unsigned long flags, u32 base,
 	}
 }
 
-static void pp_enhist_config(unsigned long flags, char __iomem *base,
+static void pp_enhist_config(unsigned long flags, char __iomem *addr,
 				struct pp_sts_type *pp_sts,
 				struct mdp_hist_lut_data *enhist_cfg)
 {
 	if (flags & PP_FLAGS_DIRTY_ENHIST) {
 		if (enhist_cfg->ops & MDP_PP_OPS_WRITE)
-			pp_update_hist_lut(base, enhist_cfg);
+			pp_update_hist_lut(addr, enhist_cfg);
 
 		if (enhist_cfg->ops & MDP_PP_OPS_DISABLE)
 			pp_sts->enhist_sts &= ~PP_STS_ENABLE;
@@ -510,18 +510,18 @@ static void pp_enhist_config(unsigned long flags, char __iomem *base,
 }
 
 /*the below function doesn't do error checking on the input params*/
-static void pp_sharp_config(char __iomem *base,
+static void pp_sharp_config(char __iomem *addr,
 				struct pp_sts_type *pp_sts,
 				struct mdp_sharp_cfg *sharp_config)
 {
 	if (sharp_config->flags & MDP_PP_OPS_WRITE) {
-		writel_relaxed(sharp_config->strength, base);
-		base += 4;
-		writel_relaxed(sharp_config->edge_thr, base);
-		base += 4;
-		writel_relaxed(sharp_config->smooth_thr, base);
-		base += 4;
-		writel_relaxed(sharp_config->noise_thr, base);
+		writel_relaxed(sharp_config->strength, addr);
+		addr += 4;
+		writel_relaxed(sharp_config->edge_thr, addr);
+		addr += 4;
+		writel_relaxed(sharp_config->smooth_thr, addr);
+		addr += 4;
+		writel_relaxed(sharp_config->noise_thr, addr);
 	}
 	if (sharp_config->flags & MDP_PP_OPS_DISABLE)
 		pp_sts->sharp_sts &= ~PP_STS_ENABLE;
@@ -532,7 +532,7 @@ static void pp_sharp_config(char __iomem *base,
 
 static int pp_vig_pipe_setup(struct mdss_mdp_pipe *pipe, u32 *op)
 {
-	u32 opmode = 0, base = 0;
+	u32 opmode = 0;
 	unsigned long flags = 0;
 	char __iomem *offset;
 
@@ -573,10 +573,10 @@ static int pp_vig_pipe_setup(struct mdss_mdp_pipe *pipe, u32 *op)
 	if (pipe->flags & MDP_OVERLAY_PP_CFG_EN) {
 		if (pipe->pp_cfg.config_ops & MDP_OVERLAY_PP_PA_CFG) {
 			flags = PP_FLAGS_DIRTY_PA;
-			base = MDSS_MDP_REG_SSPP_OFFSET(pipe->num) +
-				MDSS_MDP_REG_VIG_PA_BASE;
-			pp_pa_config(flags, base, &pipe->pp_res.pp_sts,
-					&pipe->pp_cfg.pa_cfg);
+			pp_pa_config(flags,
+				pipe->base + MDSS_MDP_REG_VIG_PA_BASE,
+				&pipe->pp_res.pp_sts,
+				&pipe->pp_cfg.pa_cfg);
 
 			if (pipe->pp_res.pp_sts.pa_sts & PP_STS_ENABLE)
 				opmode |= (1 << 4); /* PA_EN */
@@ -811,8 +811,9 @@ int mdss_mdp_pipe_sspp_setup(struct mdss_mdp_pipe *pipe, u32 *op)
 {
 	int ret = 0;
 	unsigned long flags = 0;
-	u32 pipe_base;
+	char __iomem *pipe_base;
 	u32 pipe_num;
+	struct mdss_data_type *mdata = mdss_mdp_get_mdata();
 
 	if (pipe == NULL)
 		return -EINVAL;
@@ -824,15 +825,15 @@ int mdss_mdp_pipe_sspp_setup(struct mdss_mdp_pipe *pipe, u32 *op)
 	 */
 	switch (pipe->type) {
 	case MDSS_MDP_PIPE_TYPE_VIG:
-		pipe_base = MDSS_MDP_REG_IGC_VIG_BASE;
+		pipe_base = mdata->mdp_base + MDSS_MDP_REG_IGC_VIG_BASE;
 		pipe_num = pipe->num - MDSS_MDP_SSPP_VIG0;
 		break;
 	case MDSS_MDP_PIPE_TYPE_RGB:
-		pipe_base = MDSS_MDP_REG_IGC_RGB_BASE;
+		pipe_base = mdata->mdp_base + MDSS_MDP_REG_IGC_RGB_BASE;
 		pipe_num = pipe->num - MDSS_MDP_SSPP_RGB0;
 		break;
 	case MDSS_MDP_PIPE_TYPE_DMA:
-		pipe_base = MDSS_MDP_REG_IGC_DMA_BASE;
+		pipe_base = mdata->mdp_base + MDSS_MDP_REG_IGC_DMA_BASE;
 		pipe_num = pipe->num - MDSS_MDP_SSPP_DMA0;
 		break;
 	default:
@@ -854,10 +855,11 @@ int mdss_mdp_pipe_sspp_setup(struct mdss_mdp_pipe *pipe, u32 *op)
 static int pp_mixer_setup(u32 disp_num,
 		struct mdss_mdp_mixer *mixer)
 {
-	u32 flags, offset, dspp_num, opmode = 0;
+	u32 flags, dspp_num, opmode = 0;
 	struct mdp_pgc_lut_data *pgc_config;
 	struct pp_sts_type *pp_sts;
 	struct mdss_mdp_ctl *ctl;
+	char __iomem *addr;
 	dspp_num = mixer->num;
 
 	if (!mixer || !mixer->ctl)
@@ -878,9 +880,9 @@ static int pp_mixer_setup(u32 disp_num,
 	if (flags & PP_FLAGS_DIRTY_ARGC) {
 		pgc_config = &mdss_pp_res->argc_disp_cfg[disp_num];
 		if (pgc_config->flags & MDP_PP_OPS_WRITE) {
-			offset = MDSS_MDP_REG_LM_OFFSET(dspp_num) +
+			addr = mixer->base +
 				MDSS_MDP_REG_LM_GC_LUT_BASE;
-			pp_update_argc_lut(offset, pgc_config);
+			pp_update_argc_lut(addr, pgc_config);
 		}
 		if (pgc_config->flags & MDP_PP_OPS_DISABLE)
 			pp_sts->argc_sts &= ~PP_STS_ENABLE;
@@ -891,15 +893,28 @@ static int pp_mixer_setup(u32 disp_num,
 	/* update LM opmode if LM needs flush */
 	if ((pp_sts->argc_sts & PP_STS_ENABLE) &&
 		(ctl->flush_bits & (BIT(6) << dspp_num))) {
-		offset = MDSS_MDP_REG_LM_OFFSET(dspp_num) +
-			MDSS_MDP_REG_LM_OP_MODE;
-		opmode = MDSS_MDP_REG_READ(offset);
+		addr = mixer->base + MDSS_MDP_REG_LM_OP_MODE;
+		opmode = readl_relaxed(addr);
 		opmode |= (1 << 0); /* GC_LUT_EN */
-		MDSS_MDP_REG_WRITE(offset, opmode);
+		writel_relaxed(opmode, addr);
 	}
 	return 0;
 }
 
+static char __iomem *mdss_mdp_get_mixer_addr_off(u32 dspp_num)
+{
+	struct mdss_data_type *mdata;
+	struct mdss_mdp_mixer *mixer;
+
+	mdata = mdss_mdp_get_mdata();
+	if (mdata->nmixers_intf <= dspp_num) {
+		pr_err("Invalid dspp_num=%d", dspp_num);
+		return ERR_PTR(-EINVAL);
+	}
+	mixer = mdata->mixer_intf + dspp_num;
+	return mixer->base;
+}
+
 static char __iomem *mdss_mdp_get_dspp_addr_off(u32 dspp_num)
 {
 	struct mdss_data_type *mdata;
@@ -973,12 +988,12 @@ error:
 
 static int pp_dspp_setup(u32 disp_num, struct mdss_mdp_mixer *mixer)
 {
-	u32 flags, base, offset, dspp_num, opmode = 0;
+	u32 flags, dspp_num, opmode = 0;
 	struct mdp_dither_cfg_data *dither_cfg;
 	struct mdp_pgc_lut_data *pgc_config;
 	struct pp_sts_type *pp_sts;
 	u32 data;
-	char __iomem *basel;
+	char __iomem *base, *addr;
 	int i, ret = 0;
 	struct mdss_data_type *mdata;
 	struct mdss_mdp_ctl *ctl;
@@ -994,8 +1009,7 @@ static int pp_dspp_setup(u32 disp_num, struct mdss_mdp_mixer *mixer)
 	if ((mixer->type != MDSS_MDP_MIXER_TYPE_INTF) ||
 		(dspp_num >= MDSS_MDP_MAX_DSPP))
 		return -EINVAL;
-	base = MDSS_MDP_REG_DSPP_OFFSET(dspp_num);
-	basel = mdss_mdp_get_dspp_addr_off(dspp_num);
+	base = mdss_mdp_get_dspp_addr_off(dspp_num);
 
 	mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_ON, false);
 
@@ -1028,14 +1042,14 @@ static int pp_dspp_setup(u32 disp_num, struct mdss_mdp_mixer *mixer)
 
 	pp_pa_config(flags, base + MDSS_MDP_REG_DSPP_PA_BASE, pp_sts,
 					&mdss_pp_res->pa_disp_cfg[disp_num]);
-
 	pp_pcc_config(flags, base + MDSS_MDP_REG_DSPP_PCC_BASE, pp_sts,
 					&mdss_pp_res->pcc_disp_cfg[disp_num]);
 
-	pp_igc_config(flags, MDSS_MDP_REG_IGC_DSPP_BASE, pp_sts,
-				&mdss_pp_res->igc_disp_cfg[disp_num], dspp_num);
+	pp_igc_config(flags, mdata->mdp_base + MDSS_MDP_REG_IGC_DSPP_BASE,
+				pp_sts, &mdss_pp_res->igc_disp_cfg[disp_num],
+				dspp_num);
 
-	pp_enhist_config(flags, basel + MDSS_MDP_REG_DSPP_HIST_LUT_BASE,
+	pp_enhist_config(flags, base + MDSS_MDP_REG_DSPP_HIST_LUT_BASE,
 			pp_sts, &mdss_pp_res->enhist_disp_cfg[disp_num]);
 
 	if (pp_sts->pa_sts & PP_STS_ENABLE)
@@ -1054,29 +1068,29 @@ static int pp_dspp_setup(u32 disp_num, struct mdss_mdp_mixer *mixer)
 				  (1 << 20); /* PA_EN */
 		if (!(pp_sts->pa_sts & PP_STS_ENABLE)) {
 			/* Program default value */
-			offset = base + MDSS_MDP_REG_DSPP_PA_BASE;
-			MDSS_MDP_REG_WRITE(offset, 0);
-			MDSS_MDP_REG_WRITE(offset + 4, 0);
-			MDSS_MDP_REG_WRITE(offset + 8, 0);
-			MDSS_MDP_REG_WRITE(offset + 12, 0);
+			addr = base + MDSS_MDP_REG_DSPP_PA_BASE;
+			writel_relaxed(0, addr);
+			writel_relaxed(0, addr + 4);
+			writel_relaxed(0, addr + 8);
+			writel_relaxed(0, addr + 12);
 		}
 	}
 	if (flags & PP_FLAGS_DIRTY_DITHER) {
 		dither_cfg = &mdss_pp_res->dither_disp_cfg[disp_num];
 		if (dither_cfg->flags & MDP_PP_OPS_WRITE) {
-			offset = base + MDSS_MDP_REG_DSPP_DITHER_DEPTH;
-			MDSS_MDP_REG_WRITE(offset,
-			  dither_depth_map[dither_cfg->g_y_depth] |
-			  (dither_depth_map[dither_cfg->b_cb_depth] << 2) |
-			  (dither_depth_map[dither_cfg->r_cr_depth] << 4));
-			offset += 0x14;
+			addr = base + MDSS_MDP_REG_DSPP_DITHER_DEPTH;
+			data = dither_depth_map[dither_cfg->g_y_depth];
+			data |= dither_depth_map[dither_cfg->b_cb_depth] << 2;
+			data |= dither_depth_map[dither_cfg->r_cr_depth] << 4;
+			writel_relaxed(data, addr);
+			addr += 0x14;
 			for (i = 0; i << 16; i += 4) {
 				data = dither_matrix[i] |
 					(dither_matrix[i + 1] << 4) |
 					(dither_matrix[i + 2] << 8) |
 					(dither_matrix[i + 3] << 12);
-				MDSS_MDP_REG_WRITE(offset, data);
-				offset += 4;
+				writel_relaxed(data, addr);
+				addr += 4;
 			}
 		}
 		if (dither_cfg->flags & MDP_PP_OPS_DISABLE)
@@ -1098,8 +1112,8 @@ static int pp_dspp_setup(u32 disp_num, struct mdss_mdp_mixer *mixer)
 	if (flags & PP_FLAGS_DIRTY_PGC) {
 		pgc_config = &mdss_pp_res->pgc_disp_cfg[disp_num];
 		if (pgc_config->flags & MDP_PP_OPS_WRITE) {
-			offset = base + MDSS_MDP_REG_DSPP_GC_BASE;
-			pp_update_argc_lut(offset, pgc_config);
+			addr = base + MDSS_MDP_REG_DSPP_GC_BASE;
+			pp_update_argc_lut(addr, pgc_config);
 		}
 		if (pgc_config->flags & MDP_PP_OPS_DISABLE)
 			pp_sts->pgc_sts &= ~PP_STS_ENABLE;
@@ -1110,7 +1124,7 @@ static int pp_dspp_setup(u32 disp_num, struct mdss_mdp_mixer *mixer)
 		opmode |= (1 << 22);
 
 flush_exit:
-	writel_relaxed(opmode, basel + MDSS_MDP_REG_DSPP_OP_MODE);
+	writel_relaxed(opmode, base + MDSS_MDP_REG_DSPP_OP_MODE);
 	mdss_mdp_ctl_write(ctl, MDSS_MDP_REG_CTL_FLUSH, BIT(13 + dspp_num));
 	wmb();
 dspp_exit:
@@ -1328,7 +1342,8 @@ int mdss_mdp_pa_config(struct mdss_mdp_ctl *ctl, struct mdp_pa_cfg_data *config,
 			u32 *copyback)
 {
 	int ret = 0;
-	u32 pa_offset, disp_num, dspp_num = 0;
+	u32 disp_num, dspp_num = 0;
+	char __iomem *pa_addr;
 
 	if (!ctl)
 		return -EINVAL;
@@ -1348,15 +1363,15 @@ int mdss_mdp_pa_config(struct mdss_mdp_ctl *ctl, struct mdp_pa_cfg_data *config,
 			goto pa_config_exit;
 		}
 		mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_ON, false);
-		pa_offset = MDSS_MDP_REG_DSPP_OFFSET(dspp_num) +
+		pa_addr = mdss_mdp_get_dspp_addr_off(dspp_num) +
 			  MDSS_MDP_REG_DSPP_PA_BASE;
-		config->pa_data.hue_adj = MDSS_MDP_REG_READ(pa_offset);
-		pa_offset += 4;
-		config->pa_data.sat_adj = MDSS_MDP_REG_READ(pa_offset);
-		pa_offset += 4;
-		config->pa_data.val_adj = MDSS_MDP_REG_READ(pa_offset);
-		pa_offset += 4;
-		config->pa_data.cont_adj = MDSS_MDP_REG_READ(pa_offset);
+		config->pa_data.hue_adj = readl_relaxed(pa_addr);
+		pa_addr += 4;
+		config->pa_data.sat_adj = readl_relaxed(pa_addr);
+		pa_addr += 4;
+		config->pa_data.val_adj = readl_relaxed(pa_addr);
+		pa_addr += 4;
+		config->pa_data.cont_adj = readl_relaxed(pa_addr);
 		*copyback = 1;
 		mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
 	} else {
@@ -1371,130 +1386,130 @@ pa_config_exit:
 	return ret;
 }
 
-static void pp_read_pcc_regs(u32 offset,
+static void pp_read_pcc_regs(char __iomem *addr,
 				struct mdp_pcc_cfg_data *cfg_ptr)
 {
-	cfg_ptr->r.c = MDSS_MDP_REG_READ(offset);
-	cfg_ptr->g.c = MDSS_MDP_REG_READ(offset + 4);
-	cfg_ptr->b.c = MDSS_MDP_REG_READ(offset + 8);
-	offset += 0x10;
-
-	cfg_ptr->r.r = MDSS_MDP_REG_READ(offset);
-	cfg_ptr->g.r = MDSS_MDP_REG_READ(offset + 4);
-	cfg_ptr->b.r = MDSS_MDP_REG_READ(offset + 8);
-	offset += 0x10;
-
-	cfg_ptr->r.g = MDSS_MDP_REG_READ(offset);
-	cfg_ptr->g.g = MDSS_MDP_REG_READ(offset + 4);
-	cfg_ptr->b.g = MDSS_MDP_REG_READ(offset + 8);
-	offset += 0x10;
-
-	cfg_ptr->r.b = MDSS_MDP_REG_READ(offset);
-	cfg_ptr->g.b = MDSS_MDP_REG_READ(offset + 4);
-	cfg_ptr->b.b = MDSS_MDP_REG_READ(offset + 8);
-	offset += 0x10;
-
-	cfg_ptr->r.rr = MDSS_MDP_REG_READ(offset);
-	cfg_ptr->g.rr = MDSS_MDP_REG_READ(offset + 4);
-	cfg_ptr->b.rr = MDSS_MDP_REG_READ(offset + 8);
-	offset += 0x10;
-
-	cfg_ptr->r.rg = MDSS_MDP_REG_READ(offset);
-	cfg_ptr->g.rg = MDSS_MDP_REG_READ(offset + 4);
-	cfg_ptr->b.rg = MDSS_MDP_REG_READ(offset + 8);
-	offset += 0x10;
-
-	cfg_ptr->r.rb = MDSS_MDP_REG_READ(offset);
-	cfg_ptr->g.rb = MDSS_MDP_REG_READ(offset + 4);
-	cfg_ptr->b.rb = MDSS_MDP_REG_READ(offset + 8);
-	offset += 0x10;
-
-	cfg_ptr->r.gg = MDSS_MDP_REG_READ(offset);
-	cfg_ptr->g.gg = MDSS_MDP_REG_READ(offset + 4);
-	cfg_ptr->b.gg = MDSS_MDP_REG_READ(offset + 8);
-	offset += 0x10;
-
-	cfg_ptr->r.gb = MDSS_MDP_REG_READ(offset);
-	cfg_ptr->g.gb = MDSS_MDP_REG_READ(offset + 4);
-	cfg_ptr->b.gb = MDSS_MDP_REG_READ(offset + 8);
-	offset += 0x10;
-
-	cfg_ptr->r.bb = MDSS_MDP_REG_READ(offset);
-	cfg_ptr->g.bb = MDSS_MDP_REG_READ(offset + 4);
-	cfg_ptr->b.bb = MDSS_MDP_REG_READ(offset + 8);
-	offset += 0x10;
-
-	cfg_ptr->r.rgb_0 = MDSS_MDP_REG_READ(offset);
-	cfg_ptr->g.rgb_0 = MDSS_MDP_REG_READ(offset + 4);
-	cfg_ptr->b.rgb_0 = MDSS_MDP_REG_READ(offset + 8);
-	offset += 0x10;
-
-	cfg_ptr->r.rgb_1 = MDSS_MDP_REG_READ(offset);
-	cfg_ptr->g.rgb_1 = MDSS_MDP_REG_READ(offset + 4);
-	cfg_ptr->b.rgb_1 = MDSS_MDP_REG_READ(offset + 8);
-}
-
-static void pp_update_pcc_regs(u32 offset,
+	cfg_ptr->r.c = readl_relaxed(addr);
+	cfg_ptr->g.c = readl_relaxed(addr + 4);
+	cfg_ptr->b.c = readl_relaxed(addr + 8);
+	addr += 0x10;
+
+	cfg_ptr->r.r = readl_relaxed(addr);
+	cfg_ptr->g.r = readl_relaxed(addr + 4);
+	cfg_ptr->b.r = readl_relaxed(addr + 8);
+	addr += 0x10;
+
+	cfg_ptr->r.g = readl_relaxed(addr);
+	cfg_ptr->g.g = readl_relaxed(addr + 4);
+	cfg_ptr->b.g = readl_relaxed(addr + 8);
+	addr += 0x10;
+
+	cfg_ptr->r.b = readl_relaxed(addr);
+	cfg_ptr->g.b = readl_relaxed(addr + 4);
+	cfg_ptr->b.b = readl_relaxed(addr + 8);
+	addr += 0x10;
+
+	cfg_ptr->r.rr = readl_relaxed(addr);
+	cfg_ptr->g.rr = readl_relaxed(addr + 4);
+	cfg_ptr->b.rr = readl_relaxed(addr + 8);
+	addr += 0x10;
+
+	cfg_ptr->r.rg = readl_relaxed(addr);
+	cfg_ptr->g.rg = readl_relaxed(addr + 4);
+	cfg_ptr->b.rg = readl_relaxed(addr + 8);
+	addr += 0x10;
+
+	cfg_ptr->r.rb = readl_relaxed(addr);
+	cfg_ptr->g.rb = readl_relaxed(addr + 4);
+	cfg_ptr->b.rb = readl_relaxed(addr + 8);
+	addr += 0x10;
+
+	cfg_ptr->r.gg = readl_relaxed(addr);
+	cfg_ptr->g.gg = readl_relaxed(addr + 4);
+	cfg_ptr->b.gg = readl_relaxed(addr + 8);
+	addr += 0x10;
+
+	cfg_ptr->r.gb = readl_relaxed(addr);
+	cfg_ptr->g.gb = readl_relaxed(addr + 4);
+	cfg_ptr->b.gb = readl_relaxed(addr + 8);
+	addr += 0x10;
+
+	cfg_ptr->r.bb = readl_relaxed(addr);
+	cfg_ptr->g.bb = readl_relaxed(addr + 4);
+	cfg_ptr->b.bb = readl_relaxed(addr + 8);
+	addr += 0x10;
+
+	cfg_ptr->r.rgb_0 = readl_relaxed(addr);
+	cfg_ptr->g.rgb_0 = readl_relaxed(addr + 4);
+	cfg_ptr->b.rgb_0 = readl_relaxed(addr + 8);
+	addr += 0x10;
+
+	cfg_ptr->r.rgb_1 = readl_relaxed(addr);
+	cfg_ptr->g.rgb_1 = readl_relaxed(addr + 4);
+	cfg_ptr->b.rgb_1 = readl_relaxed(addr + 8);
+}
+
+static void pp_update_pcc_regs(char __iomem *addr,
 				struct mdp_pcc_cfg_data *cfg_ptr)
 {
-	MDSS_MDP_REG_WRITE(offset, cfg_ptr->r.c);
-	MDSS_MDP_REG_WRITE(offset + 4, cfg_ptr->g.c);
-	MDSS_MDP_REG_WRITE(offset + 8, cfg_ptr->b.c);
-	offset += 0x10;
-
-	MDSS_MDP_REG_WRITE(offset, cfg_ptr->r.r);
-	MDSS_MDP_REG_WRITE(offset + 4, cfg_ptr->g.r);
-	MDSS_MDP_REG_WRITE(offset + 8, cfg_ptr->b.r);
-	offset += 0x10;
-
-	MDSS_MDP_REG_WRITE(offset, cfg_ptr->r.g);
-	MDSS_MDP_REG_WRITE(offset + 4, cfg_ptr->g.g);
-	MDSS_MDP_REG_WRITE(offset + 8, cfg_ptr->b.g);
-	offset += 0x10;
-
-	MDSS_MDP_REG_WRITE(offset, cfg_ptr->r.b);
-	MDSS_MDP_REG_WRITE(offset + 4, cfg_ptr->g.b);
-	MDSS_MDP_REG_WRITE(offset + 8, cfg_ptr->b.b);
-	offset += 0x10;
-
-	MDSS_MDP_REG_WRITE(offset, cfg_ptr->r.rr);
-	MDSS_MDP_REG_WRITE(offset + 4, cfg_ptr->g.rr);
-	MDSS_MDP_REG_WRITE(offset + 8, cfg_ptr->b.rr);
-	offset += 0x10;
-
-	MDSS_MDP_REG_WRITE(offset, cfg_ptr->r.rg);
-	MDSS_MDP_REG_WRITE(offset + 4, cfg_ptr->g.rg);
-	MDSS_MDP_REG_WRITE(offset + 8, cfg_ptr->b.rg);
-	offset += 0x10;
-
-	MDSS_MDP_REG_WRITE(offset, cfg_ptr->r.rb);
-	MDSS_MDP_REG_WRITE(offset + 4, cfg_ptr->g.rb);
-	MDSS_MDP_REG_WRITE(offset + 8, cfg_ptr->b.rb);
-	offset += 0x10;
-
-	MDSS_MDP_REG_WRITE(offset, cfg_ptr->r.gg);
-	MDSS_MDP_REG_WRITE(offset + 4, cfg_ptr->g.gg);
-	MDSS_MDP_REG_WRITE(offset + 8, cfg_ptr->b.gg);
-	offset += 0x10;
-
-	MDSS_MDP_REG_WRITE(offset, cfg_ptr->r.gb);
-	MDSS_MDP_REG_WRITE(offset + 4, cfg_ptr->g.gb);
-	MDSS_MDP_REG_WRITE(offset + 8, cfg_ptr->b.gb);
-	offset += 0x10;
-
-	MDSS_MDP_REG_WRITE(offset, cfg_ptr->r.bb);
-	MDSS_MDP_REG_WRITE(offset + 4, cfg_ptr->g.bb);
-	MDSS_MDP_REG_WRITE(offset + 8, cfg_ptr->b.bb);
-	offset += 0x10;
-
-	MDSS_MDP_REG_WRITE(offset, cfg_ptr->r.rgb_0);
-	MDSS_MDP_REG_WRITE(offset + 4, cfg_ptr->g.rgb_0);
-	MDSS_MDP_REG_WRITE(offset + 8, cfg_ptr->b.rgb_0);
-	offset += 0x10;
-
-	MDSS_MDP_REG_WRITE(offset, cfg_ptr->r.rgb_1);
-	MDSS_MDP_REG_WRITE(offset + 4, cfg_ptr->g.rgb_1);
-	MDSS_MDP_REG_WRITE(offset + 8, cfg_ptr->b.rgb_1);
+	writel_relaxed(cfg_ptr->r.c, addr);
+	writel_relaxed(cfg_ptr->g.c, addr + 4);
+	writel_relaxed(cfg_ptr->b.c, addr + 8);
+	addr += 0x10;
+
+	writel_relaxed(cfg_ptr->r.r, addr);
+	writel_relaxed(cfg_ptr->g.r, addr + 4);
+	writel_relaxed(cfg_ptr->b.r, addr + 8);
+	addr += 0x10;
+
+	writel_relaxed(cfg_ptr->r.g, addr);
+	writel_relaxed(cfg_ptr->g.g, addr + 4);
+	writel_relaxed(cfg_ptr->b.g, addr + 8);
+	addr += 0x10;
+
+	writel_relaxed(cfg_ptr->r.b, addr);
+	writel_relaxed(cfg_ptr->g.b, addr + 4);
+	writel_relaxed(cfg_ptr->b.b, addr + 8);
+	addr += 0x10;
+
+	writel_relaxed(cfg_ptr->r.rr, addr);
+	writel_relaxed(cfg_ptr->g.rr, addr + 4);
+	writel_relaxed(cfg_ptr->b.rr, addr + 8);
+	addr += 0x10;
+
+	writel_relaxed(cfg_ptr->r.rg, addr);
+	writel_relaxed(cfg_ptr->g.rg, addr + 4);
+	writel_relaxed(cfg_ptr->b.rg, addr + 8);
+	addr += 0x10;
+
+	writel_relaxed(cfg_ptr->r.rb, addr);
+	writel_relaxed(cfg_ptr->g.rb, addr + 4);
+	writel_relaxed(cfg_ptr->b.rb, addr + 8);
+	addr += 0x10;
+
+	writel_relaxed(cfg_ptr->r.gg, addr);
+	writel_relaxed(cfg_ptr->g.gg, addr + 4);
+	writel_relaxed(cfg_ptr->b.gg, addr + 8);
+	addr += 0x10;
+
+	writel_relaxed(cfg_ptr->r.gb, addr);
+	writel_relaxed(cfg_ptr->g.gb, addr + 4);
+	writel_relaxed(cfg_ptr->b.gb, addr + 8);
+	addr += 0x10;
+
+	writel_relaxed(cfg_ptr->r.bb, addr);
+	writel_relaxed(cfg_ptr->g.bb, addr + 4);
+	writel_relaxed(cfg_ptr->b.bb, addr + 8);
+	addr += 0x10;
+
+	writel_relaxed(cfg_ptr->r.rgb_0, addr);
+	writel_relaxed(cfg_ptr->g.rgb_0, addr + 4);
+	writel_relaxed(cfg_ptr->b.rgb_0, addr + 8);
+	addr += 0x10;
+
+	writel_relaxed(cfg_ptr->r.rgb_1, addr);
+	writel_relaxed(cfg_ptr->g.rgb_1, addr + 4);
+	writel_relaxed(cfg_ptr->b.rgb_1, addr + 8);
 }
 
 int mdss_mdp_pcc_config(struct mdss_mdp_ctl *ctl,
@@ -1502,7 +1517,8 @@ int mdss_mdp_pcc_config(struct mdss_mdp_ctl *ctl,
 					u32 *copyback)
 {
 	int ret = 0;
-	u32 base, disp_num, dspp_num = 0;
+	u32 disp_num, dspp_num = 0;
+	char __iomem *addr;
 
 	if (!ctl)
 		return -EINVAL;
@@ -1524,9 +1540,9 @@ int mdss_mdp_pcc_config(struct mdss_mdp_ctl *ctl,
 
 		mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_ON, false);
 
-		base = MDSS_MDP_REG_DSPP_OFFSET(dspp_num) +
+		addr = mdss_mdp_get_dspp_addr_off(dspp_num) +
 			  MDSS_MDP_REG_DSPP_PCC_BASE;
-		pp_read_pcc_regs(base, config);
+		pp_read_pcc_regs(addr, config);
 		*copyback = 1;
 		mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
 	} else {
@@ -1542,57 +1558,57 @@ pcc_config_exit:
 }
 
 static void pp_read_igc_lut(struct mdp_igc_lut_data *cfg,
-				u32 offset, u32 blk_idx)
+				char __iomem *addr, u32 blk_idx)
 {
 	int i;
 	u32 data;
 
 	/* INDEX_UPDATE & VALUE_UPDATEN */
 	data = (3 << 24) | (((~(1 << blk_idx)) & 0x7) << 28);
-	MDSS_MDP_REG_WRITE(offset, data);
+	writel_relaxed(data, addr);
 
 	for (i = 0; i < cfg->len; i++)
-		cfg->c0_c1_data[i] = MDSS_MDP_REG_READ(offset) & 0xFFF;
+		cfg->c0_c1_data[i] = readl_relaxed(addr) & 0xFFF;
 
-	offset += 0x4;
-	MDSS_MDP_REG_WRITE(offset, data);
+	addr += 0x4;
+	writel_relaxed(data, addr);
 	for (i = 0; i < cfg->len; i++)
-		cfg->c0_c1_data[i] |= (MDSS_MDP_REG_READ(offset) & 0xFFF) << 16;
+		cfg->c0_c1_data[i] |= (readl_relaxed(addr) & 0xFFF) << 16;
 
-	offset += 0x4;
-	MDSS_MDP_REG_WRITE(offset, data);
+	addr += 0x4;
+	writel_relaxed(data, addr);
 	for (i = 0; i < cfg->len; i++)
-		cfg->c2_data[i] = MDSS_MDP_REG_READ(offset) & 0xFFF;
+		cfg->c2_data[i] = readl_relaxed(addr) & 0xFFF;
 }
 
 static void pp_update_igc_lut(struct mdp_igc_lut_data *cfg,
-				u32 offset, u32 blk_idx)
+				char __iomem *addr, u32 blk_idx)
 {
 	int i;
 	u32 data;
 	/* INDEX_UPDATE */
 	data = (1 << 25) | (((~(1 << blk_idx)) & 0x7) << 28);
-	MDSS_MDP_REG_WRITE(offset, (cfg->c0_c1_data[0] & 0xFFF) | data);
+	writel_relaxed((cfg->c0_c1_data[0] & 0xFFF) | data, addr);
 
 	/* disable index update */
 	data &= ~(1 << 25);
 	for (i = 1; i < cfg->len; i++)
-		MDSS_MDP_REG_WRITE(offset, (cfg->c0_c1_data[i] & 0xFFF) | data);
+		writel_relaxed((cfg->c0_c1_data[i] & 0xFFF) | data, addr);
 
-	offset += 0x4;
+	addr += 0x4;
 	data |= (1 << 25);
-	MDSS_MDP_REG_WRITE(offset, ((cfg->c0_c1_data[0] >> 16) & 0xFFF) | data);
+	writel_relaxed(((cfg->c0_c1_data[0] >> 16) & 0xFFF) | data, addr);
 	data &= ~(1 << 25);
 	for (i = 1; i < cfg->len; i++)
-		MDSS_MDP_REG_WRITE(offset,
-		((cfg->c0_c1_data[i] >> 16) & 0xFFF) | data);
+		writel_relaxed(((cfg->c0_c1_data[i] >> 16) & 0xFFF) | data,
+				addr);
 
-	offset += 0x4;
+	addr += 0x4;
 	data |= (1 << 25);
-	MDSS_MDP_REG_WRITE(offset, (cfg->c2_data[0] & 0xFFF) | data);
+	writel_relaxed((cfg->c2_data[0] & 0xFFF) | data, addr);
 	data &= ~(1 << 25);
 	for (i = 1; i < cfg->len; i++)
-		MDSS_MDP_REG_WRITE(offset, (cfg->c2_data[i] & 0xFFF) | data);
+		writel_relaxed((cfg->c2_data[i] & 0xFFF) | data, addr);
 }
 
 int mdss_mdp_limited_lut_igc_config(struct mdss_mdp_ctl *ctl)
@@ -1621,8 +1637,10 @@ int mdss_mdp_igc_lut_config(struct mdss_mdp_ctl *ctl,
 					u32 *copyback, u32 copy_from_kernel)
 {
 	int ret = 0;
-	u32 tbl_idx, igc_offset, disp_num, dspp_num = 0;
+	u32 tbl_idx, disp_num, dspp_num = 0;
 	struct mdp_igc_lut_data local_cfg;
+	char __iomem *igc_addr;
+	struct mdss_data_type *mdata = mdss_mdp_get_mdata();
 
 	if (!ctl)
 		return -EINVAL;
@@ -1651,13 +1669,14 @@ int mdss_mdp_igc_lut_config(struct mdss_mdp_ctl *ctl,
 			tbl_idx = 2;
 		else
 			tbl_idx = 0;
-		igc_offset = MDSS_MDP_REG_IGC_DSPP_BASE + (0x10 * tbl_idx);
+		igc_addr = mdata->mdp_base + MDSS_MDP_REG_IGC_DSPP_BASE +
+			(0x10 * tbl_idx);
 		local_cfg = *config;
 		local_cfg.c0_c1_data =
 			&mdss_pp_res->igc_lut_c0c1[disp_num][0];
 		local_cfg.c2_data =
 			&mdss_pp_res->igc_lut_c2[disp_num][0];
-		pp_read_igc_lut(&local_cfg, igc_offset, dspp_num);
+		pp_read_igc_lut(&local_cfg, igc_addr, dspp_num);
 		if (copy_to_user(config->c0_c1_data, local_cfg.c2_data,
 			config->len * sizeof(u32))) {
 			ret = -EFAULT;
@@ -1707,116 +1726,117 @@ igc_config_exit:
 		mdss_mdp_pp_setup(ctl);
 	return ret;
 }
-static void pp_update_gc_one_lut(u32 offset,
+static void pp_update_gc_one_lut(char __iomem *addr,
 		struct mdp_ar_gc_lut_data *lut_data,
 		uint8_t num_stages)
 {
 	int i, start_idx, idx;
 
-	start_idx = (MDSS_MDP_REG_READ(offset) >> 16) & 0xF;
+	start_idx = (readl_relaxed(addr) >> 16) & 0xF;
 	for (i = start_idx; i < GC_LUT_SEGMENTS; i++) {
 		idx = min((uint8_t)i, (uint8_t)(num_stages-1));
-		MDSS_MDP_REG_WRITE(offset, lut_data[idx].x_start);
+		writel_relaxed(lut_data[idx].x_start, addr);
 	}
 	for (i = 0; i < start_idx; i++) {
 		idx = min((uint8_t)i, (uint8_t)(num_stages-1));
-		MDSS_MDP_REG_WRITE(offset, lut_data[idx].x_start);
+		writel_relaxed(lut_data[idx].x_start, addr);
 	}
-	offset += 4;
-	start_idx = (MDSS_MDP_REG_READ(offset) >> 16) & 0xF;
+	addr += 4;
+	start_idx = (readl_relaxed(addr) >> 16) & 0xF;
 	for (i = start_idx; i < GC_LUT_SEGMENTS; i++) {
 		idx = min((uint8_t)i, (uint8_t)(num_stages-1));
-		MDSS_MDP_REG_WRITE(offset, lut_data[idx].slope);
+		writel_relaxed(lut_data[idx].slope, addr);
 	}
 	for (i = 0; i < start_idx; i++) {
 		idx = min((uint8_t)i, (uint8_t)(num_stages-1));
-		MDSS_MDP_REG_WRITE(offset, lut_data[idx].slope);
+		writel_relaxed(lut_data[idx].slope, addr);
 	}
-	offset += 4;
-	start_idx = (MDSS_MDP_REG_READ(offset) >> 16) & 0xF;
+	addr += 4;
+	start_idx = (readl_relaxed(addr) >> 16) & 0xF;
 	for (i = start_idx; i < GC_LUT_SEGMENTS; i++) {
 		idx = min((uint8_t)i, (uint8_t)(num_stages-1));
-		MDSS_MDP_REG_WRITE(offset, lut_data[idx].offset);
+		writel_relaxed(lut_data[idx].offset, addr);
 	}
 	for (i = 0; i < start_idx; i++) {
 		idx = min((uint8_t)i, (uint8_t)(num_stages-1));
-		MDSS_MDP_REG_WRITE(offset, lut_data[idx].offset);
+		writel_relaxed(lut_data[idx].offset, addr);
 	}
 }
-static void pp_update_argc_lut(u32 offset, struct mdp_pgc_lut_data *config)
+static void pp_update_argc_lut(char __iomem *addr,
+				struct mdp_pgc_lut_data *config)
 {
-	pp_update_gc_one_lut(offset, config->r_data, config->num_r_stages);
-	offset += 0x10;
-	pp_update_gc_one_lut(offset, config->g_data, config->num_g_stages);
-	offset += 0x10;
-	pp_update_gc_one_lut(offset, config->b_data, config->num_b_stages);
+	pp_update_gc_one_lut(addr, config->r_data, config->num_r_stages);
+	addr += 0x10;
+	pp_update_gc_one_lut(addr, config->g_data, config->num_g_stages);
+	addr += 0x10;
+	pp_update_gc_one_lut(addr, config->b_data, config->num_b_stages);
 }
-static void pp_read_gc_one_lut(u32 offset,
+static void pp_read_gc_one_lut(char __iomem *addr,
 		struct mdp_ar_gc_lut_data *gc_data)
 {
 	int i, start_idx, data;
-	data = MDSS_MDP_REG_READ(offset);
+	data = readl_relaxed(addr);
 	start_idx = (data >> 16) & 0xF;
 	gc_data[start_idx].x_start = data & 0xFFF;
 
 	for (i = start_idx + 1; i < GC_LUT_SEGMENTS; i++) {
-		data = MDSS_MDP_REG_READ(offset);
+		data = readl_relaxed(addr);
 		gc_data[i].x_start = data & 0xFFF;
 	}
 	for (i = 0; i < start_idx; i++) {
-		data = MDSS_MDP_REG_READ(offset);
+		data = readl_relaxed(addr);
 		gc_data[i].x_start = data & 0xFFF;
 	}
 
-	offset += 4;
-	data = MDSS_MDP_REG_READ(offset);
+	addr += 4;
+	data = readl_relaxed(addr);
 	start_idx = (data >> 16) & 0xF;
 	gc_data[start_idx].slope = data & 0x7FFF;
 	for (i = start_idx + 1; i < GC_LUT_SEGMENTS; i++) {
-		data = MDSS_MDP_REG_READ(offset);
+		data = readl_relaxed(addr);
 		gc_data[i].slope = data & 0x7FFF;
 	}
 	for (i = 0; i < start_idx; i++) {
-		data = MDSS_MDP_REG_READ(offset);
+		data = readl_relaxed(addr);
 		gc_data[i].slope = data & 0x7FFF;
 	}
-	offset += 4;
-	data = MDSS_MDP_REG_READ(offset);
+	addr += 4;
+	data = readl_relaxed(addr);
 	start_idx = (data >> 16) & 0xF;
 	gc_data[start_idx].offset = data & 0x7FFF;
 	for (i = start_idx + 1; i < GC_LUT_SEGMENTS; i++) {
-		data = MDSS_MDP_REG_READ(offset);
+		data = readl_relaxed(addr);
 		gc_data[i].offset = data & 0x7FFF;
 	}
 	for (i = 0; i < start_idx; i++) {
-		data = MDSS_MDP_REG_READ(offset);
+		data = readl_relaxed(addr);
 		gc_data[i].offset = data & 0x7FFF;
 	}
 }
 
-static int pp_read_argc_lut(struct mdp_pgc_lut_data *config, u32 offset)
+static int pp_read_argc_lut(struct mdp_pgc_lut_data *config, char __iomem *addr)
 {
 	int ret = 0;
-	pp_read_gc_one_lut(offset, config->r_data);
-	offset += 0x10;
-	pp_read_gc_one_lut(offset, config->g_data);
-	offset += 0x10;
-	pp_read_gc_one_lut(offset, config->b_data);
+	pp_read_gc_one_lut(addr, config->r_data);
+	addr += 0x10;
+	pp_read_gc_one_lut(addr, config->g_data);
+	addr += 0x10;
+	pp_read_gc_one_lut(addr, config->b_data);
 	return ret;
 }
 
 /* Note: Assumes that its inputs have been checked by calling function */
-static void pp_update_hist_lut(char __iomem *offset,
+static void pp_update_hist_lut(char __iomem *addr,
 				struct mdp_hist_lut_data *cfg)
 {
 	int i;
 	for (i = 0; i < ENHIST_LUT_ENTRIES; i++)
-		writel_relaxed(cfg->data[i], offset);
+		writel_relaxed(cfg->data[i], addr);
 	/* swap */
 	if (PP_LOCAT(cfg->block) == MDSS_PP_DSPP_CFG)
-		writel_relaxed(1, offset + 4);
+		writel_relaxed(1, addr + 4);
 	else
-		writel_relaxed(1, offset + 16);
+		writel_relaxed(1, addr + 16);
 }
 
 int mdss_mdp_argc_config(struct mdss_mdp_ctl *ctl,
@@ -1824,10 +1844,11 @@ int mdss_mdp_argc_config(struct mdss_mdp_ctl *ctl,
 				u32 *copyback)
 {
 	int ret = 0;
-	u32 argc_offset = 0, disp_num, dspp_num = 0;
+	u32 disp_num, dspp_num = 0;
 	struct mdp_pgc_lut_data local_cfg;
 	struct mdp_pgc_lut_data *pgc_ptr;
 	u32 tbl_size, r_size, g_size, b_size;
+	char __iomem *argc_addr = 0;
 
 	if (!ctl)
 		return -EINVAL;
@@ -1841,14 +1862,14 @@ int mdss_mdp_argc_config(struct mdss_mdp_ctl *ctl,
 	disp_num = PP_BLOCK(config->block) - MDP_LOGICAL_BLOCK_DISP_0;
 	switch (PP_LOCAT(config->block)) {
 	case MDSS_PP_LM_CFG:
-		argc_offset = MDSS_MDP_REG_LM_OFFSET(dspp_num) +
+		argc_addr = mdss_mdp_get_mixer_addr_off(dspp_num) +
 			MDSS_MDP_REG_LM_GC_LUT_BASE;
 		pgc_ptr = &mdss_pp_res->argc_disp_cfg[disp_num];
 		mdss_pp_res->pp_disp_flags[disp_num] |=
 			PP_FLAGS_DIRTY_ARGC;
 		break;
 	case MDSS_PP_DSPP_CFG:
-		argc_offset = MDSS_MDP_REG_DSPP_OFFSET(dspp_num) +
+		argc_addr = mdss_mdp_get_dspp_addr_off(dspp_num) +
 					MDSS_MDP_REG_DSPP_GC_BASE;
 		pgc_ptr = &mdss_pp_res->pgc_disp_cfg[disp_num];
 		mdss_pp_res->pp_disp_flags[disp_num] |=
@@ -1876,7 +1897,7 @@ int mdss_mdp_argc_config(struct mdss_mdp_ctl *ctl,
 			&mdss_pp_res->gc_lut_g[disp_num][0];
 		local_cfg.b_data =
 			&mdss_pp_res->gc_lut_b[disp_num][0];
-		pp_read_argc_lut(&local_cfg, argc_offset);
+		pp_read_argc_lut(&local_cfg, argc_addr);
 		if (copy_to_user(config->r_data,
 			&mdss_pp_res->gc_lut_r[disp_num][0], tbl_size)) {
 			mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_OFF, false);
@@ -1950,7 +1971,8 @@ int mdss_mdp_hist_lut_config(struct mdss_mdp_ctl *ctl,
 					u32 *copyback)
 {
 	int i, ret = 0;
-	u32 hist_offset, disp_num, dspp_num = 0;
+	u32 disp_num, dspp_num = 0;
+	char __iomem *hist_addr;
 
 	if (!ctl)
 		return -EINVAL;
@@ -1971,11 +1993,11 @@ int mdss_mdp_hist_lut_config(struct mdss_mdp_ctl *ctl,
 		}
 		mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_ON, false);
 
-		hist_offset = MDSS_MDP_REG_DSPP_OFFSET(dspp_num) +
+		hist_addr = mdss_mdp_get_dspp_addr_off(dspp_num) +
 			  MDSS_MDP_REG_DSPP_HIST_LUT_BASE;
 		for (i = 0; i < ENHIST_LUT_ENTRIES; i++)
 			mdss_pp_res->enhist_lut[disp_num][i] =
-				MDSS_MDP_REG_READ(hist_offset);
+				readl_relaxed(hist_addr);
 		if (copy_to_user(config->data,
 			&mdss_pp_res->enhist_lut[disp_num][0],
 			ENHIST_LUT_ENTRIES * sizeof(u32))) {
@@ -2031,13 +2053,14 @@ int mdss_mdp_gamut_config(struct mdss_mdp_ctl *ctl,
 					u32 *copyback)
 {
 	int i, j, size_total = 0, ret = 0;
-	u32 offset, disp_num, dspp_num = 0;
+
+	u32 disp_num, dspp_num = 0;
 	uint16_t *tbl_off;
 	struct mdp_gamut_cfg_data local_cfg;
 	uint16_t *r_tbl[MDP_GAMUT_TABLE_NUM];
 	uint16_t *g_tbl[MDP_GAMUT_TABLE_NUM];
 	uint16_t *b_tbl[MDP_GAMUT_TABLE_NUM];
-
+	char __iomem *addr;
 
 	if (!ctl)
 		return -EINVAL;
@@ -2062,7 +2085,7 @@ int mdss_mdp_gamut_config(struct mdss_mdp_ctl *ctl,
 		}
 		mdss_mdp_clk_ctrl(MDP_BLOCK_POWER_ON, false);
 
-		offset = MDSS_MDP_REG_DSPP_OFFSET(dspp_num) +
+		addr = mdss_mdp_get_dspp_addr_off(dspp_num) +
 			  MDSS_MDP_REG_DSPP_GAMUT_BASE;
 		for (i = 0; i < MDP_GAMUT_TABLE_NUM; i++) {
 			r_tbl[i] = kzalloc(
@@ -2074,8 +2097,8 @@ int mdss_mdp_gamut_config(struct mdss_mdp_ctl *ctl,
 			}
 			for (j = 0; j < config->tbl_size[i]; j++)
 				r_tbl[i][j] =
-					(u16)MDSS_MDP_REG_READ(offset);
-			offset += 4;
+					(u16)readl_relaxed(addr);
+			addr += 4;
 			ret = copy_to_user(config->r_tbl[i], r_tbl[i],
 				     sizeof(uint16_t) * config->tbl_size[i]);
 			kfree(r_tbl[i]);
@@ -2095,8 +2118,8 @@ int mdss_mdp_gamut_config(struct mdss_mdp_ctl *ctl,
 			}
 			for (j = 0; j < config->tbl_size[i]; j++)
 				g_tbl[i][j] =
-					(u16)MDSS_MDP_REG_READ(offset);
-			offset += 4;
+					(u16)readl_relaxed(addr);
+			addr += 4;
 			ret = copy_to_user(config->g_tbl[i], g_tbl[i],
 				     sizeof(uint16_t) * config->tbl_size[i]);
 			kfree(g_tbl[i]);
@@ -2116,8 +2139,8 @@ int mdss_mdp_gamut_config(struct mdss_mdp_ctl *ctl,
 			}
 			for (j = 0; j < config->tbl_size[i]; j++)
 				b_tbl[i][j] =
-					(u16)MDSS_MDP_REG_READ(offset);
-			offset += 4;
+					(u16)readl_relaxed(addr);
+			addr += 4;
 			ret = copy_to_user(config->b_tbl[i], b_tbl[i],
 				     sizeof(uint16_t) * config->tbl_size[i]);
 			kfree(b_tbl[i]);
@@ -2168,18 +2191,18 @@ gamut_config_exit:
 		mdss_mdp_pp_setup(ctl);
 	return ret;
 }
-static void pp_hist_read(char __iomem *v_base,
+static void pp_hist_read(char __iomem *v_addr,
 				struct pp_hist_col_info *hist_info)
 {
 	int i, i_start;
 	u32 data;
-	data = readl_relaxed(v_base);
+	data = readl_relaxed(v_addr);
 	i_start = data >> 24;
 	hist_info->data[i_start] = data & 0xFFFFFF;
 	for (i = i_start + 1; i < HIST_V_SIZE; i++)
-		hist_info->data[i] = readl_relaxed(v_base) & 0xFFFFFF;
+		hist_info->data[i] = readl_relaxed(v_addr) & 0xFFFFFF;
 	for (i = 0; i < i_start - 1; i++)
-		hist_info->data[i] = readl_relaxed(v_base) & 0xFFFFFF;
+		hist_info->data[i] = readl_relaxed(v_addr) & 0xFFFFFF;
 	hist_info->hist_cnt_read++;
 }
 
@@ -3318,7 +3341,7 @@ static void pp_ad_calc_worker(struct work_struct *work)
 }
 
 #define PP_AD_LUT_LEN 33
-static void pp_ad_cfg_lut(char __iomem *offset, u32 *data)
+static void pp_ad_cfg_lut(char __iomem *addr, u32 *data)
 {
 	int i;
 	u32 temp;
@@ -3326,10 +3349,10 @@ static void pp_ad_cfg_lut(char __iomem *offset, u32 *data)
 	for (i = 0; i < PP_AD_LUT_LEN - 1; i += 2) {
 		temp = data[i+1] << 16;
 		temp |= (data[i] & 0xFFFF);
-		writel_relaxed(temp, offset + (i*2));
+		writel_relaxed(temp, addr + (i*2));
 	}
 	writel_relaxed(data[PP_AD_LUT_LEN - 1] << 16,
-			offset + ((PP_AD_LUT_LEN - 1) * 2));
+			addr + ((PP_AD_LUT_LEN - 1) * 2));
 }
 
 int mdss_mdp_ad_addr_setup(struct mdss_data_type *mdata, u32 *ad_off)