diff options
| author | Padmanabhan Komanduru <pkomandu@codeaurora.org> | 2014-11-07 14:43:10 +0530 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-23 20:36:05 -0700 |
| commit | d8a026f775202dcf3fd7dbe13c46ab3b4eb84522 (patch) | |
| tree | 9cfd3fb1332a980667737eb90e6be496cbcbfd52 | |
| parent | 4dc5ccfa3b89083b3b5dbdd7f95bffcee04b710d (diff) | |
msm: mdss: fix lane configuration during DSI overflow recovery
While performing DSI overflow recovery operations, we currently
enable all the 4 DSI data lanes. For panels which have less than
4 data lanes, this might cause issues. Hence, program the
DSI_CTRL register based on the lane configuration that exists
prior to the overflow recovery operation.
Change-Id: I4131adb12169491c862033340a5f72efbd56971c
Signed-off-by: Padmanabhan Komanduru <pkomandu@codeaurora.org>
| -rw-r--r-- | drivers/video/fbdev/msm/mdss_dsi_host.c | 27 |
1 files changed, 15 insertions, 12 deletions
diff --git a/drivers/video/fbdev/msm/mdss_dsi_host.c b/drivers/video/fbdev/msm/mdss_dsi_host.c index 7647c1faedbc..7f1dae75857c 100644 --- a/drivers/video/fbdev/msm/mdss_dsi_host.c +++ b/drivers/video/fbdev/msm/mdss_dsi_host.c @@ -568,11 +568,13 @@ static void mdss_dsi_ctl_phy_reset(struct mdss_dsi_ctrl_pdata *ctrl) data0 = MIPI_INP(ctrl0->ctrl_base + 0x0004); data1 = MIPI_INP(ctrl1->ctrl_base + 0x0004); /* Disable DSI video mode */ - MIPI_OUTP(ctrl0->ctrl_base + 0x004, 0x1f5); - MIPI_OUTP(ctrl1->ctrl_base + 0x004, 0x1f5); + MIPI_OUTP(ctrl0->ctrl_base + 0x004, (data0 & ~BIT(1))); + MIPI_OUTP(ctrl1->ctrl_base + 0x004, (data1 & ~BIT(1))); /* Disable DSI controller */ - MIPI_OUTP(ctrl0->ctrl_base + 0x004, 0x1f4); - MIPI_OUTP(ctrl1->ctrl_base + 0x004, 0x1f4); + MIPI_OUTP(ctrl0->ctrl_base + 0x004, + (data0 & ~(BIT(0) | BIT(1)))); + MIPI_OUTP(ctrl1->ctrl_base + 0x004, + (data1 & ~(BIT(0) | BIT(1)))); /* "Force On" all dynamic clocks */ MIPI_OUTP(ctrl0->ctrl_base + 0x11c, 0x100a00); MIPI_OUTP(ctrl1->ctrl_base + 0x11c, 0x100a00); @@ -590,8 +592,8 @@ static void mdss_dsi_ctl_phy_reset(struct mdss_dsi_ctrl_pdata *ctrl) MIPI_OUTP(ctrl1->ctrl_base + 0x11c, 0x00); /* DSI_CLK_CTRL */ /* Enable DSI controller */ - MIPI_OUTP(ctrl0->ctrl_base + 0x004, 0x1f5); - MIPI_OUTP(ctrl1->ctrl_base + 0x004, 0x1f5); + MIPI_OUTP(ctrl0->ctrl_base + 0x004, (data0 & ~BIT(1))); + MIPI_OUTP(ctrl1->ctrl_base + 0x004, (data1 & ~BIT(1))); /* * Toggle Clk lane Force TX stop so that @@ -629,8 +631,8 @@ static void mdss_dsi_ctl_phy_reset(struct mdss_dsi_ctrl_pdata *ctrl) MIPI_OUTP(ctrl1->ctrl_base + 0x0ac, ln_ctrl1 & ~BIT(20)); /* Enable Video mode for DSI controller */ - MIPI_OUTP(ctrl0->ctrl_base + 0x004, 0x1f7); - MIPI_OUTP(ctrl1->ctrl_base + 0x004, 0x1f7); + MIPI_OUTP(ctrl0->ctrl_base + 0x004, data0); + MIPI_OUTP(ctrl1->ctrl_base + 0x004, data1); /* * Enable PHY contention detection and receive. @@ -652,9 +654,10 @@ static void mdss_dsi_ctl_phy_reset(struct mdss_dsi_ctrl_pdata *ctrl) data0 = MIPI_INP(ctrl->ctrl_base + 0x0004); /* Disable DSI video mode */ - MIPI_OUTP(ctrl->ctrl_base + 0x004, 0x1f5); + MIPI_OUTP(ctrl->ctrl_base + 0x004, (data0 & ~BIT(1))); /* Disable DSI controller */ - MIPI_OUTP(ctrl->ctrl_base + 0x004, 0x1f4); + MIPI_OUTP(ctrl->ctrl_base + 0x004, + (data0 & ~(BIT(0) | BIT(1)))); /* "Force On" all dynamic clocks */ MIPI_OUTP(ctrl->ctrl_base + 0x11c, 0x100a00); @@ -667,7 +670,7 @@ static void mdss_dsi_ctl_phy_reset(struct mdss_dsi_ctrl_pdata *ctrl) /* Remove "Force On" all dynamic clocks */ MIPI_OUTP(ctrl->ctrl_base + 0x11c, 0x00); /* Enable DSI controller */ - MIPI_OUTP(ctrl->ctrl_base + 0x004, 0x1f5); + MIPI_OUTP(ctrl->ctrl_base + 0x004, (data0 & ~BIT(1))); /* * Toggle Clk lane Force TX stop so that @@ -698,7 +701,7 @@ static void mdss_dsi_ctl_phy_reset(struct mdss_dsi_ctrl_pdata *ctrl) MIPI_OUTP(ctrl->ctrl_base + 0x0ac, ln_ctrl0 & ~BIT(20)); /* Enable Video mode for DSI controller */ - MIPI_OUTP(ctrl->ctrl_base + 0x004, 0x1f7); + MIPI_OUTP(ctrl->ctrl_base + 0x004, data0); /* Enable PHY contention detection and receiver */ MIPI_OUTP((ctrl->phy_io.base) + 0x0188, 0x6); /* |