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authorSree Sesha Aravind Vadrevu <svadrevu@codeaurora.org>2014-04-21 15:07:10 -0700
committerDavid Keitel <dkeitel@codeaurora.org>2016-03-23 20:29:21 -0700
commitd5db6c1ca941a830b239fa95505b4be86985d603 (patch)
tree6e580bd8160b450e9cea18068052630ff7ad35d2
parent05bd942a225079adb150e9772a8dc1c6d1f44fbd (diff)
msm: mdss: Support scalar programming for all usecases
Program scalar registers for both RGB and VIG pipes when requested by the user. The scalar factors are also computed by the user. Change-Id: I6854a9ff3acdef07bb6a964f2f3686612230eff3 Signed-off-by: Sree Sesha Aravind Vadrevu <svadrevu@codeaurora.org>
-rw-r--r--drivers/video/fbdev/msm/mdss_mdp_overlay.c18
-rw-r--r--drivers/video/fbdev/msm/mdss_mdp_pp.c72
2 files changed, 55 insertions, 35 deletions
diff --git a/drivers/video/fbdev/msm/mdss_mdp_overlay.c b/drivers/video/fbdev/msm/mdss_mdp_overlay.c
index 157aa5a588b4..5f4441adb3ae 100644
--- a/drivers/video/fbdev/msm/mdss_mdp_overlay.c
+++ b/drivers/video/fbdev/msm/mdss_mdp_overlay.c
@@ -397,7 +397,8 @@ static int __mdp_pipe_tune_perf(struct mdss_mdp_pipe *pipe)
* mdp clock requirement
*/
if (mdata->has_decimation && (pipe->vert_deci < MAX_DECIMATION)
- && !pipe->bwc_mode && !pipe->src_fmt->tile)
+ && !pipe->bwc_mode && !pipe->src_fmt->tile &&
+ !pipe->scale.enable_pxl_ext)
pipe->vert_deci++;
else
return -EPERM;
@@ -798,14 +799,21 @@ static int mdss_mdp_overlay_pipe_setup(struct msm_fb_data_type *mfd,
}
}
- if ((pipe->flags & MDP_DEINTERLACE) && !pipe->scale.enable_pxl_ext) {
+ /*
+ * When scaling is enabled src crop and image
+ * width and height is modified by user
+ */
+ if ((pipe->flags & MDP_DEINTERLACE)) {
if (pipe->flags & MDP_SOURCE_ROTATED_90) {
pipe->src.x = DIV_ROUND_UP(pipe->src.x, 2);
pipe->src.x &= ~1;
- pipe->src.w /= 2;
- pipe->img_width /= 2;
+ if (!pipe->scale.enable_pxl_ext) {
+ pipe->src.w /= 2;
+ pipe->img_width /= 2;
+ }
} else {
- pipe->src.h /= 2;
+ if (!pipe->scale.enable_pxl_ext)
+ pipe->src.h /= 2;
pipe->src.y = DIV_ROUND_UP(pipe->src.y, 2);
pipe->src.y &= ~1;
}
diff --git a/drivers/video/fbdev/msm/mdss_mdp_pp.c b/drivers/video/fbdev/msm/mdss_mdp_pp.c
index c91557d04843..9870e9c14475 100644
--- a/drivers/video/fbdev/msm/mdss_mdp_pp.c
+++ b/drivers/video/fbdev/msm/mdss_mdp_pp.c
@@ -1183,39 +1183,51 @@ static int mdss_mdp_scale_setup(struct mdss_mdp_pipe *pipe)
}
}
- if (pipe->scale.enable_pxl_ext &&
- pipe->type == MDSS_MDP_PIPE_TYPE_VIG) {
-
- /*program x,y initial phase and phase step*/
- writel_relaxed(pipe->scale.init_phase_x[0],
- pipe->base + MDSS_MDP_REG_VIG_QSEED2_C03_INIT_PHASEX);
- writel_relaxed(pipe->scale.phase_step_x[0],
- pipe->base + MDSS_MDP_REG_VIG_QSEED2_C03_PHASESTEPX);
- writel_relaxed(pipe->scale.init_phase_x[1],
- pipe->base + MDSS_MDP_REG_VIG_QSEED2_C12_INIT_PHASEX);
- writel_relaxed(pipe->scale.phase_step_x[1],
- pipe->base + MDSS_MDP_REG_VIG_QSEED2_C12_PHASESTEPX);
-
- writel_relaxed(pipe->scale.init_phase_y[0],
- pipe->base + MDSS_MDP_REG_VIG_QSEED2_C03_INIT_PHASEY);
- writel_relaxed(pipe->scale.phase_step_y[0],
- pipe->base + MDSS_MDP_REG_VIG_QSEED2_C03_PHASESTEPY);
- writel_relaxed(pipe->scale.init_phase_y[1],
- pipe->base + MDSS_MDP_REG_VIG_QSEED2_C12_INIT_PHASEY);
- writel_relaxed(pipe->scale.phase_step_y[1],
- pipe->base + MDSS_MDP_REG_VIG_QSEED2_C12_PHASESTEPY);
+ if (pipe->scale.enable_pxl_ext) {
+ if (pipe->type == MDSS_MDP_PIPE_TYPE_VIG) {
+ /*program x,y initial phase and phase step*/
+ writel_relaxed(pipe->scale.init_phase_x[0],
+ pipe->base +
+ MDSS_MDP_REG_VIG_QSEED2_C03_INIT_PHASEX);
+ writel_relaxed(pipe->scale.phase_step_x[0],
+ pipe->base +
+ MDSS_MDP_REG_VIG_QSEED2_C03_PHASESTEPX);
+ writel_relaxed(pipe->scale.init_phase_x[1],
+ pipe->base +
+ MDSS_MDP_REG_VIG_QSEED2_C12_INIT_PHASEX);
+ writel_relaxed(pipe->scale.phase_step_x[1],
+ pipe->base +
+ MDSS_MDP_REG_VIG_QSEED2_C12_PHASESTEPX);
+
+ writel_relaxed(pipe->scale.init_phase_y[0],
+ pipe->base +
+ MDSS_MDP_REG_VIG_QSEED2_C03_INIT_PHASEY);
+ writel_relaxed(pipe->scale.phase_step_y[0],
+ pipe->base +
+ MDSS_MDP_REG_VIG_QSEED2_C03_PHASESTEPY);
+ writel_relaxed(pipe->scale.init_phase_y[1],
+ pipe->base +
+ MDSS_MDP_REG_VIG_QSEED2_C12_INIT_PHASEY);
+ writel_relaxed(pipe->scale.phase_step_y[1],
+ pipe->base +
+ MDSS_MDP_REG_VIG_QSEED2_C12_PHASESTEPY);
+ } else {
+ writel_relaxed(pipe->scale.phase_step_x[0],
+ pipe->base +
+ MDSS_MDP_REG_SCALE_PHASE_STEP_X);
+ writel_relaxed(pipe->scale.phase_step_y[0],
+ pipe->base +
+ MDSS_MDP_REG_SCALE_PHASE_STEP_Y);
+ writel_relaxed(pipe->scale.init_phase_x[0],
+ pipe->base +
+ MDSS_MDP_REG_SCALE_INIT_PHASE_X);
+ writel_relaxed(pipe->scale.init_phase_y[0],
+ pipe->base +
+ MDSS_MDP_REG_SCALE_INIT_PHASE_Y);
+ }
/*program pixel extn values for the SSPP*/
mdss_mdp_pipe_program_pixel_extn(pipe);
- } else if (pipe->type == MDSS_MDP_PIPE_TYPE_VIG) {
- writel_relaxed(phasex_step, pipe->base +
- MDSS_MDP_REG_SCALE_PHASE_STEP_X);
- writel_relaxed(phasey_step, pipe->base +
- MDSS_MDP_REG_SCALE_PHASE_STEP_Y);
- writel_relaxed(init_phasex, pipe->base +
- MDSS_MDP_REG_SCALE_INIT_PHASE_X);
- writel_relaxed(init_phasey, pipe->base +
- MDSS_MDP_REG_SCALE_INIT_PHASE_Y);
} else {
writel_relaxed(phasex_step, pipe->base +
MDSS_MDP_REG_SCALE_PHASE_STEP_X);