diff options
| author | Osvaldo Banuelos <osvaldob@codeaurora.org> | 2016-05-09 11:55:24 -0700 |
|---|---|---|
| committer | Jeevan Shriram <jshriram@codeaurora.org> | 2016-05-16 20:10:34 -0700 |
| commit | cf4266513cf20c214b1f668e21fc24abc2dbfe95 (patch) | |
| tree | 1c18357763253937456e869a65fdd3ae5e80ef72 | |
| parent | 36015d8392eaea996c4c5b4184367ceafdeb26a4 (diff) | |
ARM: dts: msm: Enable Silver frequency scaling up to SVS on msmcobalt
Add the necessary frequency configuration to the OSM and CPUfreq
device nodes to allow frequency scaling of the Silver cluster in
msmcobalt to SVS Fmax.
Change-Id: I8153e1c2ad9cb320a4c116593b15898dbe2f6ca2
CRs-Fixed: 1014894
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
| -rw-r--r-- | arch/arm/boot/dts/qcom/msmcobalt.dtsi | 22 |
1 files changed, 20 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/qcom/msmcobalt.dtsi b/arch/arm/boot/dts/qcom/msmcobalt.dtsi index a27269102083..a67323ec75b2 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt.dtsi @@ -605,7 +605,16 @@ qcom,governor-per-policy; qcom,cpufreq-table-0 = - < 300000 >; + < 300000 >, + < 345600 >, + < 422400 >, + < 499200 >, + < 576000 >, + < 633600 >, + < 710400 >, + < 806400 >, + < 883200 >, + < 960000 >; qcom,cpufreq-table-4 = < 300000 >; @@ -710,7 +719,16 @@ interrupt-names = "pwrcl-irq", "perfcl-irq"; qcom,pwrcl-speedbin0-v0 = - < 300000000 0x0004000f 0x031e001e 0x1>; + < 300000000 0x0004000f 0x031e001e 0x1>, + < 345600000 0x05040012 0x04200020 0x1>, + < 422400000 0x05040016 0x04200020 0x1>, + < 499200000 0x0504001a 0x05200020 0x1>, + < 576000000 0x0504001e 0x06200020 0x1>, + < 633600000 0x04040021 0x07200020 0x1>, + < 710400000 0x04040025 0x07200020 0x1>, + < 806400000 0x0404002a 0x08220022 0x2>, + < 883200000 0x0404002e 0x09250025 0x2>, + < 960000000 0x04040032 0x0a280028 0x2>; qcom,perfcl-speedbin0-v0 = < 300000000 0x0004000f 0x03200020 0x1>; |