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| author | Linux Build Service Account <lnxbuild@localhost> | 2016-09-02 13:52:33 -0700 |
|---|---|---|
| committer | Gerrit - the friendly Code Review server <code-review@localhost> | 2016-09-02 13:52:32 -0700 |
| commit | ce208ebb32597e733c201c3373616d18b5c62d57 (patch) | |
| tree | d9b1de552a0de6ad7a1e2546d8edbc284946a702 | |
| parent | 90d089418c59ed424d288d1b48d9d6683dd2fa7e (diff) | |
| parent | 54b8bf43e46f02196b0cc8d841300abfa8378ec1 (diff) | |
Merge "ARM: dts: msm: add 2 lane support for msmcobalt ufs phy"
| -rw-r--r-- | arch/arm/boot/dts/qcom/msmcobalt-v2.dtsi | 35 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msmcobalt.dtsi | 16 |
2 files changed, 50 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/qcom/msmcobalt-v2.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-v2.dtsi index f4d5e106e403..9cde93760089 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-v2.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-v2.dtsi @@ -570,3 +570,38 @@ }; }; }; + +&ufs1 { + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks = + <&clock_gcc clk_gcc_ufs_axi_hw_ctl_clk>, + <&clock_gcc clk_gcc_aggre1_ufs_axi_clk>, + <&clock_gcc clk_gcc_ufs_ahb_clk>, + <&clock_gcc clk_gcc_ufs_unipro_core_hw_ctl_clk>, + <&clock_gcc clk_gcc_ufs_ice_core_hw_ctl_clk>, + <&clock_gcc clk_ln_bb_clk1>, + <&clock_gcc clk_gcc_ufs_tx_symbol_0_clk>, + <&clock_gcc clk_gcc_ufs_rx_symbol_0_clk>, + <&clock_gcc clk_gcc_ufs_rx_symbol_1_clk>; + freq-table-hz = + <50000000 200000000>, + <0 0>, + <0 0>, + <37500000 150000000>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + + lanes-per-direction = <2>; +}; diff --git a/arch/arm/boot/dts/qcom/msmcobalt.dtsi b/arch/arm/boot/dts/qcom/msmcobalt.dtsi index a531226eba47..d49a4faa22f0 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt.dtsi @@ -1723,8 +1723,9 @@ <0 0>; lanes-per-direction = <1>; + qcom,msm-bus,name = "ufs1"; - qcom,msm-bus,num-cases = <12>; + qcom,msm-bus,num-cases = <22>; qcom,msm-bus,num-paths = <2>; qcom,msm-bus,vectors-KBps = <95 512 0 0>, <1 650 0 0>, /* No vote */ @@ -1732,17 +1733,30 @@ <95 512 1844 0>, <1 650 1000 0>, /* PWM G2 */ <95 512 3688 0>, <1 650 1000 0>, /* PWM G3 */ <95 512 7376 0>, <1 650 1000 0>, /* PWM G4 */ + <95 512 1844 0>, <1 650 1000 0>, /* PWM G1 L2 */ + <95 512 3688 0>, <1 650 1000 0>, /* PWM G2 L2 */ + <95 512 7376 0>, <1 650 1000 0>, /* PWM G3 L2 */ + <95 512 14752 0>, <1 650 1000 0>, /* PWM G4 L2 */ <95 512 127796 0>, <1 650 1000 0>, /* HS G1 RA */ <95 512 255591 0>, <1 650 1000 0>, /* HS G2 RA */ <95 512 511181 0>, <1 650 1000 0>, /* HS G3 RA */ + <95 512 255591 0>, <1 650 1000 0>, /* HS G1 RA L2 */ + <95 512 511181 0>, <1 650 1000 0>, /* HS G2 RA L2 */ + <95 512 1022362 0>, <1 650 1000 0>, /* HS G3 RA L2 */ <95 512 149422 0>, <1 650 1000 0>, /* HS G1 RB */ <95 512 298189 0>, <1 650 1000 0>, /* HS G2 RB */ <95 512 596378 0>, <1 650 1000 0>, /* HS G3 RB */ + <95 512 298189 0>, <1 650 1000 0>, /* HS G1 RB L2 */ + <95 512 596378 0>, <1 650 1000 0>, /* HS G2 RB L2 */ + <95 512 1192756 0>, <1 650 1000 0>, /* HS G3 RB L2 */ <95 512 4096000 0>, <1 650 1000 0>; /* Max. bandwidth */ qcom,bus-vector-names = "MIN", "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", + "PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2", "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", + "HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", + "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "MAX"; /* PM QoS */ |