diff options
| author | Anirudh Ghayal <aghayal@codeaurora.org> | 2019-05-15 08:58:15 +0530 |
|---|---|---|
| committer | Anirudh Ghayal <aghayal@codeaurora.org> | 2019-05-15 09:03:34 +0530 |
| commit | c9fa4db90a8303e88555fefee113db5530fe7f17 (patch) | |
| tree | a3e5611a0b7a8c8b136f927e818c5f875e850025 | |
| parent | 22dc337a69af6c8b2aceecb3cbaef9049ef4fb73 (diff) | |
pwm: pwm-qpnp: Fix the order of configuring PWM value
The hardware expects the PWM MSB value to be written
before LSB to avoid glitches in the output. Fix this.
Change-Id: I048bdbd0c096a6d03501bdd5b1d2d4bb50d45dd7
Signed-off-by: Anirudh Ghayal <aghayal@codeaurora.org>
| -rw-r--r-- | drivers/pwm/pwm-qpnp.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/drivers/pwm/pwm-qpnp.c b/drivers/pwm/pwm-qpnp.c index 8edb8a61795a..38b70e4e6edd 100644 --- a/drivers/pwm/pwm-qpnp.c +++ b/drivers/pwm/pwm-qpnp.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2012-2017, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2017, 2019 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -694,17 +694,6 @@ static int qpnp_lpg_save_pwm_value(struct qpnp_pwm_chip *chip) if (pwm_config->pwm_value > max_pwm_value) pwm_config->pwm_value = max_pwm_value; - value = pwm_config->pwm_value; - mask = QPNP_PWM_VALUE_LSB_MASK; - - pr_debug("pwm_lsb value:%d\n", value & mask); - rc = qpnp_lpg_save_and_write(value, mask, - &chip->qpnp_lpg_registers[QPNP_PWM_VALUE_LSB], - SPMI_LPG_REG_ADDR(lpg_config->base_addr, - QPNP_PWM_VALUE_LSB), 1, chip); - if (rc) - return rc; - value = (pwm_config->pwm_value >> QPNP_PWM_VALUE_MSB_SHIFT) & QPNP_PWM_VALUE_MSB_MASK; @@ -718,6 +707,17 @@ static int qpnp_lpg_save_pwm_value(struct qpnp_pwm_chip *chip) if (rc) return rc; + value = pwm_config->pwm_value; + mask = QPNP_PWM_VALUE_LSB_MASK; + + pr_debug("pwm_lsb value:%d\n", value & mask); + rc = qpnp_lpg_save_and_write(value, mask, + &chip->qpnp_lpg_registers[QPNP_PWM_VALUE_LSB], + SPMI_LPG_REG_ADDR(lpg_config->base_addr, + QPNP_PWM_VALUE_LSB), 1, chip); + if (rc) + return rc; + if (chip->sub_type == QPNP_PWM_MODE_ONLY_SUB_TYPE || chip->sub_type == QPNP_LPG_S_CHAN_SUB_TYPE) { value = QPNP_PWM_SYNC_VALUE & QPNP_PWM_SYNC_MASK; |