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| author | Linux Build Service Account <lnxbuild@localhost> | 2016-09-07 08:48:13 -0700 |
|---|---|---|
| committer | Gerrit - the friendly Code Review server <code-review@localhost> | 2016-09-07 08:48:13 -0700 |
| commit | c9796e05e92b55b575671fc84ee78b563cdc7139 (patch) | |
| tree | c658cc0e4531a7f5b9e9a7f7d11d290b655d0d34 | |
| parent | 26745af0124e3ff541e01cd32fca2bddb97784bf (diff) | |
| parent | 82200b104b20407e357b3e8a75081a1c292f2f98 (diff) | |
Merge "ARM: dts: msm: Update debug uart support for msmfalcon"
| -rw-r--r-- | arch/arm/boot/dts/qcom/msmfalcon-rumi.dts | 2 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msmfalcon-sim.dts | 2 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msmfalcon.dtsi | 12 |
3 files changed, 13 insertions, 3 deletions
diff --git a/arch/arm/boot/dts/qcom/msmfalcon-rumi.dts b/arch/arm/boot/dts/qcom/msmfalcon-rumi.dts index 6631d31bac6d..0d694a6cd9fa 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-rumi.dts +++ b/arch/arm/boot/dts/qcom/msmfalcon-rumi.dts @@ -22,7 +22,7 @@ qcom,board-id = <15 0>; }; -&uartblsp2dm1 { +&uartblsp1dm1 { status = "ok"; pinctrl-names = "default"; pinctrl-0 = <&uart_console_active>; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-sim.dts b/arch/arm/boot/dts/qcom/msmfalcon-sim.dts index 9840343fc3a7..eaaa1b407425 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-sim.dts +++ b/arch/arm/boot/dts/qcom/msmfalcon-sim.dts @@ -22,7 +22,7 @@ qcom,board-id = <16 0>; }; -&uartblsp2dm1 { +&uartblsp1dm1 { status = "ok"; pinctrl-names = "default"; pinctrl-0 = <&uart_console_active>; diff --git a/arch/arm/boot/dts/qcom/msmfalcon.dtsi b/arch/arm/boot/dts/qcom/msmfalcon.dtsi index e46041cdd501..549274d52791 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon.dtsi +++ b/arch/arm/boot/dts/qcom/msmfalcon.dtsi @@ -23,7 +23,7 @@ interrupt-parent = <&intc>; aliases { - serial0 = &uartblsp2dm1; + serial0 = &uartblsp1dm1; }; chosen { @@ -246,6 +246,16 @@ 3200 3200 3200 3200 3200 3200>; }; + uartblsp1dm1: serial@0c170000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0xc170000 0x1000>; + interrupts = <0 108 0>; + status = "disabled"; + clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>, + <&clock_gcc GCC_BLSP1_AHB_CLK>; + clock-names = "core", "iface"; + }; + uartblsp2dm1: serial@0c1b0000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0xc1b0000 0x1000>; |