Promotion of kernel.lnx.4.4-160602.

CRs      Change ID                                   Subject
--------------------------------------------------------------------------------------------------------------
1014726   Ia6d4755408646ac4a75724f3c6f2177651875da3   ASoC: compress: fix unsigned integer overflow check
999619   Ia31c3f10c24380d9670cd0ca83834844435e593d   msm: camera: isp: For vfe version 4.8 do not reset vbif
1021009   Id0687402d56f24ca851916f92f86a145136bb866   msm: camera: Configure some of the csiphy registers
1023180   I9601efd300c7f428c4576e6ecf6d31791d0b47bd   arm64: dma-mapping: Attach IOMMUs as groups
1021593   Ide3309d4dc713892703e2eb5ee33c9db7f990156   clk: msm: osm: increase main PLL minimum L_VAL to 825.6
987041   I2eb33c63168ab26818dfdb3e11315f2ce8f24fa5   net: core: neighbour: Change the print format for addres
1003213   I9f9845fea425fc4463dae72e8f8ab6e8bda23121   clk: msm: clock-gcc-cobalt: Add the cnoc_periph RPM reso
1008023   If43428f0eb53370ca725480b3cd13e7b53e643c3   ARM: dts: msm: Advertise SG support by rmnet_ipa on msmc
1023412   I812f0f6b38e7e9973cc9a0c8bfd6fb5078f719ff   ARM: dts: msm: rename the flash/WLED devices in pmicobal
1021593 1022853   I1fdde432e267c1161ac5d28bdee4af57c23137ec   ARM: dts: msm: Add full Silver cluster frequency plan fo
890916   If4503b0e25ac151039d1743a007ba1624a2e90f4   ARM: dts: msm: Add Round robin ADC channels for pmicobal
1022663   I60185482ae9b5364e297370593d95cce056b314e   clk: msm: clock-mmss-8996: Add graphics clocks support o
1023187   Icb5c5f219a197a158e00f600e68111ff699062b7   clk: msm: osm: increase unstall timer for PC/RET FSM to
890916   I88b5922ab4dc817257042fdaa385768e6f14be57   defconfig: arm64: msmcortex: Enable IIO and RRADC driver
1007397   Iab4f544532e57682eb5dbfe7865850b8e978f1b4   ARM: dts: msm: add WCN3990 BT/FM support for msmcobalt d
1015446   I78f1d3a1ac9ed09d2f4f266f61a1c14d44b41f53   ARM: dts: msm: Enable the GPU clock driver on MSMCOBALT
1019576   Ibd0041cea2ac47180110a1cfe96516d347d9816a   ARM: dts: msm: disable IPA and rmnet-ipa nodes on APQ809
1017800   I93aa6df8c7ec1916ba23d21d92e477510db949da   qcom-charger: use mutex instead of spinlock when calling
1008023   Idf626cb5a22d2ed5152ab76dcc5fe56696a631a6   msm: rmnet_ipa3: add RMNET_IOCTL_GET_SG_SUPPORT support

Change-Id: I4e27425902c8c7fc8baad951575616e92b28b2fc
CRs-Fixed: 1014726, 1023180, 1023412, 1021593, 1023187, 1003213, 1017800, 890916, 1008023, 1022853, 1007397, 1022663, 987041, 1015446, 1019576, 1021009, 999619

29 files changed, 344 insertions, 106 deletions

diff --git a/Documentation/devicetree/bindings/arm/msm/clock-controller.txt b/Documentation/devicetree/bindings/arm/msm/clock-controller.txt
index 0f6175897d27..20506e132727 100644
--- a/Documentation/devicetree/bindings/arm/msm/clock-controller.txt
+++ b/Documentation/devicetree/bindings/arm/msm/clock-controller.txt
@@ -54,10 +54,12 @@ Required properties:
 			"qcom,mmsscc-8996"
 			"qcom,mmsscc-8996-v2"
 			"qcom,mmsscc-8996-v3"
+			"qcom,mmsscc-8996-pro"
 			"qcom,gpucc-8996"
 			"qcom,gpucc-8996-v2"
 			"qcom,gpucc-8996-v3"
 			"qcom,gpucc-8996-v3.0"
+			"qcom,gpucc-8996-pro"
 			"qcom,gcc-gfx-titanium"
 			"qcom,gcc-californium"
 			"qcom,cc-debug-californium"
@@ -83,7 +85,7 @@ Required properties:
 			there is one expected base: "cc_base". Optional
 			reg-names are "apcs_base", "meas", "mmss_base",
 			"lpass_base", "apcs_c0_base", "apcs_c1_base",
-			"apcs_cci_base".
+			"apcs_cci_base", "efuse".
 
 Optional properties:
 - vdd_dig-supply:	The digital logic rail supply.
diff --git a/Documentation/devicetree/bindings/platform/msm/rmnet_ipa3.txt b/Documentation/devicetree/bindings/platform/msm/rmnet_ipa3.txt
index 767f7ac61844..3f5531278700 100644
--- a/Documentation/devicetree/bindings/platform/msm/rmnet_ipa3.txt
+++ b/Documentation/devicetree/bindings/platform/msm/rmnet_ipa3.txt
@@ -8,6 +8,8 @@ Required properties:
 Optional:
 - qcom,rmnet-ipa-ssr: determine if modem SSR is supported
 - qcom,ipa-loaduC: indicate that ipa uC should be loaded
+- qcom,ipa-advertise-sg-support: determine how to respond to a query
+regarding scatter-gather capability
 
 Example:
 	qcom,rmnet-ipa3 {
diff --git a/arch/arm/boot/dts/qcom/apq8096-v2.dtsi b/arch/arm/boot/dts/qcom/apq8096-v2.dtsi
index 2199c9061ceb..a2b9b4d62d27 100644
--- a/arch/arm/boot/dts/qcom/apq8096-v2.dtsi
+++ b/arch/arm/boot/dts/qcom/apq8096-v2.dtsi
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -22,3 +22,13 @@
 	model = "Qualcomm Technologies, Inc. APQ 8096 v2";
 	qcom,msm-id = <291 0x20001>;
 };
+
+&soc {
+	qcom,rmnet-ipa {
+		status = "disabled";
+	};
+};
+
+&ipa_hw {
+	status = "disabled";
+};
diff --git a/arch/arm/boot/dts/qcom/apq8096-v3.0.dtsi b/arch/arm/boot/dts/qcom/apq8096-v3.0.dtsi
index 51c690f6a305..f79119c22823 100644
--- a/arch/arm/boot/dts/qcom/apq8096-v3.0.dtsi
+++ b/arch/arm/boot/dts/qcom/apq8096-v3.0.dtsi
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -22,3 +22,13 @@
 	model = "Qualcomm Technologies, Inc. APQ 8096 v3.0";
 	qcom,msm-id = <291 0x30000>;
 };
+
+&soc {
+	qcom,rmnet-ipa {
+		status = "disabled";
+	};
+};
+
+&ipa_hw {
+	status = "disabled";
+};
diff --git a/arch/arm/boot/dts/qcom/apq8096-v3.dtsi b/arch/arm/boot/dts/qcom/apq8096-v3.dtsi
index 7ec5d505ac8b..fdf9e997db28 100644
--- a/arch/arm/boot/dts/qcom/apq8096-v3.dtsi
+++ b/arch/arm/boot/dts/qcom/apq8096-v3.dtsi
@@ -1,4 +1,4 @@
-/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2014-2016, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -22,3 +22,13 @@
 	model = "Qualcomm Technologies, Inc. APQ 8096 v3";
 	qcom,msm-id = <291 0x30001>;
 };
+
+&soc {
+	qcom,rmnet-ipa {
+		status = "disabled";
+	};
+};
+
+&ipa_hw {
+	status = "disabled";
+};
diff --git a/arch/arm/boot/dts/qcom/apq8096pro.dtsi b/arch/arm/boot/dts/qcom/apq8096pro.dtsi
index 2dc47c418c09..7a70c51ec0e4 100644
--- a/arch/arm/boot/dts/qcom/apq8096pro.dtsi
+++ b/arch/arm/boot/dts/qcom/apq8096pro.dtsi
@@ -22,3 +22,13 @@
 	model = "Qualcomm Technologies, Inc. APQ 8096 pro";
 	qcom,msm-id = <312 0x20000>;
 };
+
+&soc {
+	qcom,rmnet-ipa {
+		status = "disabled";
+	};
+};
+
+&ipa_hw {
+	status = "disabled";
+};
diff --git a/arch/arm/boot/dts/qcom/msm-pmicobalt.dtsi b/arch/arm/boot/dts/qcom/msm-pmicobalt.dtsi
index 5b2f52330906..c0bae6c6e5f8 100644
--- a/arch/arm/boot/dts/qcom/msm-pmicobalt.dtsi
+++ b/arch/arm/boot/dts/qcom/msm-pmicobalt.dtsi
@@ -285,6 +285,54 @@
 			qcom,ibat-polling-delay-ms = <100>;
 		};
 
+		pmicobalt_rradc: rradc@4500 {
+			compatible = "qcom,rradc";
+			reg = <0x4500 0x100>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#io-channel-cells = <1>;
+
+			/* Channel node */
+			batt_id {
+				channel = <3>;
+			};
+
+			batt_therm {
+				channel = <4>;
+			};
+
+			skin_temp {
+				channel = <5>;
+			};
+
+			usbin_v {
+				channel = <6>;
+			};
+
+			usbin_i {
+				channel = <7>;
+			};
+
+			dcin_v {
+				channel = <8>;
+			};
+
+			dcin_i {
+				channel = <9>;
+			};
+
+			die_temp {
+				channel = <0xa>;
+			};
+
+			chg_temp {
+				channel = <0xb>;
+			};
+
+			gpio {
+				channel = <0xc>;
+			};
+		};
 	};
 
 	qcom,pmicobalt@3 {
@@ -443,7 +491,7 @@
 			};
 		};
 
-		pmi8998_wled: qcom,leds@d800 {
+		pmicobalt_wled: qcom,leds@d800 {
 			compatible = "qcom,qpnp-wled";
 			reg = <0xd800 0x100>,
 				<0xd900 0x100>,
@@ -507,7 +555,7 @@
 			qcom,hdrm-auto-mode;
 			qcom,isc-delay = <192>;
 
-			pmi8998_flash0: qcom,flash_0 {
+			pmicobalt_flash0: qcom,flash_0 {
 				label = "flash";
 				qcom,led-name = "led:flash_0";
 				qcom,max-current = <1500>;
@@ -520,7 +568,7 @@
 				qcom,hdrm-vol-hi-lo-win-mv = <100>;
 			};
 
-			pmi8998_flash1: qcom,flash_1 {
+			pmicobalt_flash1: qcom,flash_1 {
 				label = "flash";
 				qcom,led-name = "led:flash_1";
 				qcom,max-current = <1500>;
@@ -533,7 +581,7 @@
 				qcom,hdrm-vol-hi-lo-win-mv = <100>;
 			};
 
-			pmi8998_flash2: qcom,flash_2 {
+			pmicobalt_flash2: qcom,flash_2 {
 				label = "flash";
 				qcom,led-name = "led:flash_2";
 				qcom,max-current = <750>;
@@ -549,7 +597,7 @@
 				pinctrl-1 = <&led_disable>;
 			};
 
-			pmi8998_switch: qcom,led_switch {
+			pmicobalt_switch: qcom,led_switch {
 				label = "switch";
 				qcom,led-name = "led:switch";
 				qcom,default-led-trigger =
diff --git a/arch/arm/boot/dts/qcom/msm8996.dtsi b/arch/arm/boot/dts/qcom/msm8996.dtsi
index e0bd005f8b76..70f98c3b98c7 100644
--- a/arch/arm/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8996.dtsi
@@ -787,8 +787,9 @@
 
 	clock_mmss: qcom,mmsscc@8c0000 {
 		compatible = "qcom,mmsscc-8996";
-		reg = <0x8c0000 0xb00c>;
-		reg-names = "cc_base";
+		reg = <0x8c0000 0xb00c>,
+			<0x74130 0x8>;
+		reg-names = "cc_base", "efuse";
 		vdd_dig-supply = <&pm8994_s1_corner>;
 		mmpll4_dig-supply = <&pm8994_s1_corner>;
 		mmpll4_analog-supply = <&pm8994_l12>;
@@ -812,9 +813,8 @@
 
 	clock_gpu: qcom,gpucc@8c0000 {
 		compatible = "qcom,gpucc-8996";
-		reg = <0x8c0000 0xb00c>,
-			<0x74130 0x8>;
-		reg-names = "cc_base", "efuse";
+		reg = <0x8c0000 0xb00c>;
+		reg-names = "cc_base";
 		vdd_gfx-supply = <&gfx_vreg>;
 		qcom,gfx3d_clk_src-opp-handle = <&msm_gpu>;
 		vdd_mx-supply = <&pm8994_s2_corner>;
diff --git a/arch/arm/boot/dts/qcom/msmcobalt-cdp.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-cdp.dtsi
index 2e69f167671b..2da3b4e3ffea 100644
--- a/arch/arm/boot/dts/qcom/msmcobalt-cdp.dtsi
+++ b/arch/arm/boot/dts/qcom/msmcobalt-cdp.dtsi
@@ -353,3 +353,9 @@
 &wil6210 {
 	status = "ok";
 };
+
+&soc {
+	sound-9335 {
+		qcom,wcn-btfm;
+	};
+};
diff --git a/arch/arm/boot/dts/qcom/msmcobalt-mtp.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-mtp.dtsi
index 7225ba84eaeb..0a17ece9ea11 100644
--- a/arch/arm/boot/dts/qcom/msmcobalt-mtp.dtsi
+++ b/arch/arm/boot/dts/qcom/msmcobalt-mtp.dtsi
@@ -274,3 +274,9 @@
 &wil6210 {
 	status = "ok";
 };
+
+&soc {
+	sound-9335 {
+		qcom,wcn-btfm;
+	};
+};
diff --git a/arch/arm/boot/dts/qcom/msmcobalt-v2.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-v2.dtsi
index 8bf667aabb52..3bb5943634f2 100644
--- a/arch/arm/boot/dts/qcom/msmcobalt-v2.dtsi
+++ b/arch/arm/boot/dts/qcom/msmcobalt-v2.dtsi
@@ -30,3 +30,31 @@
 &clock_mmss {
 	compatible = "qcom,mmsscc-cobalt-v2";
 };
+
+&clock_gpu {
+	compatible = "qcom,gpucc-cobalt-v2";
+};
+
+&clock_gfx {
+	compatible = "qcom,gfxcc-cobalt-v2";
+	qcom,gfxfreq-speedbin0 =
+		<         0 0                           0 >,
+		< 189000000 1 RPM_SMD_REGULATOR_LEVEL_SVS >,
+		< 264000000 2 RPM_SMD_REGULATOR_LEVEL_SVS >,
+		< 342000000 3 RPM_SMD_REGULATOR_LEVEL_SVS >,
+		< 414000000 4 RPM_SMD_REGULATOR_LEVEL_SVS >,
+		< 520000000 5 RPM_SMD_REGULATOR_LEVEL_NOM >,
+		< 596000000 6 RPM_SMD_REGULATOR_LEVEL_NOM >,
+		< 670000000 7 RPM_SMD_REGULATOR_LEVEL_TURBO >,
+		< 710000000 8 RPM_SMD_REGULATOR_LEVEL_TURBO >;
+	qcom,gfxfreq-mx-speedbin0 =
+		<         0                           0 >,
+		< 189000000 RPM_SMD_REGULATOR_LEVEL_SVS >,
+		< 264000000 RPM_SMD_REGULATOR_LEVEL_SVS >,
+		< 342000000 RPM_SMD_REGULATOR_LEVEL_SVS >,
+		< 414000000 RPM_SMD_REGULATOR_LEVEL_SVS >,
+		< 520000000 RPM_SMD_REGULATOR_LEVEL_NOM >,
+		< 596000000 RPM_SMD_REGULATOR_LEVEL_NOM >,
+		< 670000000 RPM_SMD_REGULATOR_LEVEL_TURBO >,
+		< 710000000 RPM_SMD_REGULATOR_LEVEL_TURBO >;
+};
diff --git a/arch/arm/boot/dts/qcom/msmcobalt.dtsi b/arch/arm/boot/dts/qcom/msmcobalt.dtsi
index 2239cd3c055e..4944d97e1e1e 100644
--- a/arch/arm/boot/dts/qcom/msmcobalt.dtsi
+++ b/arch/arm/boot/dts/qcom/msmcobalt.dtsi
@@ -631,7 +631,19 @@
 			<  710400 >,
 			<  806400 >,
 			<  883200 >,
-			<  960000 >;
+			<  960000 >,
+			< 1036800 >,
+			< 1113600 >,
+			< 1190400 >,
+			< 1248000 >,
+			< 1324800 >,
+			< 1401600 >,
+			< 1478400 >,
+			< 1574400 >,
+			< 1651200 >,
+			< 1728000 >,
+			< 1804800 >,
+			< 1881600 >;
 
 		qcom,cpufreq-table-4 =
 			<  300000 >;
@@ -736,16 +748,28 @@
 		interrupt-names = "pwrcl-irq", "perfcl-irq";
 
 		qcom,pwrcl-speedbin0-v0 =
-			< 300000000  0x0004000f 0x031e001e 0x1>,
-			< 345600000  0x05040012 0x04200020 0x1>,
-			< 422400000  0x05040016 0x04200020 0x1>,
-			< 499200000  0x0504001a 0x05200020 0x1>,
-			< 576000000  0x0504001e 0x06200020 0x1>,
-			< 633600000  0x04040021 0x07200020 0x1>,
-			< 710400000  0x04040025 0x07200020 0x1>,
-			< 806400000  0x0404002a 0x08220022 0x2>,
-			< 883200000  0x0404002e 0x09250025 0x2>,
-			< 960000000  0x04040032 0x0a280028 0x2>;
+			<   300000000 0x0004000f 0x01200020 0x1 >,
+			<   345600000 0x05040012 0x02200020 0x1 >,
+			<   422400000 0x05040016 0x02200020 0x1 >,
+			<   499200000 0x0504001a 0x02200020 0x1 >,
+			<   576000000 0x0504001e 0x03200020 0x1 >,
+			<   633600000 0x05040021 0x03200020 0x1 >,
+			<   710400000 0x05040025 0x03200020 0x1 >,
+			<   806400000 0x0504002a 0x04200020 0x2 >,
+			<   883200000 0x0404002e 0x04250025 0x2 >,
+			<   960000000 0x04040032 0x05280028 0x2 >,
+			<  1036800000 0x04040036 0x052b002b 0x3 >,
+			<  1113600000 0x0404003a 0x052e002e 0x3 >,
+			<  1190400000 0x0404003e 0x06320032 0x3 >,
+			<  1248000000 0x04040041 0x06340034 0x3 >,
+			<  1324800000 0x04040045 0x06370037 0x3 >,
+			<  1401600000 0x04040049 0x073a003a 0x3 >,
+			<  1478400000 0x0404004d 0x073e003e 0x3 >,
+			<  1574400000 0x04040052 0x08420042 0x4 >,
+			<  1651200000 0x04040056 0x08450045 0x4 >,
+			<  1728000000 0x0404005a 0x08480048 0x4 >,
+			<  1804800000 0x0404005e 0x094b004b 0x4 >,
+			<  1881600000 0x04040062 0x094e004e 0x4 >;
 
 		qcom,perfcl-speedbin0-v0 =
 			< 300000000  0x0004000f 0x03200020 0x1>;
@@ -848,6 +872,7 @@
 		compatible = "qcom,rmnet-ipa3";
 		qcom,rmnet-ipa-ssr;
 		qcom,ipa-loaduC;
+		qcom,ipa-advertise-sg-support;
 	};
 
 	ipa_hw: qcom,ipa@01e00000 {
@@ -1920,17 +1945,16 @@
 
 		clocks = <&clock_gcc clk_cxo_clk_src>,
 			 <&clock_gcc clk_gcc_mss_cfg_ahb_clk>,
-			 <&clock_gcc clk_pnoc_clk>,
 			 <&clock_gcc clk_gcc_bimc_mss_q6_axi_clk>,
 			 <&clock_gcc clk_gcc_boot_rom_ahb_clk>,
 			 <&clock_gcc clk_gpll0_out_msscc>,
 			 <&clock_gcc clk_gcc_mss_snoc_axi_clk>,
 			 <&clock_gcc clk_gcc_mss_mnoc_bimc_axi_clk>,
 			 <&clock_gcc clk_qdss_clk>;
-		clock-names = "xo", "iface_clk", "pnoc_clk", "bus_clk",
+		clock-names = "xo", "iface_clk", "bus_clk",
 			      "mem_clk", "gpll0_mss_clk", "snoc_axi_clk",
 			      "mnoc_axi_clk", "qdss_clk";
-		qcom,proxy-clock-names = "xo", "pnoc_clk", "qdss_clk";
+		qcom,proxy-clock-names = "xo", "qdss_clk";
 		qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk",
 					  "gpll0_mss_clk", "snoc_axi_clk",
 					  "mnoc_axi_clk";
diff --git a/arch/arm64/configs/msmcortex-perf_defconfig b/arch/arm64/configs/msmcortex-perf_defconfig
index f19832a5b321..d578b0eec486 100644
--- a/arch/arm64/configs/msmcortex-perf_defconfig
+++ b/arch/arm64/configs/msmcortex-perf_defconfig
@@ -487,6 +487,8 @@ CONFIG_QCOM_BIMC_BWMON=y
 CONFIG_DEVFREQ_GOV_QCOM_BW_HWMON=y
 CONFIG_QCOM_DEVFREQ_DEVBW=y
 CONFIG_EXTCON=y
+CONFIG_IIO=y
+CONFIG_QCOM_RRADC=y
 CONFIG_PWM=y
 CONFIG_PWM_QPNP=y
 CONFIG_ANDROID=y
diff --git a/arch/arm64/configs/msmcortex_defconfig b/arch/arm64/configs/msmcortex_defconfig
index b385b3029732..867ee6b0a40a 100644
--- a/arch/arm64/configs/msmcortex_defconfig
+++ b/arch/arm64/configs/msmcortex_defconfig
@@ -514,6 +514,8 @@ CONFIG_QCOM_BIMC_BWMON=y
 CONFIG_DEVFREQ_GOV_QCOM_BW_HWMON=y
 CONFIG_QCOM_DEVFREQ_DEVBW=y
 CONFIG_EXTCON=y
+CONFIG_IIO=y
+CONFIG_QCOM_RRADC=y
 CONFIG_PWM=y
 CONFIG_PWM_QPNP=y
 CONFIG_ARM_GIC_V3_ACL=y
diff --git a/arch/arm64/mm/dma-mapping.c b/arch/arm64/mm/dma-mapping.c
index c2819df04b3f..6b151d483f5c 100644
--- a/arch/arm64/mm/dma-mapping.c
+++ b/arch/arm64/mm/dma-mapping.c
@@ -2114,12 +2114,19 @@ int arm_iommu_attach_device(struct device *dev,
 {
 	int err;
 	int s1_bypass = 0, is_fast = 0;
+	struct iommu_group *group;
 
 	iommu_domain_get_attr(mapping->domain, DOMAIN_ATTR_FAST, &is_fast);
 	if (is_fast)
 		return fast_smmu_attach_device(dev, mapping);
 
-	err = iommu_attach_device(mapping->domain, dev);
+	group = iommu_group_get(dev);
+	if (!group) {
+		dev_err(dev, "Couldn't get group\n");
+		return -ENODEV;
+	}
+
+	err = iommu_attach_group(mapping->domain, group);
 	if (err)
 		return err;
 
@@ -2147,6 +2154,7 @@ void arm_iommu_detach_device(struct device *dev)
 {
 	struct dma_iommu_mapping *mapping;
 	int is_fast;
+	struct iommu_group *group;
 
 	mapping = to_dma_iommu_mapping(dev);
 	if (!mapping) {
@@ -2160,7 +2168,13 @@ void arm_iommu_detach_device(struct device *dev)
 		return;
 	}
 
-	iommu_detach_device(mapping->domain, dev);
+	group = iommu_group_get(dev);
+	if (!group) {
+		dev_err(dev, "Couldn't get group\n");
+		return;
+	}
+
+	iommu_detach_group(mapping->domain, group);
 	kref_put(&mapping->kref, release_iommu_mapping);
 	dev->archdata.mapping = NULL;
 	set_dma_ops(dev, NULL);
diff --git a/drivers/clk/msm/clock-gcc-cobalt.c b/drivers/clk/msm/clock-gcc-cobalt.c
index 1718114c38a8..d225e710560b 100644
--- a/drivers/clk/msm/clock-gcc-cobalt.c
+++ b/drivers/clk/msm/clock-gcc-cobalt.c
@@ -59,10 +59,13 @@ static DEFINE_VDD_REGULATORS(vdd_dig, VDD_DIG_NUM, 1, vdd_corner, NULL);
 
 DEFINE_CLK_RPM_SMD_BRANCH(cxo_clk_src, cxo_clk_src_ao, RPM_MISC_CLK_TYPE,
 			  CXO_CLK_SRC_ID, 19200000);
-DEFINE_CLK_RPM_SMD(pnoc_clk, pnoc_a_clk, RPM_BUS_CLK_TYPE, PNOC_CLK_ID, NULL);
 DEFINE_CLK_RPM_SMD(bimc_clk, bimc_a_clk, RPM_MEM_CLK_TYPE, BIMC_CLK_ID, NULL);
 DEFINE_CLK_RPM_SMD(cnoc_clk, cnoc_a_clk, RPM_BUS_CLK_TYPE, CNOC_CLK_ID, NULL);
 DEFINE_CLK_RPM_SMD(snoc_clk, snoc_a_clk, RPM_BUS_CLK_TYPE, SNOC_CLK_ID, NULL);
+DEFINE_CLK_RPM_SMD(cnoc_periph_clk, cnoc_periph_a_clk, RPM_BUS_CLK_TYPE,
+			CNOC_PERIPH_CLK_ID, NULL);
+static DEFINE_CLK_VOTER(cnoc_periph_keepalive_a_clk, &cnoc_periph_a_clk.c,
+			LONG_MAX);
 static DEFINE_CLK_VOTER(bimc_msmbus_clk, &bimc_clk.c, LONG_MAX);
 static DEFINE_CLK_VOTER(bimc_msmbus_a_clk, &bimc_a_clk.c, LONG_MAX);
 static DEFINE_CLK_VOTER(cnoc_msmbus_clk, &cnoc_clk.c, LONG_MAX);
@@ -91,17 +94,12 @@ DEFINE_CLK_RPM_SMD_XO_BUFFER_PINCTRL(ln_bb_clk3_pin, ln_bb_clk3_pin_ao,
 				     LN_BB_CLK3_PIN_ID);
 static DEFINE_CLK_VOTER(mcd_ce1_clk, &ce1_clk.c, 85710000);
 DEFINE_CLK_DUMMY(measure_only_bimc_hmss_axi_clk, 0);
-DEFINE_CLK_RPM_SMD(mmssnoc_axi_clk, mmssnoc_axi_a_clk, RPM_BUS_CLK_TYPE,
-		   MMSSNOC_AXI_CLK_ID, NULL);
+DEFINE_CLK_RPM_SMD(mmssnoc_axi_clk, mmssnoc_axi_a_clk,
+			RPM_MMAXI_CLK_TYPE, MMSSNOC_AXI_CLK_ID, NULL);
 DEFINE_CLK_RPM_SMD_BRANCH(aggre1_noc_clk, aggre1_noc_a_clk,
 				RPM_AGGR_CLK_TYPE, AGGR1_NOC_ID, 1000);
 DEFINE_CLK_RPM_SMD_BRANCH(aggre2_noc_clk, aggre2_noc_a_clk,
 				RPM_AGGR_CLK_TYPE, AGGR2_NOC_ID, 1000);
-static DEFINE_CLK_VOTER(pnoc_keepalive_a_clk, &pnoc_a_clk.c, LONG_MAX);
-static DEFINE_CLK_VOTER(pnoc_msmbus_clk, &pnoc_clk.c, LONG_MAX);
-static DEFINE_CLK_VOTER(pnoc_msmbus_a_clk, &pnoc_a_clk.c, LONG_MAX);
-static DEFINE_CLK_VOTER(pnoc_pm_clk, &pnoc_clk.c, LONG_MAX);
-static DEFINE_CLK_VOTER(pnoc_sps_clk, &pnoc_clk.c, 0);
 static DEFINE_CLK_VOTER(qcedev_ce1_clk, &ce1_clk.c, 85710000);
 static DEFINE_CLK_VOTER(qcrypto_ce1_clk, &ce1_clk.c, 85710000);
 DEFINE_CLK_RPM_SMD_QDSS(qdss_clk, qdss_a_clk, RPM_MISC_CLK_TYPE,
@@ -2468,14 +2466,15 @@ static struct mux_clk gcc_debug_mux = {
 
 static struct clk_lookup msm_clocks_rpm_cobalt[] = {
 	CLK_LIST(cxo_clk_src),
-	CLK_LIST(pnoc_clk),
-	CLK_LIST(pnoc_a_clk),
 	CLK_LIST(bimc_clk),
 	CLK_LIST(bimc_a_clk),
 	CLK_LIST(cnoc_clk),
 	CLK_LIST(cnoc_a_clk),
 	CLK_LIST(snoc_clk),
 	CLK_LIST(snoc_a_clk),
+	CLK_LIST(cnoc_periph_clk),
+	CLK_LIST(cnoc_periph_a_clk),
+	CLK_LIST(cnoc_periph_keepalive_a_clk),
 	CLK_LIST(bimc_msmbus_clk),
 	CLK_LIST(bimc_msmbus_a_clk),
 	CLK_LIST(ce1_clk),
@@ -2517,11 +2516,6 @@ static struct clk_lookup msm_clocks_rpm_cobalt[] = {
 	CLK_LIST(aggre1_noc_a_clk),
 	CLK_LIST(aggre2_noc_clk),
 	CLK_LIST(aggre2_noc_a_clk),
-	CLK_LIST(pnoc_keepalive_a_clk),
-	CLK_LIST(pnoc_msmbus_clk),
-	CLK_LIST(pnoc_msmbus_a_clk),
-	CLK_LIST(pnoc_pm_clk),
-	CLK_LIST(pnoc_sps_clk),
 	CLK_LIST(qcedev_ce1_clk),
 	CLK_LIST(qcrypto_ce1_clk),
 	CLK_LIST(qdss_clk),
@@ -2797,11 +2791,9 @@ static int msm_gcc_cobalt_probe(struct platform_device *pdev)
 	if (ret)
 		return ret;
 
-	/*
-	 * Hold an active set vote for the PNOC AHB source. Sleep set vote is 0.
-	 */
-	clk_set_rate(&pnoc_keepalive_a_clk.c, 19200000);
-	clk_prepare_enable(&pnoc_keepalive_a_clk.c);
+	/* Hold an active set vote for the cnoc_periph resource */
+	clk_set_rate(&cnoc_periph_keepalive_a_clk.c, 19200000);
+	clk_prepare_enable(&cnoc_periph_keepalive_a_clk.c);
 
 	/* This clock is used for all MMSSCC register access */
 	clk_prepare_enable(&gcc_mmss_noc_cfg_ahb_clk.c);
diff --git a/drivers/clk/msm/clock-mmss-8996.c b/drivers/clk/msm/clock-mmss-8996.c
index 2b8a2d2edcbc..ba81731ce1cb 100644
--- a/drivers/clk/msm/clock-mmss-8996.c
+++ b/drivers/clk/msm/clock-mmss-8996.c
@@ -68,8 +68,10 @@ static void __iomem *virt_base_gpu;
 #define GFX_MIN_SVS_LEVEL	2
 #define GPU_REQ_ID		0x3
 
-#define EFUSE_SHIFT	29
-#define EFUSE_MASK	0x7
+#define EFUSE_SHIFT_v3	29
+#define EFUSE_MASK_v3	0x7
+#define EFUSE_SHIFT_PRO	28
+#define EFUSE_MASK_PRO	0x3
 
 static struct clk_ops clk_ops_gpu;
 
@@ -404,9 +406,9 @@ static struct mux_div_clk gfx3d_clk_src_v2 = {
 		.max_div = 1,
 	},
 	.parents = (struct clk_src[]) {
+		{&mmpll9_postdiv_clk.c, 2},
 		{&mmpll2_postdiv_clk.c, 3},
 		{&mmpll8_postdiv_clk.c, 4},
-		{&mmpll9_postdiv_clk.c, 2},
 	},
 	.num_parents = 3,
 	.c = {
@@ -3516,6 +3518,19 @@ static void msm_mmsscc_8996_v3_fixup(void)
 	video_subcore1_clk_src.c.fmax[VDD_DIG_HIGH] = 520000000;
 }
 
+static void msm_mmsscc_8996_pro_fixup(void)
+{
+	mmpll9.c.rate = 0;
+	mmpll9.c.fmax[VDD_DIG_LOWER] = 652800000;
+	mmpll9.c.fmax[VDD_DIG_LOW] = 652800000;
+	mmpll9.c.fmax[VDD_DIG_NOMINAL] = 1305600000;
+	mmpll9.c.fmax[VDD_DIG_HIGH] = 1305600000;
+	mmpll9.c.ops = &clk_ops_alpha_pll;
+	mmpll9.min_supported_freq = 1248000000;
+
+	mmpll9_postdiv_clk.c.ops = &clk_ops_div;
+}
+
 static int is_v3_gpu;
 static int gpu_pre_set_rate(struct clk *clk, unsigned long new_rate)
 {
@@ -3614,6 +3629,10 @@ static int of_get_fmax_vdd_class(struct platform_device *pdev, struct clk *c,
 }
 
 static struct platform_driver msm_clock_gpu_driver;
+struct resource *efuse_res;
+void __iomem *gpu_base;
+u64 efuse;
+int gpu_speed_bin;
 
 int msm_mmsscc_8996_probe(struct platform_device *pdev)
 {
@@ -3622,19 +3641,33 @@ int msm_mmsscc_8996_probe(struct platform_device *pdev)
 	struct clk *tmp;
 	struct regulator *reg;
 	u32 regval;
-	int is_v2, is_v3 = 0;
+	int is_pro, is_v2, is_v3 = 0;
 
 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cc_base");
 	if (!res) {
 		dev_err(&pdev->dev, "Unable to retrieve register base.\n");
 		return -ENOMEM;
 	}
+
+	efuse_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "efuse");
+	if (!efuse_res) {
+		dev_err(&pdev->dev, "Unable to retrieve efuse register base.\n");
+		return -ENOMEM;
+	}
+
 	virt_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
 	if (!virt_base) {
 		dev_err(&pdev->dev, "Failed to map CC registers\n");
 		return -ENOMEM;
 	}
 
+	gpu_base = devm_ioremap(&pdev->dev, efuse_res->start,
+					resource_size(efuse_res));
+	if (!gpu_base) {
+		dev_err(&pdev->dev, "Unable to map in efuse base\n");
+		return -ENOMEM;
+	}
+
 	/* Clear the DBG_CLK_DIV bits of the MMSS debug register */
 	regval = readl_relaxed(virt_base + mmss_gcc_dbg_clk.offset);
 	regval &= ~BM(18, 17);
@@ -3710,6 +3743,9 @@ int msm_mmsscc_8996_probe(struct platform_device *pdev)
 	ext_extpclk_clk_src.dev = &pdev->dev;
 	ext_extpclk_clk_src.clk_id = "extpclk_src";
 
+	efuse = readl_relaxed(gpu_base);
+	gpu_speed_bin = ((efuse >> EFUSE_SHIFT_v3) & EFUSE_MASK_v3);
+
 	is_v2 = of_device_is_compatible(pdev->dev.of_node,
 						"qcom,mmsscc-8996-v2");
 	if (is_v2)
@@ -3720,14 +3756,22 @@ int msm_mmsscc_8996_probe(struct platform_device *pdev)
 	if (is_v3)
 		msm_mmsscc_8996_v3_fixup();
 
+	is_pro = of_device_is_compatible(pdev->dev.of_node,
+						"qcom,mmsscc-8996-pro");
+	if (is_pro) {
+		gpu_speed_bin = ((efuse >> EFUSE_SHIFT_PRO) & EFUSE_MASK_PRO);
+		msm_mmsscc_8996_v3_fixup();
+		if (!gpu_speed_bin)
+			msm_mmsscc_8996_pro_fixup();
+	}
 
 	rc = of_msm_clock_register(pdev->dev.of_node, msm_clocks_mmss_8996,
 				   ARRAY_SIZE(msm_clocks_mmss_8996));
 	if (rc)
 		return rc;
 
-	/* Register v2/v3 specific clocks */
-	if (is_v2 || is_v3) {
+	/* Register v2/v3/pro specific clocks */
+	if (is_v2 || is_v3 || is_pro) {
 		rc = of_msm_clock_register(pdev->dev.of_node,
 				msm_clocks_mmsscc_8996_v2,
 				ARRAY_SIZE(msm_clocks_mmsscc_8996_v2));
@@ -3743,6 +3787,7 @@ static struct of_device_id msm_clock_mmss_match_table[] = {
 	{ .compatible = "qcom,mmsscc-8996" },
 	{ .compatible = "qcom,mmsscc-8996-v2" },
 	{ .compatible = "qcom,mmsscc-8996-v3" },
+	{ .compatible = "qcom,mmsscc-8996-pro" },
 	{},
 };
 
@@ -3807,14 +3852,11 @@ static void msm_gpucc_8996_v2_fixup(void)
 
 int msm_gpucc_8996_probe(struct platform_device *pdev)
 {
-	struct resource *res, *efuse_res;
+	struct resource *res;
 	struct device_node *of_node = pdev->dev.of_node;
-	void __iomem *base;
 	int rc;
 	struct regulator *reg;
-	u64 efuse;
-	int speed_bin;
-	int is_v2_gpu, is_v3_0_gpu;
+	int is_v2_gpu, is_v3_0_gpu, is_pro_gpu;
 	char speedbin_str[] = "qcom,gfxfreq-speedbin0";
 	char mx_speedbin_str[] = "qcom,gfxfreq-mx-speedbin0";
 
@@ -3827,12 +3869,6 @@ int msm_gpucc_8996_probe(struct platform_device *pdev)
 		return -ENOMEM;
 	}
 
-	efuse_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "efuse");
-	if (!efuse_res) {
-		dev_err(&pdev->dev, "Unable to retrieve efuse register base.\n");
-		return -ENOMEM;
-	}
-
 	gfx3d_clk_src_v2.base = virt_base_gpu =  devm_ioremap(&pdev->dev,
 					res->start, resource_size(res));
 	if (!virt_base_gpu) {
@@ -3840,13 +3876,6 @@ int msm_gpucc_8996_probe(struct platform_device *pdev)
 		return -ENOMEM;
 	}
 
-	base = devm_ioremap(&pdev->dev, efuse_res->start,
-					resource_size(efuse_res));
-	if (!base) {
-		dev_err(&pdev->dev, "Unable to map in efuse base\n");
-		return -ENOMEM;
-	}
-
 	reg = vdd_gfx.regulator[0] = devm_regulator_get(&pdev->dev, "vdd_gfx");
 	if (IS_ERR(reg)) {
 		if (PTR_ERR(reg) != -EPROBE_DEFER)
@@ -3874,14 +3903,13 @@ int msm_gpucc_8996_probe(struct platform_device *pdev)
 	is_v2_gpu = of_device_is_compatible(of_node, "qcom,gpucc-8996-v2");
 	is_v3_gpu = of_device_is_compatible(of_node, "qcom,gpucc-8996-v3");
 	is_v3_0_gpu = of_device_is_compatible(of_node, "qcom,gpucc-8996-v3.0");
+	is_pro_gpu = of_device_is_compatible(of_node, "qcom,gpucc-8996-pro");
 
-	efuse = readl_relaxed(base);
-	speed_bin = ((efuse >> EFUSE_SHIFT) & EFUSE_MASK);
-	dev_info(&pdev->dev, "using speed bin %u\n", speed_bin);
+	dev_info(&pdev->dev, "using speed bin %u\n", gpu_speed_bin);
 	snprintf(speedbin_str, ARRAY_SIZE(speedbin_str),
-				"qcom,gfxfreq-speedbin%d", speed_bin);
+				"qcom,gfxfreq-speedbin%d", gpu_speed_bin);
 	snprintf(mx_speedbin_str, ARRAY_SIZE(mx_speedbin_str),
-				"qcom,gfxfreq-mx-speedbin%d", speed_bin);
+				"qcom,gfxfreq-mx-speedbin%d", gpu_speed_bin);
 
 	rc = of_get_fmax_vdd_class(pdev, &gpu_mx_clk.c, mx_speedbin_str);
 	if (rc) {
@@ -3894,7 +3922,7 @@ int msm_gpucc_8996_probe(struct platform_device *pdev)
 		}
 	}
 
-	if (!is_v2_gpu && !is_v3_gpu && !is_v3_0_gpu) {
+	if (!is_v2_gpu && !is_v3_gpu && !is_v3_0_gpu && !is_pro_gpu) {
 		rc = of_get_fmax_vdd_class(pdev, &gfx3d_clk_src.c,
 							speedbin_str);
 		if (rc) {
@@ -3946,6 +3974,7 @@ static struct of_device_id msm_clock_gpu_match_table[] = {
 	{ .compatible = "qcom,gpucc-8996-v2" },
 	{ .compatible = "qcom,gpucc-8996-v3" },
 	{ .compatible = "qcom,gpucc-8996-v3.0" },
+	{ .compatible = "qcom,gpucc-8996-pro" },
 	{},
 };
 
diff --git a/drivers/clk/msm/clock-osm.c b/drivers/clk/msm/clock-osm.c
index f3c9ff7969b4..94007b87b2fc 100644
--- a/drivers/clk/msm/clock-osm.c
+++ b/drivers/clk/msm/clock-osm.c
@@ -115,7 +115,7 @@ enum clk_osm_trace_packet_id {
 #define PLL_LOCK_DET_MASK	BIT(16)
 #define PLL_WAIT_LOCK_TIME_US 5
 #define PLL_WAIT_LOCK_TIME_NS	(PLL_WAIT_LOCK_TIME_US * 1000)
-#define PLL_MIN_LVAL 32
+#define PLL_MIN_LVAL 43
 
 #define CC_ZERO_BEHAV_CTRL 0x100C
 #define SPM_CC_DCVS_DISABLE 0x1020
@@ -1615,7 +1615,7 @@ static void clk_osm_setup_fsms(struct clk_osm *c)
 				  PDN_FSM_CTRL_REG);
 
 		val = clk_osm_read_reg(c, DROOP_UNSTALL_TIMER_CTRL_REG) |
-			BVAL(15, 0, clk_osm_count_ns(c, 1000));
+			BVAL(15, 0, clk_osm_count_ns(c, 5000));
 		clk_osm_write_reg(c, val, DROOP_UNSTALL_TIMER_CTRL_REG);
 	}
 
diff --git a/drivers/media/platform/msm/camera_v2/isp/msm_isp47.c b/drivers/media/platform/msm/camera_v2/isp/msm_isp47.c
index d0ad44c7a276..299476cab3e0 100644
--- a/drivers/media/platform/msm/camera_v2/isp/msm_isp47.c
+++ b/drivers/media/platform/msm/camera_v2/isp/msm_isp47.c
@@ -669,6 +669,7 @@ long msm_vfe47_reset_hardware(struct vfe_device *vfe_dev,
 	uint32_t first_start, uint32_t blocking_call)
 {
 	long rc = 0;
+	uint32_t reset;
 
 	init_completion(&vfe_dev->reset_complete);
 
@@ -676,9 +677,17 @@ long msm_vfe47_reset_hardware(struct vfe_device *vfe_dev,
 		vfe_dev->reset_pending = 1;
 
 	if (first_start) {
-		msm_camera_io_w_mb(0x3FF, vfe_dev->vfe_base + 0x18);
+		if (msm_vfe_is_vfe48(vfe_dev))
+			reset = 0x3F7;
+		else
+			reset = 0x3FF;
+		msm_camera_io_w_mb(reset, vfe_dev->vfe_base + 0x18);
 	} else {
-		msm_camera_io_w_mb(0x3EF, vfe_dev->vfe_base + 0x18);
+		if (msm_vfe_is_vfe48(vfe_dev))
+			reset = 0x3E7;
+		else
+			reset = 0x3EF;
+		msm_camera_io_w_mb(reset, vfe_dev->vfe_base + 0x18);
 		msm_camera_io_w(0x7FFFFFFF, vfe_dev->vfe_base + 0x64);
 		msm_camera_io_w(0xFFFFFEFF, vfe_dev->vfe_base + 0x68);
 		msm_camera_io_w(0x1, vfe_dev->vfe_base + 0x58);
diff --git a/drivers/media/platform/msm/camera_v2/isp/msm_isp48.h b/drivers/media/platform/msm/camera_v2/isp/msm_isp48.h
index a0f1c564dbbb..ccca2010105f 100644
--- a/drivers/media/platform/msm/camera_v2/isp/msm_isp48.h
+++ b/drivers/media/platform/msm/camera_v2/isp/msm_isp48.h
@@ -22,4 +22,14 @@ enum msm_vfe_clk_rates {
 	MSM_VFE_MAX_CLK_RATES = 3,
 };
 
+#define MSM_VFE48_HW_VERSION 0x8
+#define MSM_VFE48_HW_VERSION_SHIFT 28
+#define MSM_VFE48_HW_VERSION_MASK 0xF
+
+static inline int msm_vfe_is_vfe48(struct vfe_device *vfe_dev)
+{
+	return (((vfe_dev->vfe_hw_version >> MSM_VFE48_HW_VERSION_SHIFT) &
+		MSM_VFE48_HW_VERSION_MASK) == MSM_VFE48_HW_VERSION);
+}
+
 #endif /* __MSM_ISP48_H__ */
diff --git a/drivers/media/platform/msm/camera_v2/isp/msm_isp_util.c b/drivers/media/platform/msm/camera_v2/isp/msm_isp_util.c
index 8164aec27315..286ecaca129c 100644
--- a/drivers/media/platform/msm/camera_v2/isp/msm_isp_util.c
+++ b/drivers/media/platform/msm/camera_v2/isp/msm_isp_util.c
@@ -1940,6 +1940,8 @@ int msm_isp_open_node(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
 
 	vfe_dev->hw_info->vfe_ops.core_ops.clear_status_reg(vfe_dev);
 
+	vfe_dev->vfe_hw_version = msm_camera_io_r(vfe_dev->vfe_base);
+	ISP_DBG("%s: HW Version: 0x%x\n", __func__, vfe_dev->vfe_hw_version);
 	rc = vfe_dev->hw_info->vfe_ops.core_ops.reset_hw(vfe_dev, 1, 1);
 	if (rc <= 0) {
 		pr_err("%s: reset timeout\n", __func__);
@@ -1949,8 +1951,6 @@ int msm_isp_open_node(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
 		mutex_unlock(&vfe_dev->realtime_mutex);
 		return -EINVAL;
 	}
-	vfe_dev->vfe_hw_version = msm_camera_io_r(vfe_dev->vfe_base);
-	ISP_DBG("%s: HW Version: 0x%x\n", __func__, vfe_dev->vfe_hw_version);
 
 	vfe_dev->hw_info->vfe_ops.core_ops.init_hw_reg(vfe_dev);
 
diff --git a/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.c b/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.c
index 407a1c10974a..8de2bdde0b6f 100644
--- a/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.c
+++ b/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.c
@@ -1160,6 +1160,11 @@ static int msm_csiphy_release(struct csiphy_device *csiphy_dev, void *arg)
 		msm_camera_io_w(0x0,
 			csiphy_dev->base + csiphy_dev->ctrl_reg->csiphy_3ph_reg.
 			mipi_csiphy_3ph_cmn_ctrl6.addr);
+		if (csiphy_dev->hw_dts_version == CSIPHY_VERSION_V50)
+			msm_camera_io_w(0x0,
+				csiphy_dev->base +
+				csiphy_dev->ctrl_reg->csiphy_3ph_reg.
+				mipi_csiphy_3ph_cmn_ctrl7.addr);
 	} else if (csiphy_dev->hw_version < CSIPHY_VERSION_V30) {
 		csiphy_dev->lane_mask[csiphy_dev->pdev->id] = 0;
 		for (i = 0; i < 4; i++)
@@ -1266,6 +1271,11 @@ static int msm_csiphy_release(struct csiphy_device *csiphy_dev, void *arg)
 		msm_camera_io_w(0x0,
 			csiphy_dev->base + csiphy_dev->ctrl_reg->csiphy_3ph_reg.
 			mipi_csiphy_3ph_cmn_ctrl6.addr);
+		if (csiphy_dev->hw_dts_version == CSIPHY_VERSION_V50)
+			msm_camera_io_w(0x0,
+				csiphy_dev->base +
+				csiphy_dev->ctrl_reg->csiphy_3ph_reg.
+				mipi_csiphy_3ph_cmn_ctrl7.addr);
 	} else	if (csiphy_dev->hw_version < CSIPHY_VERSION_V30) {
 		csiphy_dev->lane_mask[csiphy_dev->pdev->id] = 0;
 		for (i = 0; i < 4; i++)
diff --git a/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c b/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c
index 9c33d8052e71..5dcb25876fd4 100644
--- a/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c
+++ b/drivers/platform/msm/ipa/ipa_v3/rmnet_ipa.c
@@ -82,6 +82,7 @@ enum ipa3_wwan_device_status {
 struct ipa3_rmnet_plat_drv_res {
 	bool ipa_rmnet_ssr;
 	bool ipa_loaduC;
+	bool ipa_advertise_sg_support;
 };
 
 /**
@@ -1219,6 +1220,8 @@ static void apps_ipa_packet_receive_notify(void *priv,
 	dev->stats.rx_bytes += packet_len;
 }
 
+static struct ipa3_rmnet_plat_drv_res ipa3_rmnet_res = {0, };
+
 /**
  * ipa3_wwan_ioctl() - I/O control for wwan network driver.
  *
@@ -1349,6 +1352,15 @@ static int ipa3_wwan_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 				sizeof(struct rmnet_ioctl_extended_s)))
 				rc = -EFAULT;
 			break;
+		/* GET SG support */
+		case RMNET_IOCTL_GET_SG_SUPPORT:
+			extend_ioctl_data.u.data =
+				ipa3_rmnet_res.ipa_advertise_sg_support;
+			if (copy_to_user((u8 *)ifr->ifr_ifru.ifru_data,
+				&extend_ioctl_data,
+				sizeof(struct rmnet_ioctl_extended_s)))
+				rc = -EFAULT;
+			break;
 		/*  Get endpoint ID  */
 		case RMNET_IOCTL_GET_EPID:
 			IPAWANDBG("get ioctl: RMNET_IOCTL_GET_EPID\n");
@@ -1915,8 +1927,6 @@ static struct notifier_block ipa3_ssr_notifier = {
 	.notifier_call = ipa3_ssr_notifier_cb,
 };
 
-static struct ipa3_rmnet_plat_drv_res ipa3_rmnet_res = {0, };
-
 static int get_ipa_rmnet_dts_configuration(struct platform_device *pdev,
 		struct ipa3_rmnet_plat_drv_res *ipa_rmnet_drv_res)
 {
@@ -1930,6 +1940,12 @@ static int get_ipa_rmnet_dts_configuration(struct platform_device *pdev,
 			"qcom,ipa-loaduC");
 	pr_info("IPA ipa-loaduC = %s\n",
 		ipa_rmnet_drv_res->ipa_loaduC ? "True" : "False");
+
+	ipa_rmnet_drv_res->ipa_advertise_sg_support =
+		of_property_read_bool(pdev->dev.of_node,
+		"qcom,ipa-advertise-sg-support");
+	pr_info("IPA SG support = %s\n",
+		ipa_rmnet_drv_res->ipa_advertise_sg_support ? "True" : "False");
 	return 0;
 }
 
@@ -2106,6 +2122,10 @@ static int ipa3_wwan_probe(struct platform_device *pdev)
 		goto set_perf_err;
 	/* IPA_RM configuration ends */
 
+	/* Enable SG support in netdevice. */
+	if (ipa3_rmnet_res.ipa_advertise_sg_support)
+		dev->hw_features |= NETIF_F_SG;
+
 	ret = register_netdev(dev);
 	if (ret) {
 		IPAWANERR("unable to register ipa_netdev %d rc=%d\n",
diff --git a/drivers/power/qcom-charger/smb-lib.c b/drivers/power/qcom-charger/smb-lib.c
index ebbc8e15f2b8..33824479a84d 100644
--- a/drivers/power/qcom-charger/smb-lib.c
+++ b/drivers/power/qcom-charger/smb-lib.c
@@ -47,10 +47,9 @@ int smblib_read(struct smb_charger *chg, u16 addr, u8 *val)
 
 int smblib_masked_write(struct smb_charger *chg, u16 addr, u8 mask, u8 val)
 {
-	unsigned long flags;
 	int rc = 0;
 
-	spin_lock_irqsave(&chg->write_lock, flags);
+	mutex_lock(&chg->write_lock);
 	if (is_secure(chg, addr)) {
 		rc = regmap_write(chg->regmap, (addr & 0xFF00) | 0xD0, 0xA5);
 		if (rc < 0)
@@ -60,16 +59,15 @@ int smblib_masked_write(struct smb_charger *chg, u16 addr, u8 mask, u8 val)
 	rc = regmap_update_bits(chg->regmap, addr, mask, val);
 
 unlock:
-	spin_unlock_irqrestore(&chg->write_lock, flags);
+	mutex_unlock(&chg->write_lock);
 	return rc;
 }
 
 int smblib_write(struct smb_charger *chg, u16 addr, u8 val)
 {
-	unsigned long flags;
 	int rc = 0;
 
-	spin_lock_irqsave(&chg->write_lock, flags);
+	mutex_lock(&chg->write_lock);
 
 	if (is_secure(chg, addr)) {
 		rc = regmap_write(chg->regmap, (addr & ~(0xFF)) | 0xD0, 0xA5);
@@ -80,7 +78,7 @@ int smblib_write(struct smb_charger *chg, u16 addr, u8 val)
 	rc = regmap_write(chg->regmap, addr, val);
 
 unlock:
-	spin_unlock_irqrestore(&chg->write_lock, flags);
+	mutex_unlock(&chg->write_lock);
 	return rc;
 }
 
@@ -1281,7 +1279,7 @@ int smblib_init(struct smb_charger *chg)
 {
 	int rc = 0;
 
-	spin_lock_init(&chg->write_lock);
+	mutex_init(&chg->write_lock);
 	INIT_DELAYED_WORK(&chg->hvdcp_detect_work, smblib_hvdcp_detect_work);
 
 	chg->usb_suspend_votable = create_votable(chg->dev,
diff --git a/drivers/power/qcom-charger/smb-lib.h b/drivers/power/qcom-charger/smb-lib.h
index 6b1037bf4ee7..b688b5ebf0af 100644
--- a/drivers/power/qcom-charger/smb-lib.h
+++ b/drivers/power/qcom-charger/smb-lib.h
@@ -62,7 +62,7 @@ struct smb_charger {
 	int			*debug_mask;
 
 	/* locks */
-	spinlock_t		write_lock;
+	struct mutex		write_lock;
 	struct mutex		ps_change_lock;
 
 	/* power supplies */
diff --git a/include/dt-bindings/clock/msm-clocks-cobalt.h b/include/dt-bindings/clock/msm-clocks-cobalt.h
index 607bcfb9b506..bb2c7b64809a 100644
--- a/include/dt-bindings/clock/msm-clocks-cobalt.h
+++ b/include/dt-bindings/clock/msm-clocks-cobalt.h
@@ -19,14 +19,15 @@
 #define clk_ce1_clk				0x42229c55
 #define clk_ce1_a_clk				0x44a833fe
 #define clk_cxo_clk_src				0x79e95308
-#define clk_pnoc_clk				0x4325d220
-#define clk_pnoc_a_clk				0x2808c12b
 #define clk_bimc_clk				0x4b80bf00
 #define clk_bimc_a_clk				0x4b25668a
 #define clk_cnoc_clk				0xd5ccb7f4
 #define clk_cnoc_a_clk				0xd8fe2ccc
 #define clk_snoc_clk				0x2c341aa0
 #define clk_snoc_a_clk				0x8fcef2af
+#define clk_cnoc_periph_clk			0xb11e9cf9
+#define clk_cnoc_periph_a_clk			0x1d7faa2e
+#define clk_cnoc_periph_keepalive_a_clk		0x7287aef2
 #define clk_ln_bb_clk1				0xb867b147
 #define clk_ln_bb_clk1_ao			0x7f63a93a
 #define clk_ln_bb_clk1_pin			0x6fc5653c
@@ -61,11 +62,6 @@
 #define clk_mcd_ce1_clk				0xbb615d26
 #define clk_mmssnoc_axi_clk			0xdb4b31e6
 #define clk_mmssnoc_axi_a_clk			0xd4970614
-#define clk_pnoc_keepalive_a_clk		0xf8f91f0b
-#define clk_pnoc_msmbus_clk			0x38b95c77
-#define clk_pnoc_msmbus_a_clk			0x8c9b4e93
-#define clk_pnoc_pm_clk				0xd6f7dfb9
-#define clk_pnoc_sps_clk			0xd482ecc7
 #define clk_qcedev_ce1_clk			0x293f97b0
 #define clk_qcrypto_ce1_clk			0xa6ac14df
 #define clk_qdss_clk				0x1492202a
diff --git a/include/dt-bindings/clock/msm-clocks-hwio-cobalt.h b/include/dt-bindings/clock/msm-clocks-hwio-cobalt.h
index a39433fa150f..52a28b5cbaf5 100644
--- a/include/dt-bindings/clock/msm-clocks-hwio-cobalt.h
+++ b/include/dt-bindings/clock/msm-clocks-hwio-cobalt.h
@@ -30,9 +30,9 @@
 
 #define CXO_CLK_SRC_ID						0x0
 #define QDSS_CLK_ID						0x1
-#define PNOC_CLK_ID						0x0
 #define SNOC_CLK_ID						0x1
 #define CNOC_CLK_ID						0x2
+#define CNOC_PERIPH_CLK_ID					0x0
 #define BIMC_CLK_ID						0x0
 #define IPA_CLK_ID						0x0
 #define CE1_CLK_ID						0x0
diff --git a/net/core/neighbour.c b/net/core/neighbour.c
index f18ae91b652e..436822c109d5 100644
--- a/net/core/neighbour.c
+++ b/net/core/neighbour.c
@@ -687,7 +687,7 @@ void neigh_destroy(struct neighbour *neigh)
 	NEIGH_CACHE_STAT_INC(neigh->tbl, destroys);
 
 	if (!neigh->dead) {
-		pr_warn("Destroying alive neighbour %p\n", neigh);
+		pr_warn("Destroying alive neighbour %pK\n", neigh);
 		dump_stack();
 		return;
 	}
diff --git a/sound/core/compress_offload.c b/sound/core/compress_offload.c
index 9d22733f882f..521da22cc80c 100644
--- a/sound/core/compress_offload.c
+++ b/sound/core/compress_offload.c
@@ -503,7 +503,7 @@ static int snd_compress_check_input(struct snd_compr_params *params)
 {
 	/* first let's check the buffer parameter's */
 	if (params->buffer.fragment_size == 0 ||
-	    params->buffer.fragments > INT_MAX / params->buffer.fragment_size)
+	    params->buffer.fragments > U32_MAX / params->buffer.fragment_size)
 		return -EINVAL;
 
 	/* now codec parameters */