diff options
| author | Linux Build Service Account <lnxbuild@localhost> | 2018-10-03 02:42:58 -0700 |
|---|---|---|
| committer | Linux Build Service Account <lnxbuild@localhost> | 2018-10-03 02:42:58 -0700 |
| commit | c76d6044a7b7d5f7adffc1dba89e5c6895573462 (patch) | |
| tree | c2380cf1a1a14edb86da5956089cbc3b7a891ea0 | |
| parent | 76a3a8856b7c6d26b8d61abcdb186fe528b88495 (diff) | |
| parent | f6aeb6b021f631809610fb79df60f2e4e344f3d2 (diff) | |
Merge f6aeb6b021f631809610fb79df60f2e4e344f3d2 on remote branch
Change-Id: I8f10c117a4d217709958a7e0fa01ad5cdf15705d
| -rwxr-xr-x | fw/dbglog.h | 1 | ||||
| -rwxr-xr-x | fw/dbglog_id.h | 318 | ||||
| -rw-r--r-- | fw/htt.h | 508 | ||||
| -rwxr-xr-x | fw/wmi_services.h | 2 | ||||
| -rwxr-xr-x | fw/wmi_tlv_defs.h | 16 | ||||
| -rwxr-xr-x | fw/wmi_unified.h | 1559 | ||||
| -rwxr-xr-x | fw/wmi_version.h | 2 |
7 files changed, 2194 insertions, 212 deletions
diff --git a/fw/dbglog.h b/fw/dbglog.h index 197866c18097..aa29c7a621e7 100755 --- a/fw/dbglog.h +++ b/fw/dbglog.h @@ -81,6 +81,7 @@ extern "C" { /* Debug Log levels*/ typedef enum { + DBGLOG_ML = 0, DBGLOG_VERBOSE = 0, DBGLOG_INFO, DBGLOG_INFO_LVL_1, diff --git a/fw/dbglog_id.h b/fw/dbglog_id.h index 18f6d833e3a0..d8b0d502dc87 100755 --- a/fw/dbglog_id.h +++ b/fw/dbglog_id.h @@ -50,6 +50,324 @@ extern "C" { */ #define DBGLOG_DBGID_SM_FRAMEWORK_PROXY_DBGLOG_MSG 1000 +/* RESMGR messageIDs for ML logging */ +typedef enum { + RESMGR_MSGID_DEFINITION_START = 0x0000, + RESMGR_CHMMGR_CHAINMASK_CHANGE_REQ_MSGID, + RESMGR_CHMMGR_PROCESS_CHM_CHANGE_REQ_MSGID, + RESMGR_CHMMGR_DB_UPDATE_MSGID, + RESMGR_CHMMGR_SEND_HW_MODE_PRE_NOTIF_MSGID, + RESMGR_OCM_SUSPEND_MSGID, + RESMGR_OCM_MIGRATE_MSGID, + RESGMR_OCM_RESUME_MSGID, + RESMGR_OCS_CHREQ_GRANT_MSGID, + RESMGR_OCS_CURR_CAT_WINDOW_MSGID, + RESMGR_OCS_CHREQ_RESTART_MSGID, + RESMGR_OCS_CHREQ_COMPLETE_MSGID, + RESMGR_OCS_WIN_CAT_DUR_MSGID, + RESMGR_OCS_PURGE_CHREQS_MSGID, + RESMGR_OCS_INVOKED_MSGID, + RESMGR_OCS_CHREQ_CREATE_MSGID, + RESMGR_OCS_CHREQ_DELETE_MSGID, + RESMGR_OCS_RECAL_QUOTAS_MSGID, + RESMGR_OCS_CHREQ_START_MSGID, + RESMGR_OCS_CHREQ_STOP_MSGID, + RESMGR_OCS_CHREQ_UPDATE_MSGID, + RESMGR_DBSMGR_SET_HW_MODE_MSGID, + RESMGR_DBSMGR_SET_CONNECTION_IN_PROGRESS_MSGID, + RESMGR_VCM_LINK_CREATE_MSGID, + RESMGR_VCM_LINK_DELETE_MSGID, + RESMGR_VC_INIT_VIR_CHAN_MSGID, + RESMGR_VC_ADD_LINK_MSGID, + RESMGR_VC_RMV_LINK_MSGID, + RESMGR_VC_REGISTER_LINK_MSGID, + RESMGR_VC_UNREGISTER_LINK_MSGID, + RESMGR_VC_ARBITRATE_ATTRIBUTES_MSGID, + RESMGR_DBSMGR_CHANGE_SCAN_STATE_MSGID, + RESMGR_DBSMGR_RECOMPUTE_SCAN_POLICY_MSGID, + RESMGR_DBSMGR_UPDATE_SCAN_POLICY_MSGID, + RESMGR_CHMMGR_INITIATE_VC_OPS_MSGID, + RESMGR_CHMMGR_INITIATE_WAL_OPS_MSGID, + RESMGR_EVENT_HANDLER_VDEV_MGR_MSGID, + RESMGR_EVENT_HANDLER_SCAN_POLICY_MSGID, + RESMGR_MSGID_DEFINITION_END = 0x7fff, +} RESMGR_MSGID; + +/* VDEVMGR messageIDs for ML logging */ +typedef enum { + VDEV_MGR_MSGID_DEFINITION_START = 0x0000, + VDEV_MGR_RESMGR_CHMMGR_NOTIF_VDEV_UP_MSGID, + VDEV_MGR_FIRST_BMISS_DETECTED_MSGID, + VDEV_MGR_FINAL_BMISS_DETECTED_MSGID, + VDEV_MGR_MY_BEACON_RECEIVED_MSGID, + VDEV_MGR_VDEV_PAUSE_MSGID, + VDEV_MGR_VDEV_UNPAUSE_MSGID, + VDEV_MGR_VDEV_MIGRATE_MSGID, + VDEV_MGR_REGISTER_RESMGR_EVENT_MSGID, + VDEV_MGR_EVENT_HANDLER_VDEV_MSGID, + VDEV_MGR_EVENT_HANDLER_BEACON_MSGID, + VDEV_MGR_EVENT_HANDLER_MGMT_TXRX, + VDEV_MGR_EVENT_HANDLER_11D_SCAN_OFFLOAD_MSG_ID, + VDEV_MGR_EVENT_HANDLER_WOW_KEEPALIVE_MSGID, + VDEV_MGR_EVENT_HANDLER_EXTSCAN_MSGID, + VDEV_MGR_EVENT_HANDLER_SWBMISS_MSGID, + VDEV_MGR_EVENT_HANDLER_BEACON_DTIMSYNC_MSGID, + VDEV_MGR_EVENT_HANDLER_BEACON_TSFOOR_MSGID, + VDEV_MGR_THREAD_COMM_BE_FLOW_CTRL_MSGID, + VDEV_MGR_THREAD_COMM_SYNC_RT_DATA_OFFLOAD_MSGID, + VDEV_MGR_THREAD_COMM_BE_VDEV_STATE_CHANGE_MSGID, + VDEV_MGR_THREAD_COMM_VDEV_STATE_CHANGE_CONF_MSGID, + VDEV_MGR_MSGID_DEFINITION_END = 0x7fff, +} VDEV_MGR_MSGID; + +/* SCAN messageIDs for ML logging */ +typedef enum { + SCAN_MSGID_DEFINITION_START = 0x0000, + SCAN_SCH_START_MSGID, + SCAN_EVENT_STARTED_MSGID, + SCAN_EVENT_FOREIGN_CHANNEL_MSGID, + SCAN_EVENT_FOREIGN_CHANNEL_EXIT_MSGID, + SCAN_EVENT_BSS_CHANNEL_MSGID, + SCAN_EVENT_PREEMPTED_MSGID, + SCAN_EVENT_RESTARTED_MSGID, + SCAN_EVENT_COMPLETED_MSGID, + SCAN_EVENT_DEQUEUED_MSGID, + SCAN_EVENT_SUSPENDED_MSGID, + SCAN_SCH_CANCEL_MSGID, + SCAN_SCH_SUSPEND_MSGID, + SCAN_MGR_EVENT_ASYNC_COMPLETE_MSGID, + SCAN_MGR_EVENT_COMPLETED_MSGID, + SCAN_MGR_EVENT_PREEMPTED_MSGID, + SCAN_MGR_EVENT_SUSPENDED_MSGID, + SCAN_POLICY_EVENT_MSGID, + SCAN_MGR_RESUME_EVENT_MSGID, + SCAN_MGR_SCAN_START_MSGID, + SCAN_MGR_CANCEL_MSGID, + SCAN_MGR_BCN_RECV_MSGID, + SCAN_MGR_CHECK_BAND_CHANNELS_MSGID, + SCAN_MGR_SCAN_POLICY_RECOMPUTE_MSGID, + SCAN_MGR_CLIENT_SCAN_POLICY_MSGID, + SCAN_ENG_START_MSGID, + SCAN_ENG_CANCEL_MSGID, + SCAN_SET_CHAN_LIST_MSGID, + SCAN_SEND_PROBE_REQ_RET_VDEV_MSGID, + SCAN_SEND_PROBE_REQ_RET_PASSIVE_MSGID, + SCAN_SEND_PROBE_REQ_2G_RET_MSGID, + SCAN_SEND_PROBE_REQ_5G_RET_MSGID, + SCAN_ADPATIVE_DWELL_ENABLED_MSGID, + SCAN_ADAPTIVE_DWELL_CH_ACTIVITY_START_MSGID, + SCAN_ADAPTIVE_DWELL_CH_ACTIVITY_END_MSGID, + SCAN_ADAPTIVE_DWELL_CH_CONGESTION_CHECK_MSGID, + SCAN_ADAPTIVE_DWELL_ACTIVE_STARTED_MSGID, + SCAN_ADAPTIVE_DWELL_ALL_PROBE_SENT_MSGID, + SCAN_ADAPTIVE_DWELL_PASSIVE_STARTED_MSGID, + SCAN_ADAPTIVE_DWELL_SWITCH_ACTIVE_MSGID, + SCAN_REGISTER_OFFLDMGR_CH_PREDICTION_MSGID, + SCAN_DEREGISTER_OFFLDMGR_CH_PREDICTION_MSGID, + SCAN_REGISTER_OFFLDMGR_ADAPTIVE_BCNPRB_MSGID, + SCAN_DEREGISTER_OFFLDMGR_ADAPTIVE_BCNPRB_MSGID, + SCAN_EVENT_HANDLER_MGMT_TXRX_MSGID, + SCAN_EVENT_HANDLER_NLO_MSGID, + SCAN_EVENT_HANDLER_SCAN_AUTOCHAN_MSGID, + SCAN_EVENT_HANDLER_VDEVMGR_MSGID, + SCAN_EVENT_HANDLER_OFFLOAD_BEACON_MSGID, + SCAN_EVENT_HANDLER_STA_TWT_MSGID, + SCAN_EVENT_HANDLER_BATCH_SCAN_MSGID, + SCAN_MSGID_DEFINITION_END = 0x7fff, +} SCAN_MSGID; + +/* MGMT_TXRX messageIDs for ML logging */ +typedef enum { + MGMT_TXRX_MSGID_DEFINITION_START = 0x0000, + MGMT_TXRX_WAL_LOCAL_FRAME_SEND_MSGID, + MGMT_TXRX_WAL_FRAME_SEND_MSGID, + MGMT_TXRX_FORWARD_TO_HOST_MSGID, + DATA_TXRX_WAL_LOCAL_FRAME_SEND_MSGID, + MGMT_TXRX_MSGID_DEFINITION_END = 0x7fff, +} MGMT_TXRX_MSGID; + +/* OFFLOAD messageIDs for ML logging */ +typedef enum { + OFFLOAD_MSGID_DEFINITION_START = 0x0000, + OFFLOAD_MGMT_RX_FRAME_ALLOW_MSGID, + OFFLOAD_MGMT_RX_FRAME_DROP_MSGID, + OFFLOAD_PROTO_DATA_RX_FRAME_STATUS_MSGID, + OFFLOAD_PROTO_DATA_RX_FRAME_TYPE_MSGID, + OFFLOAD_SCAN_CH_PREDICTION_MSGID, + OFFLOAD_SCAN_ADAPTIVE_BCNPRB_MSGID, + OFFLOAD_VDEV_OWN_BEACON_MSGID, + OFFLOAD_VDEV_BEACON_FILTER_MSGID, + OFFLOAD_VDEV_CONNECTING_MSGID, + OFFLOAD_11D_SCAN_MSGID, + OFFLOAD_BATCH_SCAN_MSGID, + OFFLOAD_OBSS_SCAN_MSGID, + OFFLOAD_ARP_RECV_MSGID, + OFFLOAD_ARP_DROP_MSGID, + OFFLOAD_ARP_REPLY_SUCCESS_MSGID, + OFFLOAD_ARP_REPLY_FAIL_MSGID, + OFFLOAD_NS_RECV_MSGID, + OFFLOAD_NS_DROP_MSGID, + OFFLOAD_NS_REPLY_SUCCESS_MSGID, + OFFLOAD_NS_REPLY_FAIL_MSGID, + OFFLOAD_GTK_PROESS_REKEY_MSGID, + OFFLOAD_GTK_REPLY_REKEY_MSGID, + OFFLOAD_GTK_PROESS_REKEY_FAIL_MSGID, + OFFLOAD_SUPPL_EAP_RECV_MSGID, + OFFLOAD_SUPPL_EAP_1X_MSGID, + OFFLOAD_MSGID_DEFINITION_END = 0x7fff, +} OFFLOAD_MSGID; + +/* STA_PWRSAVE messageIDs for ML logging */ +typedef enum { + STA_PWRSAVE_MSGID_DEFINITION_START = 0x0000, + STA_PWRSAVE_ARBITER_REQUEST_MSGID, + STA_PWRSAVE_MSGID_DEFINITION_END = 0x7fff, +} STA_PWRSAVE_MSGID; + +/* COEX messageIDs for ML logging */ +typedef enum { + COEX_MSGID_DEFINITION_START = 0x0000, + COEX_ASM_ANTENNA_REQUEST_MSGID, + COEX_ASM_ANTENNA_RELEASE_MSGID, + COEX_EVENT_HANDLER_RESMGR_MSGID, + COEX_EVENT_HANDLER_SCAN_ANT_MSGID, + COEX_EVENT_HANDLER_VDEV_ANT_OP_MSGID, + COEX_MSGID_DEFINITION_END = 0x7fff, +} COEX_MSGID; + +/* STA_SMPS messageIDs for ML logging */ +typedef enum { + STA_SMPS_MSGID_DEFINITION_START = 0x0000, + STA_SMPS_VC_CFG_NOTIFY_MSGID, + STA_SMPS_MSGID_EDFINITION_END = 0x7fff, +} STA_SMPS_MSGID; + +/* WAL messageIDs for ML logging */ +typedef enum { + WAL_MSGID_DEFINITION_START = 0x0000, + WAL_PDEV_CHANNEL_CHANGE_MSGID, + WAL_PDEV_HALPHY_RUN_DPD_CAL_MSGID, + WAL_TX_MGMT_COMP_MSGID, + WAL_TX_MGMT_ENQUEUE_MSGID, + WAL_RX_SUSPEND_START_MSGID, + WAL_RX_SUSPEND_SUCCESS_MSGID, + WAL_RX_RESUME_START_MSGID, + WAL_SOC_SWITCH_MODE_MSGID, + WAL_CONNECTION_PAUSE_BLOCK_ENABLE_MSGID, + WAL_CONNECTION_PAUSE_BLOCK_DISABLE_MSGID, + WAL_VDEV_PAUSE_ENABLE_MSGID, + WAL_VDEV_PAUSE_DISABLE_MSGID, + WAL_VDEV_PAUSE_RESET_MSGID, + WAL_PDEV_PAUSE_ENABLE_MSGID, + WAL_PDEV_PAUSE_DISABLE_MSGID, + WAL_PEER_SEND_N_REQ_MSGID, + WAL_PEER_PS_PRE_REQ_MSGID, + WAL_CONNECTION_PAUSE_ATTACH_TID_MSGID, + WAL_PDEV_PAUSE_NOTIFY_VDEV_CREATE_MSGID, + WAL_CONNECTION_PAUSE_PEER_CREATE_MSGID, + WAL_CONNECTION_PAUSE_TIDQ_HWQ_EMPTY_MSGID, + WAL_TX_SEND_ABORT_TX_MSGID, + WAL_TX_SEND_RESUME_TX_MSGID, + WAL_TX_FLUSH_TID_MSGID, + WAL_TX_FLUSH_PEER_MSGID, + WAL_TX_FLUSH_VDEV_MSGID, + WAL_VDEV_UP_MSGID, + WAL_VDEV_START_MSGID, + WAL_VDEV_DOWN_MSGID, + WAL_VDEV_STOP_MSGID, + WAL_VDEV_MIGRATE_MSGID, + WAL_PEER_CONSECUTIVE_FAILURE_MSGID, + WAL_PEER_CONSECUTIVE_FAILURE_RESET_MSGID, + WAL_PEER_STA_KICKOUT_MSGID, + SM_DISPATCH_EVENT_MSGID, + SM_STATE_TRANSITION_MSGID, + WAL_THREAD_COMM_TX_PAUSE_HWQ_EMPTY_MSGID, + WAL_THREAD_COMM_PEER_TX_PAUSE_REQ_MSGID, + WAL_THREAD_COMM_PEER_TX_UNPAUSE_REQ_MSGID, + WAL_THREAD_COMM_VDEV_TX_PAUSE_REQ_MSGID, + WAL_THREAD_COMM_PDEV_TX_PAUSE_REQ_MSGID, + WAL_THREAD_COMM_VDEV_TX_UNPAUSE_REQ_MSGID, + WAL_THREAD_COMM_PDEV_TX_UNPAUSE_REQ_MSGID, + WAL_THREAD_COMM_VDEV_TX_PAUSE_RESET_IND_MSGID, + WAL_THREAD_COMM_PEER_TX_BLOCK_REQ_MSGID, + WAL_THREAD_COMM_PEER_TX_UNBLOCK_REQ_MSGID, + WAL_THREAD_COMM_PEER_SEND_N_REQ_MSGID, + WAL_THREAD_COMM_PEER_PS_PRE_REQ_MSGID, + WAL_THREAD_COMM_TX_PAUSE_TID_CREATE_MSGID, + WAL_THREAD_COMM_TX_PAUSE_VDEV_CREATE_MSGID, + WAL_THREAD_COMM_TX_PAUSE_POST_RESPONSE_MSGID, + WAL_THREAD_COMM_PDEV_EVENT_HANDLER_MSGID, + WAL_THREAD_COMM_VDEV_EVENT_HANDLER_MSGID, + WAL_THREAD_COMM_PEER_EVENT_HANDLER_MSGID, + WAL_THREAD_COMM_POWER_MSGID, + WAL_THREAD_COMM_RT_POWER_BEACON_TIMEOUT_MSGID, + WAL_THREAD_COMM_RT_POWER_SUSPEND_FAIL_RESET_MSGID, + WAL_THREAD_COMM_RT_DATA_NULL_DEAUTH_MSGID, + WAL_THREAD_COMM_LOCAL_SEND_WITH_RATE_MSGID, + WAL_THREAD_COMM_LOCAL_SEND_COMPLETION_MSGID, + WAL_THREAD_COMM_TX_FLUSH_ENTITY_TID_MSGID, + WAL_THREAD_COMM_TX_FLUSH_ENTITY_PEER_MSGID, + WAL_THREAD_COMM_TX_FLUSH_ENTITY_VDEV_MSGID, + WAL_THREAD_COMM_TX_FLUSH_COMPLETE_MSGID, + WAL_THREAD_COMM_TAC_TID_LIST_OP_MSGID, + WAL_THREAD_COMM_TAC_TX_SCHED_MSGID, + WAL_THREAD_COMM_BE_RX_ATTACH_MSGID, + WAL_THREAD_COMM_TT_CONTROL_MSGID, + WAL_THREAD_COMM_RT_EXEC_DEV_RESET_MSGID, + WAL_THREAD_COMM_VDEV_MIGRATION_SYNC_MSGID, + WAL_THREAD_COMM_BE_SOC_SUSPEND_NOTIFY_MSGID, + WAL_THREAD_COMM_RT_SOC_SUSPEND_CONF_MSGID, + WAL_THREAD_COMM_TX_ABORT_MSGID, + WAL_THREAD_COMM_TX_RESUME_MSGID, + WAL_THREAD_COMM_RT_WPM_EXIT_HW_DTIM_AWAKE_MSGID, + WAL_THREAD_COMM_BE_RX_PROC_MSGID, + WAL_THREAD_COMM_BE_PEER_SET_PARAM_MSGID, + WAL_THREAD_COMM_PEER_SEND_MSG_MSGID, + WAL_THREAD_COMM_TID_DEL_MSGID, + WAL_TX_PAUSE_REQ_HANDLER_MSGID, + WAL_TX_PAUSE_RSP_HANDLER_MSGID, + WAL_SW_DTIM_POWER_MSG_HANDLER_MSGID, + WAL_PEER_KEY_SET_MSGID, + WAL_PEER_WAPI_EAPOL_TX_SEND_COMPLETE_MSGID, + WAL_PEER_PTK_M4_SENT_MSGID, + WAL_PEER_ALLOW_DATA_MSGID, + WAL_EVENT_HANDLER_VDEV_PAUSE_MSGID, + WAL_EVENT_HANDLER_STA_SWTIM_MSGID, + WAL_EVENT_HANDLER_VDEV_RECONFIG_MSGID, + WAL_MSGID_DEFINITION_END = 0x7fff, +} WAL_MSGID; + +/* WPM messageIDs for ML logging */ +typedef enum { + WPM_MSGID_DEFINITION_START = 0x0000, + WPM_ARBITER_REQUEST_MSGID, + WPM_MSGID_DEFINITION_END = 0x7fff, +} WPM_MSGID; + +/* MLME messageIDs for ML logging */ +typedef enum { + MLME_MSGID_DEFINITION_START = 0x0000, + MLME_THREAD_COMM_BE_HTT_SVC_VDEV_CHANGE_MSGID, + MLME_THREAD_COMM_INSTALL_KEY_MSGID, + MLME_THREAD_COMM_STORE_KEY_MSGID, + MLME_THREAD_COMM_UPDATE_STATUS_MSGID, + MLME_THREAD_COMM_CMD_PROXY_MSGID, + MLME_MSGID_DEFINITION_END = 0x7fff, +} MLME_MSGID; + +typedef enum { + SUPPL_MSGID_DEFINITION_START = 0x0000, + SUPPL_THREAD_COMM_INIT_AUTH_MSGID, + SUPPL_THREAD_COMM_STATUS_CHANGE_EVT_MSGID, + SUPPL_MSGID_DEFINITION_END = 0x7fff, +} SUPPL_MSGID; + +typedef enum { + AP_PWRSAVE_MSGID_DEFINITION_START = 0x0000, + AP_PWRSAVE_EVENT_HANDLER_SLEEP_STA_UPDATE_MSGID, + AP_PWRSAVE_MSGID_DEFINITION_END = 0x7fff, +} AP_PWRSAVE_MSGID; + /* INF debug identifier definitions */ #define INF_DBGID_DEFINITION_START 0 @@ -170,9 +170,10 @@ * 3.53 Update HTT_T2H FLOW_POOL_RESIZE msg def * 3.54 Define mcast and mcast_valid flags within htt_tx_wbm_transmit_status * 3.55 Add initiator / responder flags to RX_DELBA indication + * 3.56 Fix HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE bit-mask defs */ #define HTT_CURRENT_VERSION_MAJOR 3 -#define HTT_CURRENT_VERSION_MINOR 55 +#define HTT_CURRENT_VERSION_MINOR 56 #define HTT_NUM_TX_FRAG_DESC 1024 @@ -4994,23 +4995,23 @@ PREPACK struct htt_rx_ring_selection_cfg_t { #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_0111_S 23 /* Beacon */ -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_1000_M 0x01000001 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_1000_M 0x01000000 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_1000_S 24 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_1000_M 0x02000001 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_1000_M 0x02000000 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_1000_S 25 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_1000_M 0x00000001 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_1000_M 0x04000000 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_1000_S 26 /* ATIM */ -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_1001_M 0x00000001 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_1001_M 0x08000000 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_FP_MGMT_1001_S 27 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_1001_M 0x00000001 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_1001_M 0x10000000 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MD_MGMT_1001_S 28 -#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_1001_M 0x00000001 +#define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_1001_M 0x20000000 #define HTT_RX_RING_SELECTION_CFG_PKT_TYPE_ENABLE_FLAG0_MO_MGMT_1001_S 29 /* Disassociation */ @@ -5597,6 +5598,7 @@ enum htt_t2h_msg_type { HTT_T2H_MSG_TYPE_PEER_UNMAP_V2 = 0x1f, HTT_T2H_MSG_TYPE_MONITOR_MAC_HEADER_IND = 0x20, HTT_T2H_MSG_TYPE_FLOW_POOL_RESIZE = 0x21, + HTT_T2H_MSG_TYPE_CFR_DUMP_COMPL_IND = 0x22, HTT_T2H_MSG_TYPE_TEST, /* keep this last */ @@ -10589,4 +10591,496 @@ PREPACK struct htt_flow_pool_resize_t { ((_var) |= ((_val) << HTT_FLOW_POOL_RESIZE_FLOW_POOL_NEW_SIZE_S)); \ } while (0) +/** + * @brief host -> target channel change message + * + * @details + * the meesage is generated by FW every time FW changes channel. This will be used by host mainly + * to associate RX frames to correct channel they were received on. + * The following field definitions describe the format of the HTT target + * to host channel change message. + * |31 16|15 8|7 5|4 0| + * |------------------------------------------------------------| + * | reserved | MSG_TYPE | + * |------------------------------------------------------------| + * | CHAN_MHZ | + * |------------------------------------------------------------| + * | BAND_CENTER_FREQ1 | + * |------------------------------------------------------------| + * | BAND_CENTER_FREQ2 | + * |------------------------------------------------------------| + * | CHAN_PHY_MODE | + * |------------------------------------------------------------| + * Header fields: + * - MSG_TYPE + * Bits 7:0 + * Value: 0xf + * - CHAN_MHZ + * Bits 31:0 + * Purpose: frequency of the primary 20mhz channel. + * - BAND_CENTER_FREQ1 + * Bits 31:0 + * Purpose: centre frequency of the full channel. + * - BAND_CENTER_FREQ2 + * Bits 31:0 + * Purpose: centre frequency2 of the channel. is only valid for 11acvht 80plus80. + * - CHAN_PHY_MODE + * Bits 31:0 + * Purpose: phy mode of the channel. +*/ + +PREPACK struct htt_chan_change_msg { + A_UINT32 chan_mhz; /* frequency in mhz */ + + A_UINT32 band_center_freq1; /* Center frequency 1 in MHz*/ + + A_UINT32 band_center_freq2; /* Center frequency 2 in MHz - valid only for 11acvht 80plus80 mode*/ + + A_UINT32 chan_mode; /* WLAN_PHY_MODE of the channel defined in wlan_defs.h */ +} POSTPACK; + +#define HTT_CFR_CAPTURE_MAGIC_PATTERN 0xCCCCCCCC +#define HTT_CFR_CAPTURE_READ_INDEX_OFFSET 0 /* bytes */ +#define HTT_CFR_CAPTURE_SIZEOF_READ_INDEX_BYTES 4 +#define HTT_CFR_CAPTURE_WRITE_INDEX_OFFSET /* bytes */ \ + (HTT_CFR_CAPTURE_READ_INDEX_OFFSET + HTT_CFR_CAPTURE_SIZEOF_READ_INDEX_BYTES) +#define HTT_CFR_CAPTURE_SIZEOF_WRITE_INDEX_BYTES 4 +#define HTT_CFR_CAPTURE_SIZEOF_MAGIC_PATTERN_BYTES 4 +/* + * The read and write indices point to the data within the host buffer. + * Because the first 4 bytes of the host buffer is used for the read index and + * the next 4 bytes for the write index, the data itself starts at offset 8. + * The read index and write index are the byte offsets from the base of the + * meta-data buffer, and thus have a minimum value of 8 rather than 0. + * Refer the ASCII text picture below. + */ +#define HTT_CFR_CAPTURE_INITIAL_RW_START_INDEX \ + (HTT_CFR_CAPTURE_SIZEOF_READ_INDEX_BYTES + \ + HTT_CFR_CAPTURE_SIZEOF_WRITE_INDEX_BYTES) + +/* + *************************************************************************** + * + * Layout when CFR capture message type is 'HTT_PEER_CFR_CAPTURE_MSG_TYPE_1' + * + *************************************************************************** + * + * The memory allocated by WMI_CHANNEL_CAPTURE_HOST_MEM_REQ_ID is used + * in the below format. The HTT message 'htt_cfr_dump_compl_ind' is sent by + * FW to Host whenever a CFR capture (CFR data1 or CFR data2 etc.,) is + * written into the Host memory region mentioned below. + * + * Read index is updated by the Host. At any point of time, the read index will + * indicate the index that will next be read by the Host. The read index is + * in units of bytes offset from the base of the meta-data buffer. + * + * Write index is updated by the FW. At any point of time, the write index will + * indicate from where the FW can start writing any new data. The write index is + * in units of bytes offset from the base of the meta-data buffer. + * + * If the Host is not fast enough in reading the CFR data, any new capture data + * would be dropped if there is no space left to write the new captures. + * + * The last 4 bytes of the memory region will have the magic pattern + * HTT_CFR_CAPTURE_MAGIC_PATTERN. This can be used to ensure that the FW does + * not overrun the host buffer. + * + * ,--------------------. read and write indices store the + * | | byte offset from the base of the + * | ,--------+--------. meta-data buffer to the next + * | | | | location within the data buffer + * | | v v that will be read / written + * ************************************************************************ + * * Read * Write * * Magic * + * * index * index * CFR data1 ...... CFR data N * pattern * + * * (4 bytes) * (4 bytes) * * (4 bytes)* + * ************************************************************************ + * |<---------- data buffer ---------->| + * + * |<----------------- meta-data buffer allocated in Host ----------------| + * + * Note: + * - Considering the 4 bytes needed to store the Read index (R) and the + * Write index (W), the initial value is as follows: + * R = W = HTT_CFR_CAPTURE_INITIAL_RW_START_INDEX + * - Buffer empty condition: + * R = W + * + * Regarding CFR data format: + * -------------------------- + * + * Each CFR tone is stored in HW as 16-bits with the following format: + * {bits[15:12], bits[11:6], bits[5:0]} = + * {unsigned exponent (4 bits), + * signed mantissa_real (6 bits), + * signed mantissa_imag (6 bits)} + * + * CFR_real = mantissa_real * 2^(exponent-5) + * CFR_imag = mantissa_imag * 2^(exponent-5) + * + * + * The CFR data is written to the 16-bit unsigned output array (buff) in + * ascending tone order. For example, the Legacy20 CFR is output as follows: + * + * buff[0]: [CFR_exp[-26], CFR_mant_real[-26], CFR_mant_imag[-26]] + * buff[1]: [CFR_exp[-25], CFR_mant_real[-25], CFR_mant_imag[-25]] + * . + * . + * . + * buff[N-2]: [CFR_exp[25], CFR_mant_real[25], CFR_mant_imag[25]] + * buff[N-1]: [CFR_exp[26], CFR_mant_real[26], CFR_mant_imag[26]] + */ + +/* Bandwidth of peer CFR captures */ +typedef enum { + HTT_PEER_CFR_CAPTURE_BW_20MHZ = 0, + HTT_PEER_CFR_CAPTURE_BW_40MHZ = 1, + HTT_PEER_CFR_CAPTURE_BW_80MHZ = 2, + HTT_PEER_CFR_CAPTURE_BW_160MHZ = 3, + HTT_PEER_CFR_CAPTURE_BW_80_80MHZ = 4, + HTT_PEER_CFR_CAPTURE_BW_MAX, +} HTT_PEER_CFR_CAPTURE_BW; + +/* Mode of the peer CFR captures. The type of RX frame for which the CFR + * was captured + */ +typedef enum { + HTT_PEER_CFR_CAPTURE_MODE_LEGACY = 0, + HTT_PEER_CFR_CAPTURE_MODE_DUP_LEGACY = 1, + HTT_PEER_CFR_CAPTURE_MODE_HT = 2, + HTT_PEER_CFR_CAPTURE_MODE_VHT = 3, + HTT_PEER_CFR_CAPTURE_MODE_MAX, +} HTT_PEER_CFR_CAPTURE_MODE; + +typedef enum { + /* This message type is currently used for the below purpose: + * + * - capture_method = WMI_PEER_CFR_CAPTURE_METHOD_NULL_FRAME in the + * wmi_peer_cfr_capture_cmd. The associated memory region gets allocated + * through WMI_CHANNEL_CAPTURE_HOST_MEM_REQ_ID + */ + HTT_PEER_CFR_CAPTURE_MSG_TYPE_1 = 0x1, + + /* Always keep this last */ + HTT_PEER_CFR_CAPTURE_MSG_TYPE_MAX, +} HTT_PEER_CFR_CAPTURE_MSG_TYPE; + +/** + * @brief target -> host CFR dump completion indication message definition + * htt_cfr_dump_compl_ind when the version is HTT_PEER_CFR_CAPTURE_MSG_TYPE_1. + * + * @details + * The following diagram shows the format of the Channel Frequency Response + * (CFR) dump completion indication. This inidcation is sent to the Host when + * the channel capture of a peer is copied by Firmware into the Host memory + * + * ************************************************************************** + * + * Message format when the CFR capture message type is + * 'HTT_PEER_CFR_CAPTURE_MSG_TYPE_1' + * + * ************************************************************************** + * + * |31 16|15 |7 0| + * |----------------------------------------------------------------| + * header: | reserved | msg_type | + * word 0 | | | + * |----------------------------------------------------------------| + * payload: | cfr_capture_msg_type | + * word 1 | | + * |----------------------------------------------------------------| + * | vdev_id | captype | chbw | sts | mode | capbw |S| req_id | + * word 2 | | | | | | | | | + * |----------------------------------------------------------------| + * | mac_addr31to0 | + * word 3 | | + * |----------------------------------------------------------------| + * | unused / reserved | mac_addr47to32 | + * word 4 | | | + * |----------------------------------------------------------------| + * | index | + * word 5 | | + * |----------------------------------------------------------------| + * | length | + * word 6 | | + * |----------------------------------------------------------------| + * | timestamp | + * word 7 | | + * |----------------------------------------------------------------| + * | counter | + * word 8 | | + * |----------------------------------------------------------------| + * | chan_mhz | + * word 9 | | + * |----------------------------------------------------------------| + * | band_center_freq1 | + * word 10 | | + * |----------------------------------------------------------------| + * | band_center_freq2 | + * word 11 | | + * |----------------------------------------------------------------| + * | chan_phy_mode | + * word 12 | | + * |----------------------------------------------------------------| + * where, + * req_id - memory request id (mem_req_id explained below) + * S - status field (status explained below) + * capbw - capture bandwidth (capture_bw explained below) + * mode - mode of capture (mode explained below) + * sts - space time streams (sts_count explained below) + * chbw - channel bandwidth (channel_bw explained below) + * captype - capture type (cap_type explained below) + * + * The following field definitions describe the format of the CFR dump + * completion indication sent from the target to the host + * + * Header fields: + * + * Word 0 + * - msg_type + * Bits 7:0 + * Purpose: Identifies this as CFR TX completion indication + * Value: HTT_T2H_MSG_TYPE_CFR_DUMP_COMPL_IND + * - reserved + * Bits 31:8 + * Purpose: Reserved + * Value: 0 + * + * Payload fields: + * + * Word 1 + * - cfr_capture_msg_type + * Bits 31:0 + * Purpose: Contains the type of the message HTT_PEER_CFR_CAPTURE_MSG_TYPE + * to specify the format used for the remainder of the message + * Value: HTT_PEER_CFR_CAPTURE_MSG_TYPE_1 + * (currently only MSG_TYPE_1 is defined) + * + * Word 2 + * - mem_req_id + * Bits 6:0 + * Purpose: Contain the mem request id of the region where the CFR capture + * has been stored - of type WMI_HOST_MEM_REQ_ID + * Value: WMI_CHANNEL_CAPTURE_HOST_MEM_REQ_ID + * - status + * Bit 7 + * Purpose: Boolean value carrying the status of the CFR capture of the peer + * Value: 1 (True) - Successful; 0 (False) - Not successful + * - capture_bw + * Bits 10:8 + * Purpose: Carry the bandwidth of the CFR capture + * Value: Bandwidth of the CFR capture of type HTT_PEER_CFR_CAPTURE_BW + * - mode + * Bits 13:11 + * Purpose: Carry the mode of the rx frame for which the CFR was captured + * Value: Mode of the CFR capture of type HTT_PEER_CFR_CAPTURE_MODE + * - sts_count + * Bits 16:14 + * Purpose: Carry the number of space time streams + * Value: Number of space time streams + * - channel_bw + * Bits 19:17 + * Purpose: Carry the bandwidth of the channel of the vdev performing the + * measurement + * Value: Bandwidth of the channel (of type HTT_PEER_CFR_CAPTURE_BW) + * - cap_type + * Bits 23:20 + * Purpose: Carry the type of the capture + * Value: Capture type (of type WMI_PEER_CFR_CAPTURE_METHOD) + * - vdev_id + * Bits 31:24 + * Purpose: Carry the virtual device id + * Value: vdev ID + * + * Word 3 + * - mac_addr31to0 + * Bits 31:0 + * Purpose: Contain the bits 31:0 of the peer MAC address + * Value: Bits 31:0 of the peer MAC address + * + * Word 4 + * - mac_addr47to32 + * Bits 15:0 + * Purpose: Contain the bits 47:32 of the peer MAC address + * Value: Bits 47:32 of the peer MAC address + * + * Word 5 + * - index + * Bits 31:0 + * Purpose: Contain the index at which this CFR dump was written in the Host + * allocated memory. This index is the number of bytes from the base address. + * Value: Index position + * + * Word 6 + * - length + * Bits 31:0 + * Purpose: Carry the length of the CFR capture of the peer, in bytes + * Value: Length of the CFR capture of the peer + * + * Word 7 + * - timestamp + * Bits 31:0 + * Purpose: Carry the time at which the CFR was captured in the hardware. The + * clock used for this timestamp is private to the target and not visible to + * the host i.e., Host can interpret only the relative timestamp deltas from + * one message to the next, but can't interpret the absolute timestamp from a + * single message. + * Value: Timestamp in microseconds + * + * Word 8 + * - counter + * Bits 31:0 + * Purpose: Carry the count of the current CFR capture from FW. This is + * helpful to identify any drops in FW in any scenario (e.g., lack of space + * in host memory) + * Value: Count of the current CFR capture + * + * Word 9 + * - chan_mhz + * Bits 31:0 + * Purpose: Carry the primary 20 MHz channel frequency in MHz of the VDEV + * Value: Primary 20 channel frequency + * + * Word 10 + * - band_center_freq1 + * Bits 31:0 + * Purpose: Carry the center frequency 1 in MHz of the VDEV + * Value: Center frequency 1 in MHz + * + * Word 11 + * - band_center_freq2 + * Bits 31:0 + * Purpose: Carry the center frequency 2 in MHz. valid only for 11acvht of + * the VDEV + * 80plus80 mode + * Value: Center frequency 2 in MHz + * + * Word 12 + * - chan_phy_mode + * Bits 31:0 + * Purpose: Carry the phy mode of the channel, of the VDEV + * Value: WLAN_PHY_MODE of the channel defined in wlan_defs.h + */ +PREPACK struct htt_cfr_dump_ind_type_1 { + A_UINT32 mem_req_id:7, + status:1, + capture_bw:3, + mode:3, + sts_count:3, + channel_bw:3, + cap_type:4, + vdev_id:8; + htt_mac_addr addr; + A_UINT32 index; + A_UINT32 length; + A_UINT32 timestamp; + A_UINT32 counter; + struct htt_chan_change_msg chan; +} POSTPACK; + +PREPACK struct htt_cfr_dump_compl_ind { + A_UINT32 msg_type; /* HTT_PEER_CFR_CAPTURE_MSG_TYPE */ + union { + /* Message format when msg_type = HTT_PEER_CFR_CAPTURE_MSG_TYPE_1 */ + struct htt_cfr_dump_ind_type_1 htt_cfr_dump_compl_ind_type_1; + /* If there is a need to change the memory layout and its associated + * HTT indication format, a new CFR capture message type can be + * introduced and added into this union. + */ + }; +} POSTPACK; + +/* + * Get / set macros for the bit fields within WORD-2 of htt_cfr_dump_compl_ind, + * msg_type = HTT_PEER_CFR_CAPTURE_MSG_TYPE_1 + */ +#define HTT_T2H_CFR_DUMP_TYPE1_MEM_REQ_ID_M 0X0000007F +#define HTT_T2H_CFR_DUMP_TYPE1_MEM_REQ_ID_S 0 +#define HTT_T2H_CFR_DUMP_TYPE1_STATUS_M 0X00000080 +#define HTT_T2H_CFR_DUMP_TYPE1_STATUS_S 7 +#define HTT_T2H_CFR_DUMP_TYPE1_CAP_BW_M 0X00000700 +#define HTT_T2H_CFR_DUMP_TYPE1_CAP_BW_S 8 +#define HTT_T2H_CFR_DUMP_TYPE1_MODE_M 0X00003800 +#define HTT_T2H_CFR_DUMP_TYPE1_MODE_S 11 +#define HTT_T2H_CFR_DUMP_TYPE1_STS_M 0X0001C000 +#define HTT_T2H_CFR_DUMP_TYPE1_STS_S 14 +#define HTT_T2H_CFR_DUMP_TYPE1_CHAN_BW_M 0X000E0000 +#define HTT_T2H_CFR_DUMP_TYPE1_CHAN_BW_S 17 +#define HTT_T2H_CFR_DUMP_TYPE1_CAP_TYPE_M 0X00F00000 +#define HTT_T2H_CFR_DUMP_TYPE1_CAP_TYPE_S 20 +#define HTT_T2H_CFR_DUMP_TYPE1_VDEV_ID_M 0XFF000000 +#define HTT_T2H_CFR_DUMP_TYPE1_VDEV_ID_S 24 + +#define HTT_T2H_CFR_DUMP_TYPE1_MEM_REQ_ID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_T2H_CFR_DUMP_TYPE1_MEM_REQ_ID, value); \ + (word) |= (value) << HTT_T2H_CFR_DUMP_TYPE1_MEM_REQ_ID_S; \ + } while (0) +#define HTT_T2H_CFR_DUMP_TYPE1_MEM_REQ_ID_GET(word) \ + (((word) & HTT_T2H_CFR_DUMP_TYPE1_MEM_REQ_ID_M) >> \ + HTT_T2H_CFR_DUMP_TYPE1_MEM_REQ_ID_S) + +#define HTT_T2H_CFR_DUMP_TYPE1_STATUS_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_T2H_CFR_DUMP_TYPE1_STATUS, value); \ + (word) |= (value) << HTT_T2H_CFR_DUMP_TYPE1_STATUS_S; \ + } while (0) +#define HTT_T2H_CFR_DUMP_TYPE1_STATUS_GET(word) \ + (((word) & HTT_T2H_CFR_DUMP_TYPE1_STATUS_M) >> \ + HTT_T2H_CFR_DUMP_TYPE1_STATUS_S) + +#define HTT_T2H_CFR_DUMP_TYPE1_CAP_BW_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_T2H_CFR_DUMP_TYPE1_CAP_BW, value); \ + (word) |= (value) << HTT_T2H_CFR_DUMP_TYPE1_CAP_BW_S; \ + } while (0) +#define HTT_T2H_CFR_DUMP_TYPE1_CAP_BW_GET(word) \ + (((word) & HTT_T2H_CFR_DUMP_TYPE1_CAP_BW_M) >> \ + HTT_T2H_CFR_DUMP_TYPE1_CAP_BW_S) + +#define HTT_T2H_CFR_DUMP_TYPE1_MODE_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_T2H_CFR_DUMP_TYPE1_MODE, value); \ + (word) |= (value) << HTT_T2H_CFR_DUMP_TYPE1_MODE_S; \ + } while (0) +#define HTT_T2H_CFR_DUMP_TYPE1_MODE_GET(word) \ + (((word) & HTT_T2H_CFR_DUMP_TYPE1_MODE_M) >> \ + HTT_T2H_CFR_DUMP_TYPE1_MODE_S) + +#define HTT_T2H_CFR_DUMP_TYPE1_STS_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_T2H_CFR_DUMP_TYPE1_STS, value); \ + (word) |= (value) << HTT_T2H_CFR_DUMP_TYPE1_STS_S; \ + } while (0) +#define HTT_T2H_CFR_DUMP_TYPE1_STS_GET(word) \ + (((word) & HTT_T2H_CFR_DUMP_TYPE1_STS_M) >> \ + HTT_T2H_CFR_DUMP_TYPE1_STS_S) + +#define HTT_T2H_CFR_DUMP_TYPE1_CHAN_BW_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_T2H_CFR_DUMP_TYPE1_CHAN_BW, value); \ + (word) |= (value) << HTT_T2H_CFR_DUMP_TYPE1_CHAN_BW_S; \ + } while (0) +#define HTT_T2H_CFR_DUMP_TYPE1_CHAN_BW_GET(word) \ + (((word) & HTT_T2H_CFR_DUMP_TYPE1_CHAN_BW_M) >> \ + HTT_T2H_CFR_DUMP_TYPE1_CHAN_BW_S) + +#define HTT_T2H_CFR_DUMP_TYPE1_CAP_TYPE_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_T2H_CFR_DUMP_TYPE1_CAP_TYPE, value); \ + (word) |= (value) << HTT_T2H_CFR_DUMP_TYPE1_CAP_TYPE_S; \ + } while (0) +#define HTT_T2H_CFR_DUMP_TYPE1_CAP_TYPE_GET(word) \ + (((word) & HTT_T2H_CFR_DUMP_TYPE1_CAP_TYPE_M) >> \ + HTT_T2H_CFR_DUMP_TYPE1_CAP_TYPE_S) + +#define HTT_T2H_CFR_DUMP_TYPE1_VDEV_ID_SET(word, value) \ + do { \ + HTT_CHECK_SET_VAL(HTT_T2H_CFR_DUMP_TYPE1_VDEV_ID, value); \ + (word) |= (value) << HTT_T2H_CFR_DUMP_TYPE1_VDEV_ID_S; \ + } while (0) +#define HTT_T2H_CFR_DUMP_TYPE1_VDEV_ID_GET(word) \ + (((word) & HTT_T2H_CFR_DUMP_TYPE1_VDEV_ID_M) >> \ + HTT_T2H_CFR_DUMP_TYPE1_VDEV_ID_S) + #endif diff --git a/fw/wmi_services.h b/fw/wmi_services.h index 49e8623ad25d..a67dada36748 100755 --- a/fw/wmi_services.h +++ b/fw/wmi_services.h @@ -261,6 +261,8 @@ typedef enum { WMI_SERVICE_NDI_DBS_SUPPORT=165, /* Support DBS for NAN data interface */ WMI_SERVICE_NAN_SAP_SUPPORT=166, /* Support SAP Concurrency for NAN Discovery interface */ WMI_SERVICE_NDI_SAP_SUPPORT=167, /* Support SAP Concurrency for NAN Data interface */ + WMI_SERVICE_CFR_CAPTURE_SUPPORT=168, /* Support to capture uncompressed Channel Frequency Response (CFR) */ + WMI_SERVICE_CFR_CAPTURE_IND_MSG_TYPE_1=169, /* Message type HTT_PEER_CFR_CAPTURE_MSG_TYPE_1 in HTT_T2H_MSG_TYPE_CFR_DUMP_COMPL_IND */ /******* ADD NEW SERVICES HERE *******/ diff --git a/fw/wmi_tlv_defs.h b/fw/wmi_tlv_defs.h index 44ac30532a07..96c2b9176c7b 100755 --- a/fw/wmi_tlv_defs.h +++ b/fw/wmi_tlv_defs.h @@ -927,6 +927,9 @@ typedef enum { WMITLV_TAG_STRUC_wmi_esp_estimate_event_fixed_param, WMITLV_TAG_STRUC_wmi_nan_host_config_param, WMITLV_TAG_STRUC_wmi_spectral_bin_scaling_params, + WMITLV_TAG_STRUC_wmi_peer_cfr_capture_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_peer_chan_width_switch_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_chan_width_peer_list, } WMITLV_TAG_ID; /* @@ -1305,6 +1308,8 @@ typedef enum { OP(WMI_MOTION_DET_START_STOP_CMDID) \ OP(WMI_MOTION_DET_BASE_LINE_START_STOP_CMDID) \ OP(WMI_PDEV_OBSS_PD_SPATIAL_REUSE_CMDID) \ + OP(WMI_PEER_CFR_CAPTURE_CMDID) \ + OP(WMI_PEER_CHAN_WIDTH_SWITCH_CMDID) \ /* add new CMD_LIST elements above this line */ @@ -3758,6 +3763,17 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PEER_TID_CONFIGURATIONS_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_obss_spatial_reuse_set_cmd_fixed_param, wmi_obss_spatial_reuse_set_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_OBSS_PD_SPATIAL_REUSE_CMDID); +/* Peer CFR capture cmd */ +#define WMITLV_TABLE_WMI_PEER_CFR_CAPTURE_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_cfr_capture_cmd_fixed_param, wmi_peer_cfr_capture_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_PEER_CFR_CAPTURE_CMDID); + +/* CHANNEL WIDTH SWITCH commands for peers. */ +#define WMITLV_TABLE_WMI_PEER_CHAN_WIDTH_SWITCH_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_chan_width_switch_cmd_fixed_param, wmi_peer_chan_width_switch_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_chan_width_peer_list, peer_info, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_PEER_CHAN_WIDTH_SWITCH_CMDID); + /************************** TLV definitions of WMI events *******************************/ diff --git a/fw/wmi_unified.h b/fw/wmi_unified.h index 17027f23574d..17d5a0791cfa 100755 --- a/fw/wmi_unified.h +++ b/fw/wmi_unified.h @@ -537,6 +537,15 @@ typedef enum { */ WMI_PEER_TID_CONFIGURATIONS_CMDID, + /** Peer configuration for Channel Frequency Response (CFR) capture + * of type wmi_peer_cfr_capture_cmd. The CFR capture is communicated + * through HTT_T2H_MSG_TYPE_CFR_DUMP_COMPL_IND. + */ + WMI_PEER_CFR_CAPTURE_CMDID, + + /** WMI command related to AP channel width switching */ + WMI_PEER_CHAN_WIDTH_SWITCH_CMDID, + /* beacon/management specific commands */ /** transmit beacon by reference . used for transmitting beacon on low latency interface like pcie */ @@ -2338,6 +2347,9 @@ typedef struct { * where 2^n is the maximum number of BSSIDs */ A_UINT32 max_bssid_indicator; + + /* 2nd DWORD of HE MAC Capabilities */ + A_UINT32 he_cap_info_ext; } wmi_service_ready_ext_event_fixed_param; typedef enum { @@ -2923,6 +2935,16 @@ typedef struct { * where 2^n is the maximum number of BSSIDs */ A_UINT32 max_bssid_indicator; + + /** @brief ul_resp_config - Configures the 11ax uplink ofdma feature on STA. + * I.e. sending uplink response to a trigger frame sent by AP. + * @details + * 0 - fw default behavior, based on chipset + * 1 - UL_RESP is disabled. + * 2 - UL_RESP is enabled. + * other - reserved. + */ + A_UINT32 ul_resp_config; } wmi_resource_config; #define WMI_RSRC_CFG_FLAG_SET(word32, flag, value) \ @@ -5151,6 +5173,33 @@ typedef enum { * Non zero Value: Periodicity (seconds) */ WMI_PDEV_PARAM_ESP_INDICATION_PERIOD, /* 0xA7 */ + + /* + * Enable/Disable periodic peer CFR capture + * WMI_PEER_CFR_CAPTURE_ENABLE - Enable per peer periodic CFR capture + * WMI_PEER_CFR_CAPTURE_DISABLE - Disable per peer periodic CFR capture + */ + WMI_PDEV_PARAM_PER_PEER_PERIODIC_CFR_ENABLE, + + /* + * Set the base timer for the periodic CFR capture. By default this is 10ms. + * The period ('periodicity' param in wmi_peer_cfr_capture_cmd) of + * CFR measurment of other peers will be in multiples of this base timer. + * The unit is in milliseconds. + */ + WMI_PDEV_PARAM_PERIODIC_CFR_BASE_TIMER, + + /* + * Once the periodic capture is enabled using + * WMI_PDEV_PARAM_PER_PEER_PERIODIC_CFR_ENABLE, the timer starts running in + * the target. This parameter will ensure that the timer stops if there are + * no active peers in the capture list. Once the peers are added again to + * the capture list, the timer will not start again. The timer has to be + * started again using WMI_PDEV_PARAM_PER_PEER_PERIODIC_CFR_ENABLE. + * Value 1: Enable this feature + * Value 0: Disable this feature + */ + WMI_PDEV_PARAM_ENABLE_OPTIMIZED_PERIODIC_CFR_TIMER, } WMI_PDEV_PARAM; typedef struct { @@ -7280,55 +7329,55 @@ typedef struct { #define WMI_UNIFIED_VDEV_START_LDPC_RX_ENABLED (1<<3) /* BSS color 0-6 */ -#define WMI_HEOPS_COLOR_GET(he_ops) WMI_GET_BITS(he_ops, 0, 6) -#define WMI_HEOPS_COLOR_SET(he_ops, value) WMI_SET_BITS(he_ops, 0, 6, value) +#define WMI_HEOPS_COLOR_GET_D2(he_ops) WMI_GET_BITS(he_ops, 0, 6) +#define WMI_HEOPS_COLOR_SET_D2(he_ops, value) WMI_SET_BITS(he_ops, 0, 6, value) /* Default PE Duration subfield indicates the PE duration in units of 4 us */ -#define WMI_HEOPS_DEFPE_GET(he_ops) WMI_GET_BITS(he_ops, 6, 3) -#define WMI_HEOPS_DEFPE_SET(he_ops, value) WMI_SET_BITS(he_ops, 6, 3, value) +#define WMI_HEOPS_DEFPE_GET_D2(he_ops) WMI_GET_BITS(he_ops, 6, 3) +#define WMI_HEOPS_DEFPE_SET_D2(he_ops, value) WMI_SET_BITS(he_ops, 6, 3, value) /* TWT required */ -#define WMI_HEOPS_TWT_REQUIRED_GET(he_ops) WMI_GET_BITS(he_ops, 9, 1) -#define WMI_HEOPS_TWT_REQUIRED_SET(he_ops, value) WMI_SET_BITS(he_ops, 9, 1, value) +#define WMI_HEOPS_TWT_REQUIRED_GET_D2(he_ops) WMI_GET_BITS(he_ops, 9, 1) +#define WMI_HEOPS_TWT_REQUIRED_SET_D2(he_ops, value) WMI_SET_BITS(he_ops, 9, 1, value) /* DEPRECATED, use WMI_HEOPS_TWT_REQUIRED_GET instead */ -#define WMI_HEOPS_TWT_GET(he_ops) \ - WMI_HEOPS_TWT_REQUIRED_GET(he_ops) +#define WMI_HEOPS_TWT_GET_D2(he_ops) \ + WMI_HEOPS_TWT_REQUIRED_GET_D2(he_ops) /* DEPRECATED, use WMI_HEOPS_TWT_REQUIRED_SET instead */ -#define WMI_HEOPS_TWT_SET(he_ops, value) \ - WMI_HEOPS_TWT_REQUIRED_SET(he_ops, value) +#define WMI_HEOPS_TWT_SET_D2(he_ops, value) \ + WMI_HEOPS_TWT_REQUIRED_SET_D2(he_ops, value) /* RTS threshold in units of 32 us,0 - always use RTS 1023 - this is disabled */ -#define WMI_HEOPS_RTSTHLD_GET(he_ops) WMI_GET_BITS(he_ops, 10, 10) -#define WMI_HEOPS_RTSTHLD_SET(he_ops, value) WMI_SET_BITS(he_ops, 10, 10, value) +#define WMI_HEOPS_RTSTHLD_GET_D2(he_ops) WMI_GET_BITS(he_ops, 10, 10) +#define WMI_HEOPS_RTSTHLD_SET_D2(he_ops, value) WMI_SET_BITS(he_ops, 10, 10, value) /* Partial BSS Color field indicates whether BSS applies an AID assignment rule using partial BSS color bits */ -#define WMI_HEOPS_PARTBSSCOLOR_GET(he_ops) WMI_GET_BITS(he_ops, 20, 1) -#define WMI_HEOPS_PARTBSSCOLOR_SET(he_ops, value) WMI_SET_BITS(he_ops, 20, 1, value) +#define WMI_HEOPS_PARTBSSCOLOR_GET_D2(he_ops) WMI_GET_BITS(he_ops, 20, 1) +#define WMI_HEOPS_PARTBSSCOLOR_SET_D2(he_ops, value) WMI_SET_BITS(he_ops, 20, 1, value) /* MAX BSS supported by MultiBSS element */ -#define WMI_HEOPS_MAXBSSID_GET(he_ops) WMI_GET_BITS(he_ops, 21, 8) -#define WMI_HEOPS_MAXBSSID_SET(he_ops, value) WMI_SET_BITS(he_ops, 21, 8, value) +#define WMI_HEOPS_MAXBSSID_GET_D2(he_ops) WMI_GET_BITS(he_ops, 21, 8) +#define WMI_HEOPS_MAXBSSID_SET_D2(he_ops, value) WMI_SET_BITS(he_ops, 21, 8, value) /* Tx BSSID Indicator indicates whether HE AP corresponds to transmitted BSSID */ -#define WMI_HEOPS_TXBSSID_GET(he_ops) WMI_GET_BITS(he_ops, 29, 1) -#define WMI_HEOPS_TXBSSID_SET(he_ops, value) WMI_SET_BITS(he_ops, 29, 1, value) +#define WMI_HEOPS_TXBSSID_GET_D2(he_ops) WMI_GET_BITS(he_ops, 29, 1) +#define WMI_HEOPS_TXBSSID_SET_D2(he_ops, value) WMI_SET_BITS(he_ops, 29, 1, value) /* when set to 1 disables use of BSS color */ -#define WMI_HEOPS_BSSCOLORDISABLE_GET(he_ops) WMI_GET_BITS(he_ops, 30, 1) -#define WMI_HEOPS_BSSCOLORDISABLE_SET(he_ops, value) WMI_SET_BITS(he_ops, 30, 1, value) +#define WMI_HEOPS_BSSCOLORDISABLE_GET_D2(he_ops) WMI_GET_BITS(he_ops, 30, 1) +#define WMI_HEOPS_BSSCOLORDISABLE_SET_D2(he_ops, value) WMI_SET_BITS(he_ops, 30, 1, value) /**--- HEOPS_DUALBEACON: DO NOT USE - DEPRECATED ---*/ /* When set to 1 HE AP transmits beacons using two PHY formats, * one in non-HE format and other in an HE_EXT_SU PHY format */ -#define WMI_HEOPS_DUALBEACON_GET(he_ops) (0) -#define WMI_HEOPS_DUALBEACON_SET(he_ops, value) {;} +#define WMI_HEOPS_DUALBEACON_GET_D2(he_ops) (0) +#define WMI_HEOPS_DUALBEACON_SET_D2(he_ops, value) {;} #define WMI_MAX_HECAP_PHY_SIZE (3) /* Dual Band both 2.4 GHz and 5 GHz Supported */ -#define WMI_HECAP_PHY_DB_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 0, 1) -#define WMI_HECAP_PHY_DB_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 0, 1, value) +#define WMI_HECAP_PHY_DB_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 0, 1) +#define WMI_HECAP_PHY_DB_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 0, 1, value) /* * B0: Indicates STA support 40 MHz channel width in 2.4 GHz @@ -7342,8 +7391,8 @@ typedef struct { * MHz channel width in 5 GHz. Otherwise Reserved. * B6: Reserved */ -#define WMI_HECAP_PHY_CBW_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 1, 7) -#define WMI_HECAP_PHY_CBW_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 1, 7, value) +#define WMI_HECAP_PHY_CBW_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 1, 7) +#define WMI_HECAP_PHY_CBW_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 1, 7, value) /* * B0: Indicates STA supports reception of preamble puncturing in 80 MHz, @@ -7358,59 +7407,59 @@ typedef struct { * or 80+80 MHz, where in the primary 80 MHz of the preamble, the * primary 40 MHz is present */ -#define WMI_HECAP_PHY_PREAMBLEPUNCRX_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 8, 4) -#define WMI_HECAP_PHY_PREAMBLEPUNCRX_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 8, 4, value) +#define WMI_HECAP_PHY_PREAMBLEPUNCRX_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 8, 4) +#define WMI_HECAP_PHY_PREAMBLEPUNCRX_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 8, 4, value) /* Indicates transmitting STA is a Class A (1) or a Class B (0) device */ -#define WMI_HECAP_PHY_COD_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 12, 1) -#define WMI_HECAP_PHY_COD_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 12, 1, value) +#define WMI_HECAP_PHY_COD_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 12, 1) +#define WMI_HECAP_PHY_COD_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 12, 1, value) /* Indicates support of transmission and reception of LDPC encoded packets */ -#define WMI_HECAP_PHY_LDPC_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 13, 1) -#define WMI_HECAP_PHY_LDPC_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 13, 1, value) +#define WMI_HECAP_PHY_LDPC_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 13, 1) +#define WMI_HECAP_PHY_LDPC_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 13, 1, value) /* Below 2 macros are for maintaining backward compatability - Deprecated use WMI_HECAP_PHY_LDPC instead */ -#define WMI_HECAP_PHY_TXLDPC_GET(he_cap_phy) WMI_HECAP_PHY_LDPC_GET(he_cap_phy) -#define WMI_HECAP_PHY_TXLDPC_SET(he_cap_phy, value) WMI_HECAP_PHY_LDPC_SET(he_cap_phy, value) +#define WMI_HECAP_PHY_TXLDPC_GET_D2(he_cap_phy) WMI_HECAP_PHY_LDPC_GET_D2(he_cap_phy) +#define WMI_HECAP_PHY_TXLDPC_SET_D2(he_cap_phy, value) WMI_HECAP_PHY_LDPC_SET_D2(he_cap_phy, value) /* Below 2 macros are for maintaining backward compatability - Deprecated use WMI_HECAP_PHY_LDPC instead */ -#define WMI_HECAP_PHY_RXLDPC_GET(he_cap_phy) WMI_HECAP_PHY_LDPC_GET(he_cap_phy) -#define WMI_HECAP_PHY_RXLDPC_SET(he_cap_phy, value) WMI_HECAP_PHY_LDPC_SET(he_cap_phy, value) +#define WMI_HECAP_PHY_RXLDPC_GET_D2(he_cap_phy) WMI_HECAP_PHY_LDPC_GET_D2(he_cap_phy) +#define WMI_HECAP_PHY_RXLDPC_SET_D2(he_cap_phy, value) WMI_HECAP_PHY_LDPC_SET_D2(he_cap_phy, value) /* * B0: Indicates support of reception of 1x LTF and 0.8us guard interval duration for HE SU PPDUs. */ -#define WMI_HECAP_PHY_LTFGIFORHE_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 14, 1) -#define WMI_HECAP_PHY_LTFGIFORHE_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 14, 1, value) +#define WMI_HECAP_PHY_LTFGIFORHE_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 14, 1) +#define WMI_HECAP_PHY_LTFGIFORHE_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 14, 1, value) /* * When the Doppler Rx subfield is 1, indicates the maximum number of space- * time streams supported for reception when midamble is used in the Data field. */ -#define WMI_HECAP_PHY_MIDAMBLERXMAXNSTS_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 15, 2) -#define WMI_HECAP_PHY_MIDAMBLERXMAXNSTS_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 15, 2, value) +#define WMI_HECAP_PHY_MIDAMBLERXMAXNSTS_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 15, 2) +#define WMI_HECAP_PHY_MIDAMBLERXMAXNSTS_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 15, 2, value) /* * B0: For a transmitting STA acting as beamformee, it indicates support of * NDP reception using 4x LTF and 3.2 us guard interval duration */ -#define WMI_HECAP_PHY_LTFGIFORNDP_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 17, 1) -#define WMI_HECAP_PHY_LTFGIFORNDP_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 17, 1, value) +#define WMI_HECAP_PHY_LTFGIFORNDP_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 17, 1) +#define WMI_HECAP_PHY_LTFGIFORNDP_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 17, 1, value) /* indicates support for the transmission of HE PPDUs using STBC with one spatial stream for <= 80MHz Tx*/ -#define WMI_HECAP_PHY_TXSTBC_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 18, 1) -#define WMI_HECAP_PHY_TXSTBC_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 18, 1, value) +#define WMI_HECAP_PHY_TXSTBC_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 18, 1) +#define WMI_HECAP_PHY_TXSTBC_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 18, 1, value) /* indicates support for the reception of HE PPDUs using STBC with one spatial stream for <= 80MHz Tx*/ -#define WMI_HECAP_PHY_RXSTBC_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 19, 1) -#define WMI_HECAP_PHY_RXSTBC_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 19, 1, value) +#define WMI_HECAP_PHY_RXSTBC_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 19, 1) +#define WMI_HECAP_PHY_RXSTBC_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 19, 1, value) /* indicates transmitting STA supports transmitting HE PPDUs with Doppler procedure */ -#define WMI_HECAP_PHY_TXDOPPLER_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 20, 1) -#define WMI_HECAP_PHY_TXDOPPLER_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 20, 1, value) +#define WMI_HECAP_PHY_TXDOPPLER_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 20, 1) +#define WMI_HECAP_PHY_TXDOPPLER_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 20, 1, value) /* indicates transmitting STA supports receiving HE PPDUs with Doppler procedure */ -#define WMI_HECAP_PHY_RXDOPPLER_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 21, 1) -#define WMI_HECAP_PHY_RXDOPPLER_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 21, 1, value) +#define WMI_HECAP_PHY_RXDOPPLER_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 21, 1) +#define WMI_HECAP_PHY_RXDOPPLER_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 21, 1, value) /* * If the transmitting STA is an AP: @@ -7420,8 +7469,8 @@ typedef struct { * indicates STA supports of transmission of full bandwidth UL MU-MIMO * transmission. */ -#define WMI_HECAP_PHY_UL_MU_MIMO_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 22, 1) -#define WMI_HECAP_PHY_UL_MU_MIMO_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 22, 1, value) +#define WMI_HECAP_PHY_UL_MU_MIMO_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 22, 1) +#define WMI_HECAP_PHY_UL_MU_MIMO_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 22, 1, value) /* * If the transmitting STA is an AP: @@ -7431,8 +7480,8 @@ typedef struct { * indicates STA supports of transmission of UL MU-MIMO transmission on an * RU in an HE MU PPDU where the RU does not span the entire PPDU bandwidth. */ -#define WMI_HECAP_PHY_ULMUMIMOOFDMA_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 23, 1) -#define WMI_HECAP_PHY_ULMUMIMOOFDMA_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 23, 1, value) +#define WMI_HECAP_PHY_ULMUMIMOOFDMA_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 23, 1) +#define WMI_HECAP_PHY_ULMUMIMOOFDMA_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 23, 1, value) /* Tx DCM * B0:B1 @@ -7444,8 +7493,8 @@ typedef struct { * 0: 1 spatial stream * 1: 2 spatial streams */ -#define WMI_HECAP_PHY_DCMTX_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 24, 3) -#define WMI_HECAP_PHY_DCMTX_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 24, 3, value) +#define WMI_HECAP_PHY_DCMTX_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 24, 3) +#define WMI_HECAP_PHY_DCMTX_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 24, 3, value) /* Rx DCM * B0:B1 @@ -7457,36 +7506,36 @@ typedef struct { * 0: 1 spatial stream * 1: 2 spatial streams */ -#define WMI_HECAP_PHY_DCMRX_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 27, 3) -#define WMI_HECAP_PHY_DCMRX_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 27, 3, value) +#define WMI_HECAP_PHY_DCMRX_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 27, 3) +#define WMI_HECAP_PHY_DCMRX_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 27, 3, value) /* * Indicates that the STA supports the reception of an HE MU PPDU payload * over full bandwidth and partial bandwidth (106-tone RU within 20 MHz). */ -#define WMI_HECAP_PHY_ULHEMU_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 30, 1) -#define WMI_HECAP_PHY_ULHEMU_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 30, 1, value) +#define WMI_HECAP_PHY_ULHEMU_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 30, 1) +#define WMI_HECAP_PHY_ULHEMU_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 30, 1, value) /* Indicates support for operation as an SU beamformer */ -#define WMI_HECAP_PHY_SUBFMR_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 31, 1) -#define WMI_HECAP_PHY_SUBFMR_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 31, 1, value) +#define WMI_HECAP_PHY_SUBFMR_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 31, 1) +#define WMI_HECAP_PHY_SUBFMR_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 31, 1, value) /* Indicates support for operation as an SU beamformee */ -#define WMI_HECAP_PHY_SUBFME_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 0, 1) -#define WMI_HECAP_PHY_SUBFME_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 0, 1, value) +#define WMI_HECAP_PHY_SUBFME_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 0, 1) +#define WMI_HECAP_PHY_SUBFME_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 0, 1, value) /* Indicates support for operation as an MU Beamformer */ -#define WMI_HECAP_PHY_MUBFMR_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 1, 1) -#define WMI_HECAP_PHY_MUBFMR_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 1, 1, value) +#define WMI_HECAP_PHY_MUBFMR_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 1, 1) +#define WMI_HECAP_PHY_MUBFMR_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 1, 1, value) /* * Num STS -1 for <= 80MHz (min val 3) * The maximum number of space-time streams minus 1 that the STA can * receive in an HE NDP */ -#define WMI_HECAP_PHY_BFMESTSLT80MHZ_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 2, 3) -#define WMI_HECAP_PHY_BFMESTSLT80MHZ_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 2, 3, value) +#define WMI_HECAP_PHY_BFMESTSLT80MHZ_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 2, 3) +#define WMI_HECAP_PHY_BFMESTSLT80MHZ_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 2, 3, value) /* @@ -7494,8 +7543,8 @@ typedef struct { * The maximum number of space-time streams minus 1 that the STA can * receive in an HE NDP */ -#define WMI_HECAP_PHY_BFMESTSGT80MHZ_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 5, 3) -#define WMI_HECAP_PHY_BFMESTSGT80MHZ_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 5, 3, value) +#define WMI_HECAP_PHY_BFMESTSGT80MHZ_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 5, 3) +#define WMI_HECAP_PHY_BFMESTSGT80MHZ_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 5, 3, value) /* * Number Of Sounding Dimensions For <= 80 MHz @@ -7503,8 +7552,8 @@ typedef struct { * TXVECTOR parameter NUM_STS minus 1. * Otherwise, reserved. */ -#define WMI_HECAP_PHY_NUMSOUNDLT80MHZ_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 8, 3) -#define WMI_HECAP_PHY_NUMSOUNDLT80MHZ_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 8, 3, value) +#define WMI_HECAP_PHY_NUMSOUNDLT80MHZ_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 8, 3) +#define WMI_HECAP_PHY_NUMSOUNDLT80MHZ_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 8, 3, value) /* * Number Of Sounding Dimensions For > 80 MHz @@ -7512,40 +7561,40 @@ typedef struct { * TXVECTOR parameter NUM_STS minus 1. * Otherwise, reserved. */ -#define WMI_HECAP_PHY_NUMSOUNDGT80MHZ_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 11, 3) -#define WMI_HECAP_PHY_NUMSOUNDGT80MHZ_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 11, 3, value) +#define WMI_HECAP_PHY_NUMSOUNDGT80MHZ_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 11, 3) +#define WMI_HECAP_PHY_NUMSOUNDGT80MHZ_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 11, 3, value) /* * Indicates if the HE beamformee is capable of feedback with tone * grouping of 16 in the HE Compressed Beamforming Report field for * a SU-type feedback. */ -#define WMI_HECAP_PHY_NG16SUFEEDBACKLT80_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 14, 1) -#define WMI_HECAP_PHY_NG16SUFEEDBACKLT80_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 14, 1, value) +#define WMI_HECAP_PHY_NG16SUFEEDBACKLT80_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 14, 1) +#define WMI_HECAP_PHY_NG16SUFEEDBACKLT80_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 14, 1, value) /* * Indicates if the HE beamformee is capable of feedback with tone * grouping of 16 in the HE Compressed Beamforming Report field for * a MU-type feedback. */ -#define WMI_HECAP_PHY_NG16MUFEEDBACKGT80_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 15, 1) -#define WMI_HECAP_PHY_NG16MUFEEDBACKGT80_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 15, 1, value) +#define WMI_HECAP_PHY_NG16MUFEEDBACKGT80_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 15, 1) +#define WMI_HECAP_PHY_NG16MUFEEDBACKGT80_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 15, 1, value) /* * Indicates if HE beamformee is capable of feedback with codebook * size {4, 2} in the HECompressed Beamforming Report field for * a SU-type feedback. */ -#define WMI_HECAP_PHY_CODBK42SU_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 16, 1) -#define WMI_HECAP_PHY_CODBK42SU_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 16, 1, value) +#define WMI_HECAP_PHY_CODBK42SU_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 16, 1) +#define WMI_HECAP_PHY_CODBK42SU_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 16, 1, value) /* * Indicates if HE beamformee is capable of feedback with codebook * size {7, 5} in the HE Compressed Beamforming Report field for * a MU-type feedback. */ -#define WMI_HECAP_PHY_CODBK75MU_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 17, 1) -#define WMI_HECAP_PHY_CODBK75MU_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 17, 1, value) +#define WMI_HECAP_PHY_CODBK75MU_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 17, 1) +#define WMI_HECAP_PHY_CODBK75MU_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 17, 1, value) /* * Beamforming Feedback With Trigger Frame @@ -7558,73 +7607,73 @@ typedef struct { * B1: indicates support of transmission of MU-Type partial(1) bandwidth feedback * B2: indicates support of transmission of CQI-Onlypartial (1)and full bandwidth feedback */ -#define WMI_HECAP_PHY_BFFEEDBACKTRIG_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 18, 3) -#define WMI_HECAP_PHY_BFFEEDBACKTRIG_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 18, 3, value) +#define WMI_HECAP_PHY_BFFEEDBACKTRIG_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 18, 3) +#define WMI_HECAP_PHY_BFFEEDBACKTRIG_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 18, 3, value) /* Indicates the support of transmission and reception of an HE extended range SU PPDU payload transmitted * over the right 106-tone RU or partial BW ER */ -#define WMI_HECAP_PHY_HEERSU_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 21, 1) -#define WMI_HECAP_PHY_HEERSU_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 21, 1, value) +#define WMI_HECAP_PHY_HEERSU_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 21, 1) +#define WMI_HECAP_PHY_HEERSU_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 21, 1, value) /* Indicates that the non-AP STA supports reception of a DL MU-MIMO transmission on an RU in an HE MU PPDU * where the RU does not span the entire PPDU bandwidth. */ -#define WMI_HECAP_PHY_DLMUMIMOPARTIALBW_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 22, 1) -#define WMI_HECAP_PHY_DLMUMIMOPARTIALBW_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 22, 1, value) +#define WMI_HECAP_PHY_DLMUMIMOPARTIALBW_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 22, 1) +#define WMI_HECAP_PHY_DLMUMIMOPARTIALBW_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 22, 1, value) /* Indicates whether or not the PPE Threshold field is present */ -#define WMI_HECAP_PHY_PETHRESPRESENT_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 23, 1) -#define WMI_HECAP_PHY_PETHRESPRESENT_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 23, 1, value) +#define WMI_HECAP_PHY_PETHRESPRESENT_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 23, 1) +#define WMI_HECAP_PHY_PETHRESPRESENT_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 23, 1, value) /* Indicates that the STA supports SRP-based SR operation */ -#define WMI_HECAP_PHY_SRPSPRESENT_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 24, 1) -#define WMI_HECAP_PHY_SRPPRESENT_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 24, 1, value) +#define WMI_HECAP_PHY_SRPSPRESENT_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 24, 1) +#define WMI_HECAP_PHY_SRPPRESENT_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 24, 1, value) /* Indicates that the STA supports a power boost factor ar for the r-th RU in the range [0.5, 2] */ -#define WMI_HECAP_PHY_PWRBOOSTAR_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 25, 1) -#define WMI_HECAP_PHY_PWRBOOSTAR_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 25, 1, value) +#define WMI_HECAP_PHY_PWRBOOSTAR_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 25, 1) +#define WMI_HECAP_PHY_PWRBOOSTAR_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 25, 1, value) /* Indicates support for the reception of 4x LTF and 0.8us guard interval duration for HE SU PPDUs. */ -#define WMI_HECAP_PHY_4XLTFAND800NSECSGI_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 26, 1) -#define WMI_HECAP_PHY_4XLTFAND800NSECSGI_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 26, 1, value) +#define WMI_HECAP_PHY_4XLTFAND800NSECSGI_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 26, 1) +#define WMI_HECAP_PHY_4XLTFAND800NSECSGI_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 26, 1, value) /* For a transmitting STA acting as a beamformee, it indicates the maximum Nc for beamforming sounding * feedback supported If SU beamformee capable, then set to the maximum Nc for beamforming sounding feedback * minus 1. Otherwise, reserved. */ -#define WMI_HECAP_PHY_MAXNC_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 27, 3) -#define WMI_HECAP_PHY_MAXNC_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 27, 3, value) +#define WMI_HECAP_PHY_MAXNC_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 27, 3) +#define WMI_HECAP_PHY_MAXNC_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 27, 3, value) /* Indicates support for the transmission of an HE PPDU that has a bandwidth greater than 80 MHz and is using * STBC with one spatial stream */ -#define WMI_HECAP_PHY_STBCTXGT80_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 30, 1) -#define WMI_HECAP_PHY_STBCTXGT80_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 30, 1, value) +#define WMI_HECAP_PHY_STBCTXGT80_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 30, 1) +#define WMI_HECAP_PHY_STBCTXGT80_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 30, 1, value) /* Indicates support for the reception of an HE PPDU that has a bandwidth greater than 80 MHz and is using * STBC with one spatial stream */ -#define WMI_HECAP_PHY_STBCRXGT80_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 31, 1) -#define WMI_HECAP_PHY_STBCRXGT80_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 31, 1, value) +#define WMI_HECAP_PHY_STBCRXGT80_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 31, 1) +#define WMI_HECAP_PHY_STBCRXGT80_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 31, 1, value) /* Indicates support for the reception of an HE ER SU PPDU with 4x LTF and 0.8 us guard interval duration */ -#define WMI_HECAP_PHY_ERSU4X800NSECGI_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[2], 0, 1) -#define WMI_HECAP_PHY_ERSU4X800NSECGI_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[2], 0, 1, value) +#define WMI_HECAP_PHY_ERSU4X800NSECGI_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[2], 0, 1) +#define WMI_HECAP_PHY_ERSU4X800NSECGI_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[2], 0, 1, value) /* * Indicates support of 26-, 52-, and 106-tone mapping for a 20 MHz operating non-AP HE STA that is the * receiver of a 40 MHz HE MU PPDU in 2.4 GHz band, or the transmitter of a 40 MHz HE TB PPDU in 2.4GHz band. */ -#define WMI_HECAP_PHY_HEPPDU20IN40MHZ2G_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[2], 1, 1) -#define WMI_HECAP_PHY_HEPPDU20IN40MHZ2G_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[2], 1, 1, value) +#define WMI_HECAP_PHY_HEPPDU20IN40MHZ2G_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[2], 1, 1) +#define WMI_HECAP_PHY_HEPPDU20IN40MHZ2G_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[2], 1, 1, value) /* * Indicates support of 26-, 52-, and 106-tone mapping for a 20 MHz operating non-AP HE STA that is the * receiver of a 80+80 MHz or a 160 MHz HE MU PPDU, or the transmitter of a 80+80 MHz or 160 MHz HE TB PPDU. */ -#define WMI_HECAP_PHY_HEPPDU20IN160OR80P80MHZ_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[2], 2, 1) -#define WMI_HECAP_PHY_HEPPDU20IN160OR80P80MHZ_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[2], 2, 1, value) +#define WMI_HECAP_PHY_HEPPDU20IN160OR80P80MHZ_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[2], 2, 1) +#define WMI_HECAP_PHY_HEPPDU20IN160OR80P80MHZ_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[2], 2, 1, value) /* * Indicates supports of 160 MHz OFDMA for a non-AP HE STA that sets bit B1 of Channel Width Set to 1, and @@ -7632,32 +7681,32 @@ typedef struct { * bit is applicable while receiving a 80+80 MHz or a 160 MHz HE MU PPDU, or transmitting a 80+80 MHz or a * 160 MHz HE TB PPDU. */ -#define WMI_HECAP_PHY_HEPPDU80IN160OR80P80MHZ_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[2], 3, 1) -#define WMI_HECAP_PHY_HEPPDU80IN160OR80P80MHZ_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[2], 3, 1, value) +#define WMI_HECAP_PHY_HEPPDU80IN160OR80P80MHZ_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[2], 3, 1) +#define WMI_HECAP_PHY_HEPPDU80IN160OR80P80MHZ_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[2], 3, 1, value) /* Indicates support for the reception of an HE ER SU PPDU with 1x LTF and 0.8 us guard interval duration */ -#define WMI_HECAP_PHY_ERSU1X800NSECGI_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[2], 4, 1) -#define WMI_HECAP_PHY_ERSU1X800NSECGI_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[2], 4, 1, value) +#define WMI_HECAP_PHY_ERSU1X800NSECGI_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[2], 4, 1) +#define WMI_HECAP_PHY_ERSU1X800NSECGI_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[2], 4, 1, value) /* * When the Doppler Rx subfield is 1, indicates support for receiving midambles with 2x HE-LTF, 1x HE-LTF * in HE SU PPDU if the HE SU PPDU With 1x HE-LTF And 0.8 s GI subfield is set to 1, and 1x HE-LTF in * HE ER SU PPDU if the HE ER SU PPDU With 1x HELTF And 0.8 s GI subfield is set to 1. */ -#define WMI_HECAP_PHY_MIDAMBLERX2XAND1XHELTF_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[2], 5, 1) -#define WMI_HECAP_PHY_MIDAMBLERX2XAND1XHELTF_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[2], 5, 1, value) +#define WMI_HECAP_PHY_MIDAMBLERX2XAND1XHELTF_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[2], 5, 1) +#define WMI_HECAP_PHY_MIDAMBLERX2XAND1XHELTF_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[2], 5, 1, value) /*HTC + HE Support Set to 1 if STA supports reception of HE Variant HT control Field*/ -#define WMI_HECAP_MAC_HECTRL_GET(he_cap) WMI_GET_BITS(he_cap, 0, 1) -#define WMI_HECAP_MAC_HECTRL_SET(he_cap, value) WMI_SET_BITS(he_cap, 0, 1, value) +#define WMI_HECAP_MAC_HECTRL_GET_D2(he_cap) WMI_GET_BITS(he_cap, 0, 1) +#define WMI_HECAP_MAC_HECTRL_SET_D2(he_cap, value) WMI_SET_BITS(he_cap, 0, 1, value) /* set to 1 to for TWT Requestor support*/ -#define WMI_HECAP_MAC_TWTREQ_GET(he_cap) WMI_GET_BITS(he_cap, 1, 1) -#define WMI_HECAP_MAC_TWTREQ_SET(he_cap, value) WMI_SET_BITS(he_cap, 1, 1, value) +#define WMI_HECAP_MAC_TWTREQ_GET_D2(he_cap) WMI_GET_BITS(he_cap, 1, 1) +#define WMI_HECAP_MAC_TWTREQ_SET_D2(he_cap, value) WMI_SET_BITS(he_cap, 1, 1, value) /* set to 1 to for TWT Responder support*/ -#define WMI_HECAP_MAC_TWTRSP_GET(he_cap) WMI_GET_BITS(he_cap, 2, 1) -#define WMI_HECAP_MAC_TWTRSP_SET(he_cap, value) WMI_SET_BITS(he_cap, 2, 1, value) +#define WMI_HECAP_MAC_TWTRSP_GET_D2(he_cap) WMI_GET_BITS(he_cap, 2, 1) +#define WMI_HECAP_MAC_TWTRSP_SET_D2(he_cap, value) WMI_SET_BITS(he_cap, 2, 1, value) /* Level of frag support Set to 0 for no support for dynamic fragmentation. @@ -7668,78 +7717,78 @@ typedef struct { dynamic fragments for each MSDU within an AMPDU or multi-TID AMPDU and up to one dynamic fragment for each MMPDU in a multi-TID A-MPDU that is not a Single MPDU */ -#define WMI_HECAP_MAC_HEFRAG_GET(he_cap) WMI_GET_BITS(he_cap, 3, 2) -#define WMI_HECAP_MAC_HEFRAG_SET(he_cap, value) WMI_SET_BITS(he_cap, 3, 2, value) +#define WMI_HECAP_MAC_HEFRAG_GET_D2(he_cap) WMI_GET_BITS(he_cap, 3, 2) +#define WMI_HECAP_MAC_HEFRAG_SET_D2(he_cap, value) WMI_SET_BITS(he_cap, 3, 2, value) /* The maximum number of fragmented MSDUs, Nmax,defined by this field is Nmax = 2 Maximum Number Of FMPDUs*/ -#define WMI_HECAP_MAC_MAXFRAGMSDU_GET(he_cap) WMI_GET_BITS(he_cap, 5, 3) -#define WMI_HECAP_MAC_MAXFRAGMSDU_SET(he_cap, value) WMI_SET_BITS(he_cap, 5, 3, value) +#define WMI_HECAP_MAC_MAXFRAGMSDU_GET_D2(he_cap) WMI_GET_BITS(he_cap, 5, 3) +#define WMI_HECAP_MAC_MAXFRAGMSDU_SET_D2(he_cap, value) WMI_SET_BITS(he_cap, 5, 3, value) /* 0 = no restriction on the minimum payload , 1 = 128 octets min, 2 = 256 octets min, 3 = 512 octets min */ -#define WMI_HECAP_MAC_MINFRAGSZ_GET(he_cap) WMI_GET_BITS(he_cap, 8, 2) -#define WMI_HECAP_MAC_MINFRAGSZ_SET(he_cap, value) WMI_SET_BITS(he_cap, 8, 2, value) +#define WMI_HECAP_MAC_MINFRAGSZ_GET_D2(he_cap) WMI_GET_BITS(he_cap, 8, 2) +#define WMI_HECAP_MAC_MINFRAGSZ_SET_D2(he_cap, value) WMI_SET_BITS(he_cap, 8, 2, value) /*0 = no additional processing time, 1 = 8us,2 = 16us */ -#define WMI_HECAP_MAC_TRIGPADDUR_GET(he_cap) WMI_GET_BITS(he_cap, 10, 2) -#define WMI_HECAP_MAC_TRIGPADDUR_SET(he_cap, value) WMI_SET_BITS(he_cap, 10, 2, value) +#define WMI_HECAP_MAC_TRIGPADDUR_GET_D2(he_cap) WMI_GET_BITS(he_cap, 10, 2) +#define WMI_HECAP_MAC_TRIGPADDUR_SET_D2(he_cap, value) WMI_SET_BITS(he_cap, 10, 2, value) /*number of TIDs minus 1 of QoS Data frames that HE STA can aggregate in multi-TID AMPDU*/ -#define WMI_HECAP_MAC_MTID_GET(he_cap) WMI_GET_BITS(he_cap, 12, 3) -#define WMI_HECAP_MAC_MTID_SET(he_cap, value) WMI_SET_BITS(he_cap, 12, 3, value) +#define WMI_HECAP_MAC_MTID_GET_D2(he_cap) WMI_GET_BITS(he_cap, 12, 3) +#define WMI_HECAP_MAC_MTID_SET_D2(he_cap, value) WMI_SET_BITS(he_cap, 12, 3, value) /* * Indicates support by a STA to receive an ack-enabled A-MPDU in which an A-MSDU is carried in * a QoS Data frame for which no block ack agreement exists. */ -#define WMI_HECAP_MAC_AMSDUINAMPDU_GET(he_cap) WMI_GET_BITS(he_cap, 15, 1) -#define WMI_HECAP_MAC_AMSDUINAMPDU_SET(he_cap, value) WMI_SET_BITS(he_cap, 15, 1, value) +#define WMI_HECAP_MAC_AMSDUINAMPDU_GET_D2(he_cap) WMI_GET_BITS(he_cap, 15, 1) +#define WMI_HECAP_MAC_AMSDUINAMPDU_SET_D2(he_cap, value) WMI_SET_BITS(he_cap, 15, 1, value) /*--- HECAP_MAC_HELKAD: DO NOT USE - DEPRECATED ---*/ /*0=No Feedback,2=Unsolicited,3=Both*/ -#define WMI_HECAP_MAC_HELKAD_GET(he_cap) (0) -#define WMI_HECAP_MAC_HELKAD_SET(he_cap, value) {;} +#define WMI_HECAP_MAC_HELKAD_GET_D2(he_cap) (0) +#define WMI_HECAP_MAC_HELKAD_SET_D2(he_cap, value) {;} /* bit 16 reserved. */ /*Set to 1 for reception of AllAck support*/ -#define WMI_HECAP_MAC_AACK_GET(he_cap) WMI_GET_BITS(he_cap, 17, 1) -#define WMI_HECAP_MAC_AACK_SET(he_cap, value) WMI_SET_BITS(he_cap, 17, 1, value) +#define WMI_HECAP_MAC_AACK_GET_D2(he_cap) WMI_GET_BITS(he_cap, 17, 1) +#define WMI_HECAP_MAC_AACK_SET_D2(he_cap, value) WMI_SET_BITS(he_cap, 17, 1, value) /*Set to 1 if the STA supports reception of the UL MU Response Scheduling A-Control field*/ -#define WMI_HECAP_MAC_ULMURSP_GET(he_cap) WMI_GET_BITS(he_cap, 18, 1) -#define WMI_HECAP_MAC_ULMURSP_SET(he_cap, value) WMI_SET_BITS(he_cap, 18, 1, value) +#define WMI_HECAP_MAC_ULMURSP_GET_D2(he_cap) WMI_GET_BITS(he_cap, 18, 1) +#define WMI_HECAP_MAC_ULMURSP_SET_D2(he_cap, value) WMI_SET_BITS(he_cap, 18, 1, value) /*Set to 1 if the STA supports the BSR A-Control field functionality.*/ -#define WMI_HECAP_MAC_BSR_GET(he_cap) WMI_GET_BITS(he_cap, 19, 1) -#define WMI_HECAP_MAC_BSR_SET(he_cap, value) WMI_SET_BITS(he_cap, 19, 1, value) +#define WMI_HECAP_MAC_BSR_GET_D2(he_cap) WMI_GET_BITS(he_cap, 19, 1) +#define WMI_HECAP_MAC_BSR_SET_D2(he_cap, value) WMI_SET_BITS(he_cap, 19, 1, value) /*Set to 1 when the STA supports broadcast TWT functionality.*/ -#define WMI_HECAP_MAC_BCSTTWT_GET(he_cap) WMI_GET_BITS(he_cap, 20, 1) -#define WMI_HECAP_MAC_BCSTTWT_SET(he_cap, value) WMI_SET_BITS(he_cap, 20, 1, value) +#define WMI_HECAP_MAC_BCSTTWT_GET_D2(he_cap) WMI_GET_BITS(he_cap, 20, 1) +#define WMI_HECAP_MAC_BCSTTWT_SET_D2(he_cap, value) WMI_SET_BITS(he_cap, 20, 1, value) /*Set to 1 if STA supports rx of Multi-STA BA that has 32-bit Block Ack Bitmap*/ -#define WMI_HECAP_MAC_32BITBA_GET(he_cap) WMI_GET_BITS(he_cap, 21, 1) -#define WMI_HECAP_MAC_32BITBA_SET(he_cap, value) WMI_SET_BITS(he_cap, 21, 1, value) +#define WMI_HECAP_MAC_32BITBA_GET_D2(he_cap) WMI_GET_BITS(he_cap, 21, 1) +#define WMI_HECAP_MAC_32BITBA_SET_D2(he_cap, value) WMI_SET_BITS(he_cap, 21, 1, value) /*Set to 1 if the STA supports MU cascading operation*/ -#define WMI_HECAP_MAC_MUCASCADE_GET(he_cap) WMI_GET_BITS(he_cap, 22, 1) -#define WMI_HECAP_MAC_MUCASCADE_SET(he_cap, value) WMI_SET_BITS(he_cap, 22, 1, value) +#define WMI_HECAP_MAC_MUCASCADE_GET_D2(he_cap) WMI_GET_BITS(he_cap, 22, 1) +#define WMI_HECAP_MAC_MUCASCADE_SET_D2(he_cap, value) WMI_SET_BITS(he_cap, 22, 1, value) /*Set to 1 when the STA supports reception of this multi-TID A-MPDU format*/ -#define WMI_HECAP_MAC_ACKMTIDAMPDU_GET(he_cap) WMI_GET_BITS(he_cap, 23, 1) -#define WMI_HECAP_MAC_ACKMTIDAMPDU_SET(he_cap, value) WMI_SET_BITS(he_cap, 23, 1, value) +#define WMI_HECAP_MAC_ACKMTIDAMPDU_GET_D2(he_cap) WMI_GET_BITS(he_cap, 23, 1) +#define WMI_HECAP_MAC_ACKMTIDAMPDU_SET_D2(he_cap, value) WMI_SET_BITS(he_cap, 23, 1, value) /*Set to 1 when the STA supports its reception*/ -#define WMI_HECAP_MAC_GROUPMSTABA_GET(he_cap) WMI_GET_BITS(he_cap, 24, 1) -#define WMI_HECAP_MAC_GROUPMSTABA_SET(he_cap, value) WMI_SET_BITS(he_cap, 24, 1, value) +#define WMI_HECAP_MAC_GROUPMSTABA_GET_D2(he_cap) WMI_GET_BITS(he_cap, 24, 1) +#define WMI_HECAP_MAC_GROUPMSTABA_SET_D2(he_cap, value) WMI_SET_BITS(he_cap, 24, 1, value) /*Set to 1 if the STA supports reception of the OMI A-Control field*/ -#define WMI_HECAP_MAC_OMI_GET(he_cap) WMI_GET_BITS(he_cap, 25, 1) -#define WMI_HECAP_MAC_OMI_SET(he_cap, value) WMI_SET_BITS(he_cap, 25, 1, value) +#define WMI_HECAP_MAC_OMI_GET_D2(he_cap) WMI_GET_BITS(he_cap, 25, 1) +#define WMI_HECAP_MAC_OMI_SET_D2(he_cap, value) WMI_SET_BITS(he_cap, 25, 1, value) /*1 if OFDMA Random Access Supported*/ -#define WMI_HECAP_MAC_OFDMARA_GET(he_cap) WMI_GET_BITS(he_cap, 26, 1) -#define WMI_HECAP_MAC_OFDMARA_SET(he_cap, value) WMI_SET_BITS(he_cap, 26, 1, value) +#define WMI_HECAP_MAC_OFDMARA_GET_D2(he_cap) WMI_GET_BITS(he_cap, 26, 1) +#define WMI_HECAP_MAC_OFDMARA_SET_D2(he_cap, value) WMI_SET_BITS(he_cap, 26, 1, value) /* Maximum AMPDU Length Exponent. * If the HE STA includes a VHT Capabilities element, the Maximum A-MPDU Length Exponent subfield in @@ -7747,130 +7796,130 @@ typedef struct { * Capabilities element indicate the maximum length of A-MPDU that the STA can Receive where EOF * padding is not included in this limit. */ -#define WMI_HECAP_MAC_MAXAMPDULEN_EXP_GET(he_cap) WMI_GET_BITS(he_cap, 27, 2) -#define WMI_HECAP_MAC_MAXAMPDULEN_EXP_SET(he_cap, value) WMI_SET_BITS(he_cap, 27, 2, value) +#define WMI_HECAP_MAC_MAXAMPDULEN_EXP_GET_D2(he_cap) WMI_GET_BITS(he_cap, 27, 2) +#define WMI_HECAP_MAC_MAXAMPDULEN_EXP_SET_D2(he_cap, value) WMI_SET_BITS(he_cap, 27, 2, value) /*A-MSDU Fragmentation Support*/ -#define WMI_HECAP_MAC_AMSDUFRAG_GET(he_cap) WMI_GET_BITS(he_cap, 29, 1) -#define WMI_HECAP_MAC_AMSDUFRAG_SET(he_cap, value) WMI_SET_BITS(he_cap, 29, 1, value) +#define WMI_HECAP_MAC_AMSDUFRAG_GET_D2(he_cap) WMI_GET_BITS(he_cap, 29, 1) +#define WMI_HECAP_MAC_AMSDUFRAG_SET_D2(he_cap, value) WMI_SET_BITS(he_cap, 29, 1, value) /*Flexible TWT Schedule Support*/ -#define WMI_HECAP_MAC_FLEXTWT_GET(he_cap) WMI_GET_BITS(he_cap, 30, 1) -#define WMI_HECAP_MAC_FLEXTWT_SET(he_cap, value) WMI_SET_BITS(he_cap, 30, 1, value) +#define WMI_HECAP_MAC_FLEXTWT_GET_D2(he_cap) WMI_GET_BITS(he_cap, 30, 1) +#define WMI_HECAP_MAC_FLEXTWT_SET_D2(he_cap, value) WMI_SET_BITS(he_cap, 30, 1, value) /*Rx Control Frame to MultiBSS*/ -#define WMI_HECAP_MAC_MBSS_GET(he_cap) WMI_GET_BITS(he_cap, 31, 1) -#define WMI_HECAP_MAC_MBSS_SET(he_cap, value) WMI_SET_BITS(he_cap, 31, 1, value) +#define WMI_HECAP_MAC_MBSS_GET_D2(he_cap) WMI_GET_BITS(he_cap, 31, 1) +#define WMI_HECAP_MAC_MBSS_SET_D2(he_cap, value) WMI_SET_BITS(he_cap, 31, 1, value) /* BSRP A-MPDU Aggregation * maintaining compatability since we dont support this now so not wasting memory */ -#define WMI_HECAP_MAC_BSRPAMPDU_GET(he_cap) (0) -#define WMI_HECAP_MAC_BSRPAMPDU_SET(he_cap, value) {;} +#define WMI_HECAP_MAC_BSRPAMPDU_GET_D2(he_cap) (0) +#define WMI_HECAP_MAC_BSRPAMPDU_SET_D2(he_cap, value) {;} /* Quiet Time Period (QTP) operation * maintaining compatability since we dont support this now so not wasting memory */ -#define WMI_HECAP_MAC_QTP_GET(he_cap) (0) -#define WMI_HECAP_MAC_QTP_SET(he_cap, value) {;} +#define WMI_HECAP_MAC_QTP_GET_D2(he_cap) (0) +#define WMI_HECAP_MAC_QTP_SET_D2(he_cap, value) {;} /* support by an AP for receiving an (A-)MPDU that contains a BQR in the * A-Control subfield and support by a non-AP STA for generating an (A-)MPDU * that contains a BQR in the A-Control subfield * maintaining compatability since we dont support this now so not wasting memory */ -#define WMI_HECAP_MAC_ABQR_GET(he_cap) (0) -#define WMI_HECAP_MAC_ABQR_SET(he_cap, value) {;} +#define WMI_HECAP_MAC_ABQR_GET_D2(he_cap) (0) +#define WMI_HECAP_MAC_ABQR_SET_D2(he_cap, value) {;} /*Indicates support by the STA for the role of SR Responder.*/ -#define WMI_HECAP_MAC_SRRESP_GET(he_cap) (0) -#define WMI_HECAP_MAC_SRRESP_SET(he_cap, value) {;} +#define WMI_HECAP_MAC_SRRESP_GET_D2(he_cap) (0) +#define WMI_HECAP_MAC_SRRESP_SET_D2(he_cap, value) {;} /* Indicates support for an AP to encode OPS information to TIM element of the FILS Discovery * frames or TIM frames as described in AP operation for opportunistic power save. * Indicates support for a non-AP STA to receive the opportunistic power save encoded TIM elements */ -#define WMI_HECAP_MAC_OPS_GET(he_cap) (0) -#define WMI_HECAP_MAC_OPS_SET(he_cap, value) {;} +#define WMI_HECAP_MAC_OPS_GET_D2(he_cap) (0) +#define WMI_HECAP_MAC_OPS_SET_D2(he_cap, value) {;} /* Indicates support for a non-AP STA to follow the NDP feedback report procedure and respond to * the NDP Feedback Report Poll Trigger frame. */ -#define WMI_HECAP_MAC_NDPFDBKRPT_GET(he_cap) (0) -#define WMI_HECAP_MAC_NDPFDBKRPT_SET(he_cap, value) {;} +#define WMI_HECAP_MAC_NDPFDBKRPT_GET_D2(he_cap) (0) +#define WMI_HECAP_MAC_NDPFDBKRPT_SET_D2(he_cap, value) {;} /* BELOW MACROS ARE DEPRECATED Also we are not defining bits for capabilities * beyond bit 31 we donot support as it adds additional dword to our struct which may be later * removed by standard */ -#define WMI_HECAP_MAC_MBAHECTRL_GET(he_cap) (0) /* DO NOT USE - DEPRECATED*/ -#define WMI_HECAP_MAC_MBAHECTRL_SET(he_cap, value) {;} /* DO NOT USE - DEPRECATED*/ +#define WMI_HECAP_MAC_MBAHECTRL_GET_D2(he_cap) (0) /* DO NOT USE - DEPRECATED*/ +#define WMI_HECAP_MAC_MBAHECTRL_SET_D2(he_cap, value) {;} /* DO NOT USE - DEPRECATED*/ -#define WMI_HECAP_MAC_MURTS_GET(he_cap) (0) /* DO NOT USE - DEPRECATED*/ -#define WMI_HECAP_MAC_MURTS_SET(he_cap, value) {;} /* DO NOT USE - DEPRECATED*/ +#define WMI_HECAP_MAC_MURTS_GET_D2(he_cap) (0) /* DO NOT USE - DEPRECATED*/ +#define WMI_HECAP_MAC_MURTS_SET_D2(he_cap, value) {;} /* DO NOT USE - DEPRECATED*/ /*Deprecate use WMI_HECAP_PHY_PREAMBLEPUNCRX instead*/ -#define WMI_HECAP_PHY_CBMODE_GET(he_cap_phy) WMI_HECAP_PHY_CBMODE_GET(he_cap_phy) -#define WMI_HECAP_PHY_CBMODE_SET(he_cap_phy, value) WMI_HECAP_PHY_CBMODE_SET(he_cap_phy, value) +#define WMI_HECAP_PHY_CBMODE_GET_D2(he_cap_phy) WMI_HECAP_PHY_CBMODE_GET_D2(he_cap_phy) +#define WMI_HECAP_PHY_CBMODE_SET_D2(he_cap_phy, value) WMI_HECAP_PHY_CBMODE_SET_D2(he_cap_phy, value) /* Below 2 macros are for maintaining backward compatability - Deprecated use WMI_HECAP_PHY_LTFGIFORHE_GET instead */ -#define WMI_HECAP_PHY_OLTF_GET(he_cap_phy) WMI_HECAP_PHY_LTFGIFORHE_GET(he_cap_phy) -#define WMI_HECAP_PHY_OLTF_SET(he_cap_phy, value) WMI_HECAP_PHY_LTFGIFORHE_SET(he_cap_phy, value) +#define WMI_HECAP_PHY_OLTF_GET_D2(he_cap_phy) WMI_HECAP_PHY_LTFGIFORHE_GET_D2(he_cap_phy) +#define WMI_HECAP_PHY_OLTF_SET_D2(he_cap_phy, value) WMI_HECAP_PHY_LTFGIFORHE_SET_D2(he_cap_phy, value) /*DEPRECATED - USE WMI_HECAP_PHY_BFMENLTSGT80MHZ*/ -#define WMI_HECAP_PHY_SUBFMESTS_GET(he_cap_phy) WMI_HECAP_PHY_BFMESTSLT80MHZ_GET(he_cap_phy) -#define WMI_HECAP_PHY_SUBFMESTS_SET(he_cap_phy, value) WMI_HECAP_PHY_BFMESTSLT80MHZ_SET(he_cap_phy, value) +#define WMI_HECAP_PHY_SUBFMESTS_GET_D2(he_cap_phy) WMI_HECAP_PHY_BFMESTSLT80MHZ_GET_D2(he_cap_phy) +#define WMI_HECAP_PHY_SUBFMESTS_SET_D2(he_cap_phy, value) WMI_HECAP_PHY_BFMESTSLT80MHZ_SET_D2(he_cap_phy, value) /*DEPRECATED - use WMI_HECAP_PHY_PETHRESPRESENT**/ -#define WMI_HECAP_PHY_PADDING_GET(he_cap_phy) WMI_HECAP_PHY_PETHRESPRESENT_GET(he_cap_phy) -#define WMI_HECAP_PHY_PADDING_SET(he_cap_phy, value) WMI_HECAP_PHY_PETHRESPRESENT_SET(he_cap_phy, value) +#define WMI_HECAP_PHY_PADDING_GET_D2(he_cap_phy) WMI_HECAP_PHY_PETHRESPRESENT_GET_D2(he_cap_phy) +#define WMI_HECAP_PHY_PADDING_SET_D2(he_cap_phy, value) WMI_HECAP_PHY_PETHRESPRESENT_SET_D2(he_cap_phy, value) /**DO NOT USE - DEPRECATED*/ -#define WMI_HECAP_PHY_DLOFMAMUMIMO_GET(he_cap_phy) (0) -#define WMI_HECAP_PHY_DLOFDMAMUMIO_SET(he_cap_phy, value) {;} +#define WMI_HECAP_PHY_DLOFMAMUMIMO_GET_D2(he_cap_phy) (0) +#define WMI_HECAP_PHY_DLOFDMAMUMIO_SET_D2(he_cap_phy, value) {;} /*DO NOT USE - DEPRECATED**/ -#define WMI_HECAP_PHY_32GI_GET(he_cap_phy) (0) -#define WMI_HECAP_PHY_32GI_SET(he_cap_phy, value) {;} +#define WMI_HECAP_PHY_32GI_GET_D2(he_cap_phy) (0) +#define WMI_HECAP_PHY_32GI_SET_D2(he_cap_phy, value) {;} /*DO NOT USE - DEPRECATED**/ -#define WMI_HECAP_PHY_NOSUNDIMENS_GET(he_cap_phy) (0) -#define WMI_HECAP_PHY_NOSUNDIMENS_SET(he_cap_phy, value) {;} +#define WMI_HECAP_PHY_NOSUNDIMENS_GET_D2(he_cap_phy) (0) +#define WMI_HECAP_PHY_NOSUNDIMENS_SET_D2(he_cap_phy, value) {;} /*DO NOT USE - DEPRECATED**/ -#define WMI_HECAP_PHY_40MHZNSS_GET(he_cap_phy)(0) -#define WMI_HECAP_PHY_40MHZNSS_SET(he_cap_phy, value) {;} +#define WMI_HECAP_PHY_40MHZNSS_GET_D2(he_cap_phy)(0) +#define WMI_HECAP_PHY_40MHZNSS_SET_D2(he_cap_phy, value) {;} /* START TEMPORARY WORKAROUND - * Leave legacy names as aliases for new names, until all references to the * legacy names have been removed. */ -#define WMI_HECAP_PHY_ULOFDMA_GET WMI_HECAP_PHY_ULMUMIMOOFDMA_GET -#define WMI_HECAP_PHY_ULOFDMA_SET WMI_HECAP_PHY_ULMUMIMOOFDMA_SET +#define WMI_HECAP_PHY_ULOFDMA_GET_D2 WMI_HECAP_PHY_ULMUMIMOOFDMA_GET_D2 +#define WMI_HECAP_PHY_ULOFDMA_SET_D2 WMI_HECAP_PHY_ULMUMIMOOFDMA_SET_D2 /* END TEMPORARY WORKAROUND */ /* DEPRECATED - use WMI_HECAP_PHY_DCMRX or WMI_HECAP_PHY_DCMTX */ -#define WMI_HECAP_PHY_DCM_GET(he_cap_phy) WMI_HECAP_PHY_DCMRX_GET(he_cap_phy) -#define WMI_HECAP_PHY_DCM_SET(he_cap_phy, value) WMI_HECAP_PHY_DCMRX_SET(he_cap_phy, value) +#define WMI_HECAP_PHY_DCM_GET_D2(he_cap_phy) WMI_HECAP_PHY_DCMRX_GET_D2(he_cap_phy) +#define WMI_HECAP_PHY_DCM_SET_D2(he_cap_phy, value) WMI_HECAP_PHY_DCMRX_SET_D2(he_cap_phy, value) /* * The maximum value for NSTS-1<=80MHz,(min val 3)total that can be sent * to the STA in a DL MU-MIMO transmission on full or partial bandwidth */ -#define WMI_HECAP_PHY_NSTSLT80MHZ_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 5, 3) -#define WMI_HECAP_PHY_NSTSLT80MHZ_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 5, 3, value) +#define WMI_HECAP_PHY_NSTSLT80MHZ_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 5, 3) +#define WMI_HECAP_PHY_NSTSLT80MHZ_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 5, 3, value) /* * The maximum value for NSTS-1 > 80MHz (min val 3) total that can be sent * to the STA in a DL MU-MIMO transmission on full or partial bandwidth */ -#define WMI_HECAP_PHY_NSTSGT80MHZ_GET(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 8, 3) -#define WMI_HECAP_PHY_NSTSGT80MHZ_SET(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 8, 3, value) +#define WMI_HECAP_PHY_NSTSGT80MHZ_GET_D2(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 8, 3) +#define WMI_HECAP_PHY_NSTSGT80MHZ_SET_D2(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 8, 3, value) #define WMI_GET_HW_RATECODE_PREAM_V1(_rcode) (((_rcode) >> 8) & 0x7) @@ -10368,6 +10417,9 @@ typedef struct { A_UINT32 peer_he_cap_phy[WMI_MAX_HECAP_PHY_SIZE]; A_UINT32 peer_he_mcs; /* Indicates number of HE MCS TLV present */ + /* 2nd DWORD of 11ax MAC Capabilities */ + A_UINT32 peer_he_cap_info_ext; + /* Following this struct are the TLV's: * A_UINT8 peer_legacy_rates[]; * A_UINT8 peer_ht_rates[]; @@ -15329,6 +15381,68 @@ typedef struct { A_UINT32 sw_retry_threshold; } wmi_peer_tid_configurations_cmd_fixed_param; +/* The below enable/disable macros are used for both per peer CFR capture + * control (as in wmi_peer_cfr_capture_cmd) and control of the entire periodic + * CFR capture feature (as in WMI_PDEV_PARAM_PER_PEER_PERIODIC_CFR_ENABLE) + */ +#define WMI_PEER_CFR_CAPTURE_ENABLE 1 +#define WMI_PEER_CFR_CAPTURE_DISABLE 0 + +#define WMI_PEER_CFR_ONE_SHOT_REQUEST 0 +#define WMI_PEER_CFR_PERIODICITY_MIN 10 /* 10ms */ +#define WMI_PEER_CFR_PERIODICITY_MAX 10*60*1000 /* 10 minutes */ + +/* Bandwidth of peer CFR captures */ +typedef enum { + WMI_PEER_CFR_CAPTURE_BW_20MHZ = 0, + WMI_PEER_CFR_CAPTURE_BW_40MHZ = 1, + WMI_PEER_CFR_CAPTURE_BW_80MHZ = 2, + WMI_PEER_CFR_CAPTURE_BW_160MHZ = 3, + WMI_PEER_CFR_CAPTURE_BW_80_80MHZ = 4, + WMI_PEER_CFR_CAPTURE_BW_MAX, +} WMI_PEER_CFR_CAPTURE_BW; + +/* Peer CFR capture method */ +typedef enum { + /* Send null frame on the requested bw and capture CFR on ACK */ + WMI_PEER_CFR_CAPTURE_METHOD_NULL_FRAME = 0, + /* New methods to be added here */ + WMI_PEER_CFR_CAPTURE_METHOD_MAX, +} WMI_PEER_CFR_CAPTURE_METHOD; + +/* + * Peer command structure to configure the CFR capture + */ +typedef struct { + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_peer_cfr_capture_cmd_fixed_param + */ + A_UINT32 tlv_header; + + /* WMI_PEER_CFR_CAPTURE_ENABLE: Enable CFR capture for the peer + * WMI_PEER_CFR_CAPTURE_DISABLE: Disable CFR capture for the peer + */ + A_UINT32 request; + /* Peer MAC address. In AP mode, this is the address of the connected peer + * for which CFR capture is needed. In case of STA mode, this is the address + * of the AP to which the STA is connected + */ + wmi_mac_addr mac_addr; + /* vdev id */ + A_UINT32 vdev_id; + /* Periodicity of measurement in ms. + * WMI_PEER_CFR_ONE_SHOT_REQUEST: One-shot request i.e., Only one CFR + * capture for the request and no periodic CFR captures. + * The min value is WMI_PEER_CFR_PERIODICITY_MIN + * The max value is WMI_PEER_CFR_PERIODICITY_MAX + */ + A_UINT32 periodicity; + /* BW of measurement - of type WMI_PEER_CFR_CAPTURE_BW */ + A_UINT32 bandwidth; + /* Method used to capture CFR - of type WMI_PEER_CFR_CAPTURE_METHOD */ + A_UINT32 capture_method; +} wmi_peer_cfr_capture_cmd_fixed_param; + typedef enum { WMI_PEER_IND_SMPS = 0x0, /* spatial multiplexing power save */ WMI_PEER_IND_OMN, /* operating mode notification */ @@ -21152,6 +21266,9 @@ typedef struct { A_UINT32 chainmask_table_id; /* PDEV ID to LMAC ID mapping */ A_UINT32 lmac_id; + /* 2nd DWORD of HE capability info field of 802.11ax, support Draft 3+ */ + A_UINT32 he_cap_info_2G_ext; + A_UINT32 he_cap_info_5G_ext; } WMI_MAC_PHY_CAPABILITIES; typedef struct { @@ -22080,6 +22197,7 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command) WMI_RETURN_STRING(WMI_MOTION_DET_BASE_LINE_START_STOP_CMDID); WMI_RETURN_STRING(WMI_SAR_LIMITS_CMDID); WMI_RETURN_STRING(WMI_SAR_GET_LIMITS_CMDID); + WMI_RETURN_STRING(WMI_PEER_CHAN_WIDTH_SWITCH_CMDID); } return "Invalid WMI cmd"; @@ -23002,8 +23120,8 @@ typedef struct { typedef enum { NO_SCALING = 0, /* No bin scaling*/ /** - * scaled_bin_mag = bin_mag * - * sqrt(10^(max(legacy_max_gain - default_agc_max_gain + low_level_offset - RSSI_corr, + * scaled_bin_mag = bin_mag * + * sqrt(10^(max(legacy_max_gain - default_agc_max_gain + low_level_offset - RSSI_corr, * (agc_total_gain_db < default_agc_max_gain) * high_level_offset)/10)) * * 2^(DET{0,1,2}_SPECTRAL_SCAN_BIN_SCALE - legacy_spectral_scan_bin_scale) */ @@ -23308,6 +23426,1039 @@ typedef struct { A_UINT32 vdev_id; } wmi_obss_spatial_reuse_set_cmd_fixed_param; +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUCT_wmi_chan_width_peer_list */ + wmi_mac_addr peer_macaddr; + A_UINT32 chan_width; /* wmi_channel_width */ +} wmi_chan_width_peer_list; + +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_chan_width_switch_cmd_fixed_param */ + A_UINT32 num_peers; + /* + * Following this structure is the TLV: + * struct wmi_chan_width_peer_list chan_width_peer_info[num_peers]; + */ +} wmi_peer_chan_width_switch_cmd_fixed_param; + +/* Default PE Duration subfield indicates the PE duration in units of 4 us */ +#define WMI_HEOPS_DEFPE_GET_D3(he_ops) WMI_GET_BITS(he_ops, 0, 3) +#define WMI_HEOPS_DEFPE_SET_D3(he_ops, value) WMI_SET_BITS(he_ops, 0, 3, value) + +/* TWT required */ +#define WMI_HEOPS_TWT_REQUIRED_GET_D3(he_ops) WMI_GET_BITS(he_ops, 3, 1) +#define WMI_HEOPS_TWT_REQUIRED_SET_D3(he_ops, value) WMI_SET_BITS(he_ops, 3, 1, value) + +/* RTS threshold in units of 32 us,0 - always use RTS 1023 - this is disabled */ +#define WMI_HEOPS_RTSTHLD_GET_D3(he_ops) WMI_GET_BITS(he_ops, 4, 10) +#define WMI_HEOPS_RTSTHLD_SET_D3(he_ops, value) WMI_SET_BITS(he_ops, 4, 10, value) + +/* VHT Operation Information Present */ +#define WMI_HEOPS_VHTOPSPRSNT_GET_D3(he_ops) WMI_GET_BITS(he_ops, 14, 1) +#define WMI_HEOPS_VHTOPSPRSNT_SET_D3(he_ops, value) WMI_SET_BITS(he_ops, 14, 1, value) + +/* Co-Located BSS */ +#define WMI_HEOPS_COLOCBSS_GET_D3(he_ops) WMI_GET_BITS(he_ops, 15, 1) +#define WMI_HEOPS_COLOCBSS_SET_D3(he_ops, value) WMI_SET_BITS(he_ops, 15, 1, value) + +/* ER SU Disable */ +#define WMI_HEOPS_ERSUDIS_GET_D3(he_ops) WMI_GET_BITS(he_ops, 16, 1) +#define WMI_HEOPS_ERSUDIS_SET_D3(he_ops, value) WMI_SET_BITS(he_ops, 16, 1, value) + +/* bit17 - bit23 are reserved */ + +/* BSS color */ +#define WMI_HEOPS_COLOR_GET_D3(he_ops) WMI_GET_BITS(he_ops, 24, 6) +#define WMI_HEOPS_COLOR_SET_D3(he_ops, value) WMI_SET_BITS(he_ops, 24, 6, value) + +/* Partial BSS Color field indicates whether BSS applies an AID assignment rule using partial BSS color bits */ +#define WMI_HEOPS_PARTBSSCOLOR_GET_D3(he_ops) WMI_GET_BITS(he_ops, 30, 1) +#define WMI_HEOPS_PARTBSSCOLOR_SET_D3(he_ops, value) WMI_SET_BITS(he_ops, 30, 1, value) + +/* when set to 1 disables use of BSS color */ +#define WMI_HEOPS_BSSCOLORDISABLE_GET_D3(he_ops) WMI_GET_BITS(he_ops, 31, 1) +#define WMI_HEOPS_BSSCOLORDISABLE_SET_D3(he_ops, value) WMI_SET_BITS(he_ops, 31, 1, value) + +/* PHY Capabilities Information field */ + + +/* bit 0 reserved */ + +/* + * B0: Indicates STA support 40 MHz channel width in 2.4 GHz + * B1: Indicates STA support 40 MHz and 80 MHz channel width in 5 GHz + * B2: Indicates STA supports 160 MHz channel width in 5 GHz + * B3: Indicates STA supports 160/80+80 MHz channel width in 5 GHz + * B4: If B1 is set to 0, then B5 indicates support of 242/106/52/26-tone + * RU mapping in 40 MHz channel width in 2.4 GHz. Otherwise Reserved. + * B5: If B2, B3, and B4 are set to 0, then B6 indicates support of + * 242-tone RU mapping in 40 MHz and 80 + * MHz channel width in 5 GHz. Otherwise Reserved. + * B6: Reserved + */ +#define WMI_HECAP_PHY_CBW_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 1, 7) +#define WMI_HECAP_PHY_CBW_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 1, 7, value) + +/* + * B0: Indicates STA supports reception of preamble puncturing in 80 MHz, + * where in the preamble only the secondary 20 MHz is punctured + * B1: Indicates STA supports reception of preamble puncturing in 80 MHz, + * where in the preamble only one of the two 20 MHz sub-channels in the + * secondary 40 MHz is punctured + * B2: Indicates STA supports reception of preamble puncturing in 160 MHz + * or 80+80 MHz, where in the primary 80 MHz of the preamble only the + * secondary 20 MHz is punctured + * B3: Indicates STA supports reception of preamble puncturing in 160 MHz + * or 80+80 MHz, where in the primary 80 MHz of the preamble, the + * primary 40 MHz is present + */ +#define WMI_HECAP_PHY_PREAMBLEPUNCRX_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 8, 4) +#define WMI_HECAP_PHY_PREAMBLEPUNCRX_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 8, 4, value) + +/* Indicates transmitting STA is a Class A (1) or a Class B (0) device */ +#define WMI_HECAP_PHY_COD_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 12, 1) +#define WMI_HECAP_PHY_COD_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 12, 1, value) + +/* Indicates support of transmission and reception of LDPC encoded packets */ +#define WMI_HECAP_PHY_LDPC_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 13, 1) +#define WMI_HECAP_PHY_LDPC_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 13, 1, value) + +/* + * B0: Indicates support of reception of 1x LTF and 0.8us guard interval duration for HE SU PPDUs. + */ +#define WMI_HECAP_PHY_LTFGIFORHE_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 14, 1) +#define WMI_HECAP_PHY_LTFGIFORHE_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 14, 1, value) + +/* + * If the Doppler Rx subfield is 1, indicates the maximum number of space-time streams supported for reception + * when a midamble is present in the Data field. + * If the Doppler Tx subfield is 1, indicates the maximum number of space-time streams supported for transmission + * when a midamble is present in the Data field. + * If both Doppler Rx and Doppler Tx subfields are 1, indicates the maximum number of space-time streams + * supported for transmission and reception when a midamble is present in the Data field. + */ +#define WMI_HECAP_PHY_MIDAMBLETXRXMAXNSTS_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 15, 2) +#define WMI_HECAP_PHY_MIDAMBLETXRXMAXNSTS_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 15, 2, value) + +/* + * B0: For a transmitting STA acting as beamformee, it indicates support of + * NDP reception using 4x LTF and 3.2 us guard interval duration + */ +#define WMI_HECAP_PHY_LTFGIFORNDP_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 17, 1) +#define WMI_HECAP_PHY_LTFGIFORNDP_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 17, 1, value) + +/* indicates support for the transmission of HE PPDUs using STBC with one spatial stream for <= 80MHz Tx */ +#define WMI_HECAP_PHY_TXSTBC_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 18, 1) +#define WMI_HECAP_PHY_TXSTBC_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 18, 1, value) + +/* indicates support for the reception of HE PPDUs using STBC with one spatial stream for <= 80MHz Tx */ +#define WMI_HECAP_PHY_RXSTBC_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 19, 1) +#define WMI_HECAP_PHY_RXSTBC_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 19, 1, value) + +/* indicates transmitting STA supports transmitting HE PPDUs with Doppler procedure */ +#define WMI_HECAP_PHY_TXDOPPLER_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 20, 1) +#define WMI_HECAP_PHY_TXDOPPLER_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 20, 1, value) + +/* indicates transmitting STA supports receiving HE PPDUs with Doppler procedure */ +#define WMI_HECAP_PHY_RXDOPPLER_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 21, 1) +#define WMI_HECAP_PHY_RXDOPPLER_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 21, 1, value) + +/* + * If the transmitting STA is an AP: + * indicates STA supports of reception of full bandwidth UL MU-MIMO + * transmission. + * If the transmitting STA is a non-AP STA: + * indicates STA supports of transmission of full bandwidth UL MU-MIMO + * transmission. + */ +#define WMI_HECAP_PHY_UL_MU_MIMO_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 22, 1) +#define WMI_HECAP_PHY_UL_MU_MIMO_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 22, 1, value) + +/* + * If the transmitting STA is an AP: + * indicates STA supports of reception of UL MUMIMO transmission on an + * RU in an HE MU PPDU where the RU does not span the entire PPDU bandwidth. + * If the transmitting STA is a non-AP STA: + * indicates STA supports of transmission of UL MU-MIMO transmission on an + * RU in an HE MU PPDU where the RU does not span the entire PPDU bandwidth. + */ +#define WMI_HECAP_PHY_ULMUMIMOOFDMA_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 23, 1) +#define WMI_HECAP_PHY_ULMUMIMOOFDMA_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 23, 1, value) + +/* Tx DCM + * B0:B1 + * 00: Does not support DCM + * 01: BPSK + * 10: QPSK + * 11: 16-QAM + * B2 signals maximum number of spatial streams with DCM + * 0: 1 spatial stream + * 1: 2 spatial streams + */ +#define WMI_HECAP_PHY_DCMTX_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 24, 3) +#define WMI_HECAP_PHY_DCMTX_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 24, 3, value) + +/* Rx DCM + * B0:B1 + * 00: Does not support DCM + * 01: BPSK + * 10: QPSK + * 11: 16-QAM + * B2 signals maximum number of spatial streams with DCM + * 0: 1 spatial stream + * 1: 2 spatial streams + */ +#define WMI_HECAP_PHY_DCMRX_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 27, 3) +#define WMI_HECAP_PHY_DCMRX_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 27, 3, value) + + +/* + * Indicates that the STA supports the reception of an HE MU PPDU payload + * over full bandwidth and partial bandwidth (106-tone RU within 20 MHz). + */ +#define WMI_HECAP_PHY_ULHEMU_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 30, 1) +#define WMI_HECAP_PHY_ULHEMU_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 30, 1, value) + +/* Indicates support for operation as an SU beamformer */ +#define WMI_HECAP_PHY_SUBFMR_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[0], 31, 1) +#define WMI_HECAP_PHY_SUBFMR_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[0], 31, 1, value) + +/* Indicates support for operation as an SU beamformee */ +#define WMI_HECAP_PHY_SUBFME_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 0, 1) +#define WMI_HECAP_PHY_SUBFME_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 0, 1, value) + +/* Indicates support for operation as an MU Beamformer */ +#define WMI_HECAP_PHY_MUBFMR_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 1, 1) +#define WMI_HECAP_PHY_MUBFMR_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 1, 1, value) + +/* + * Num STS -1 for <= 80MHz (min val 3) + * The maximum number of space-time streams minus 1 that the STA can + * receive in an HE NDP + */ +#define WMI_HECAP_PHY_BFMESTSLT80MHZ_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 2, 3) +#define WMI_HECAP_PHY_BFMESTSLT80MHZ_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 2, 3, value) + + +/* + * Num STS -1 for > 80MHz (min val 3) + * The maximum number of space-time streams minus 1 that the STA can + * receive in an HE NDP + */ +#define WMI_HECAP_PHY_BFMESTSGT80MHZ_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 5, 3) +#define WMI_HECAP_PHY_BFMESTSGT80MHZ_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 5, 3, value) + + +/* + * Number Of Sounding Dimensions For <= 80 MHz + * If SU beamformer capable, set to the maximum supported value of the + * TXVECTOR parameter NUM_STS minus 1. + * Otherwise, reserved. + */ +#define WMI_HECAP_PHY_NUMSOUNDLT80MHZ_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 8, 3) +#define WMI_HECAP_PHY_NUMSOUNDLT80MHZ_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 8, 3, value) + +/* + * Number Of Sounding Dimensions For > 80 MHz + * If SU beamformer capable, set to the maximum supported value of the + * TXVECTOR parameter NUM_STS minus 1. + * Otherwise, reserved. + */ +#define WMI_HECAP_PHY_NUMSOUNDGT80MHZ_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 11, 3) +#define WMI_HECAP_PHY_NUMSOUNDGT80MHZ_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 11, 3, value) + +/* + * Indicates if the HE beamformee is capable of feedback with tone + * grouping of 16 in the HE Compressed Beamforming Report field for + * a SU-type feedback. + */ +#define WMI_HECAP_PHY_NG16SUFEEDBACKLT80_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 14, 1) +#define WMI_HECAP_PHY_NG16SUFEEDBACKLT80_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 14, 1, value) + +/* + * Indicates if the HE beamformee is capable of feedback with tone + * grouping of 16 in the HE Compressed Beamforming Report field for + * a MU-type feedback. + */ +#define WMI_HECAP_PHY_NG16MUFEEDBACKGT80_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 15, 1) +#define WMI_HECAP_PHY_NG16MUFEEDBACKGT80_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 15, 1, value) + +/* + * Indicates if HE beamformee is capable of feedback with codebook + * size {4, 2} in the HECompressed Beamforming Report field for + * a SU-type feedback. + */ +#define WMI_HECAP_PHY_CODBK42SU_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 16, 1) +#define WMI_HECAP_PHY_CODBK42SU_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 16, 1, value) + +/* + * Indicates if HE beamformee is capable of feedback with codebook + * size {7, 5} in the HE Compressed Beamforming Report field for + * a MU-type feedback. + */ +#define WMI_HECAP_PHY_CODBK75MU_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 17, 1) +#define WMI_HECAP_PHY_CODBK75MU_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 17, 1, value) + +/* + * Beamforming Feedback With Trigger Frame + * If the transmitting STA is an AP STA: + * B0: indicates support of reception of SU-Type partial(1) and full bandwidth feedback(0) + * B1: indicates support of reception of MU-Type partial(1) bandwidth feedback + * B2: indicates support of reception of CQI-Only partial and full bandwidth feedback + * If the transmitting STA is a non-AP STA: + * B0: indicates support of transmission of SU-Type partial(1) and full bandwidth(0) feedback + * B1: indicates support of transmission of MU-Type partial(1) bandwidth feedback + * B2: indicates support of transmission of CQI-Onlypartial (1)and full bandwidth feedback + */ +#define WMI_HECAP_PHY_BFFEEDBACKTRIG_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 18, 3) +#define WMI_HECAP_PHY_BFFEEDBACKTRIG_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 18, 3, value) + +/* Indicates the support of transmission and reception of an HE extended range SU PPDU payload transmitted + * over the right 106-tone RU or partial BW ER + */ +#define WMI_HECAP_PHY_HEERSU_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 21, 1) +#define WMI_HECAP_PHY_HEERSU_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 21, 1, value) + +/* Indicates that the non-AP STA supports reception of a DL MU-MIMO transmission on an RU in an HE MU PPDU + * where the RU does not span the entire PPDU bandwidth. + */ +#define WMI_HECAP_PHY_DLMUMIMOPARTIALBW_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 22, 1) +#define WMI_HECAP_PHY_DLMUMIMOPARTIALBW_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 22, 1, value) + +/* Indicates whether or not the PPE Threshold field is present */ +#define WMI_HECAP_PHY_PETHRESPRESENT_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 23, 1) +#define WMI_HECAP_PHY_PETHRESPRESENT_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 23, 1, value) + +/* Indicates that the STA supports SRP-based SR operation */ +#define WMI_HECAP_PHY_SRPSPRESENT_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 24, 1) +#define WMI_HECAP_PHY_SRPPRESENT_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 24, 1, value) + +/* Indicates that the STA supports a power boost factor ar for the r-th RU in the range [0.5, 2] */ +#define WMI_HECAP_PHY_PWRBOOSTAR_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 25, 1) +#define WMI_HECAP_PHY_PWRBOOSTAR_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 25, 1, value) + +/* Indicates support for the reception of 4x LTF and 0.8us guard interval duration for HE SU PPDUs. */ +#define WMI_HECAP_PHY_4XLTFAND800NSECSGI_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 26, 1) +#define WMI_HECAP_PHY_4XLTFAND800NSECSGI_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 26, 1, value) + +/* For a transmitting STA acting as a beamformee, it indicates the maximum Nc for beamforming sounding + * feedback supported If SU beamformee capable, then set to the maximum Nc for beamforming sounding feedback + * minus 1. Otherwise, reserved. + */ +#define WMI_HECAP_PHY_MAXNC_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 27, 3) +#define WMI_HECAP_PHY_MAXNC_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 27, 3, value) + +/* Indicates support for the transmission of an HE PPDU that has a bandwidth greater than 80 MHz and is using + * STBC with one spatial stream + */ +#define WMI_HECAP_PHY_STBCTXGT80_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 30, 1) +#define WMI_HECAP_PHY_STBCTXGT80_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 30, 1, value) + +/* Indicates support for the reception of an HE PPDU that has a bandwidth greater than 80 MHz and is using + * STBC with one spatial stream + */ +#define WMI_HECAP_PHY_STBCRXGT80_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[1], 31, 1) +#define WMI_HECAP_PHY_STBCRXGT80_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[1], 31, 1, value) + +/* Indicates support for the reception of an HE ER SU PPDU with 4x LTF and 0.8 us guard interval duration */ +#define WMI_HECAP_PHY_ERSU4X800NSECGI_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[2], 0, 1) +#define WMI_HECAP_PHY_ERSU4X800NSECGI_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[2], 0, 1, value) + +/* + * Indicates support of 26-, 52-, and 106-tone mapping for a 20 MHz operating non-AP HE STA that is the + * receiver of a 40 MHz HE MU PPDU in 2.4 GHz band, or the transmitter of a 40 MHz HE TB PPDU in 2.4GHz band. + */ +#define WMI_HECAP_PHY_HEPPDU20IN40MHZ2G_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[2], 1, 1) +#define WMI_HECAP_PHY_HEPPDU20IN40MHZ2G_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[2], 1, 1, value) + +/* + * Indicates support of 26-, 52-, and 106-tone mapping for a 20 MHz operating non-AP HE STA that is the + * receiver of a 80+80 MHz or a 160 MHz HE MU PPDU, or the transmitter of a 80+80 MHz or 160 MHz HE TB PPDU. + */ +#define WMI_HECAP_PHY_HEPPDU20IN160OR80P80MHZ_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[2], 2, 1) +#define WMI_HECAP_PHY_HEPPDU20IN160OR80P80MHZ_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[2], 2, 1, value) + +/* + * Indicates supports of 160 MHz OFDMA for a non-AP HE STA that sets bit B1 of Channel Width Set to 1, and + * sets B2 and B3 of Channel Width Set each to 0, when operating with 80 MHz channel width. The capability + * bit is applicable while receiving a 80+80 MHz or a 160 MHz HE MU PPDU, or transmitting a 80+80 MHz or a + * 160 MHz HE TB PPDU. + */ +#define WMI_HECAP_PHY_HEPPDU80IN160OR80P80MHZ_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[2], 3, 1) +#define WMI_HECAP_PHY_HEPPDU80IN160OR80P80MHZ_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[2], 3, 1, value) + +/* Indicates support for the reception of an HE ER SU PPDU with 1x LTF and 0.8 us guard interval duration */ +#define WMI_HECAP_PHY_ERSU1X800NSECGI_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[2], 4, 1) +#define WMI_HECAP_PHY_ERSU1X800NSECGI_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[2], 4, 1, value) + +/* + * If the Doppler Rx subfield is 1, indicates support for receiving midambles with 2x HE-LTF, 1x HE-LTF in + * HE SU PPDU if the HE SU PPDU With 1x HE-LTF And 0.8 s GI subfield is set to 1, and 1x HE-LTF in + * HE ER SU PPDU if the HE ER SU PPDU With 1x HELTF And 0.8 s GI subfield is set to 1. + * + * If the Doppler Tx subfield is 1, indicates support for transmitting midambles with 2x HE-LTF, 1x HE-LTF + * in HE TB PPDU when allowed. + + * If both the Doppler Rx and Doppler Tx subfields are 1, indicates support for receiving midambles with 2x HELTF, + * 1x HE-LTF in HE SU PPDU if the HE SU PPDU With 1x HE-LTF And 0.8 s GI subfield is set to 1, and + * 1x HE-LTF in HE ER SU PPDU if the HE ER SU PPDU With 1x HE-LTF And 0.8 s GI subfield is set + * to 1; and also support for transmitting midambles with 2x HE-LTF, 1x HE-LTF in HE TB PPDU when allowed. + */ +#define WMI_HECAP_PHY_MIDAMBLETXRX2XAND1XHELTF_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[2], 5, 1) +#define WMI_HECAP_PHY_MIDAMBLETXRX2XAND1XHELTF_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[2], 5, 1, value) + +/* + * If the DCM Max Constellation Tx subfield is greater than 0, then the DCM Max BW subfield indicates the + * maximum bandwidth of a PPDU that the STA might transmit with DCM applied. + * + * If the DCM Max Constellation Rx subfield is greater than 0, then the DCM Max BW subfield indicates the + * maximum bandwidth of a PPDU with DCM applied that the STA can receive. + * + * If both the DCM Max Constellation Tx subfield and DCM Max Constellation Rx subfield are 0, then this + * subfield is reserved. + * + * 0=20MHz, 1=40Mhz, 2=80Mhz, 3=160Mhz or 80+80Mhz + */ +#define WMI_HECAP_PHY_DCMMAXBW_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[2], 6, 2) +#define WMI_HECAP_PHY_DCMMAXBW_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[2], 6, 2, value) + +/* + * For a non-AP STA, indicates support for receiving a DL HE MU PPDU where the number of OFDM symbols + * in the HE SIG-B field is greater than 16. + */ +#define WMI_HECAP_PHY_LNG16SIGBSYMBSUPRT_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[2], 8, 1) +#define WMI_HECAP_PHY_LNG16SIGBSYMBSUPRT_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[2], 8, 1, value) + +/* + * For an AP, indicates support for the reception of full bandwidth non-triggered CQI-only feedback. + * For a non-AP STA, indicates support for the transmission of full bandwidth non-triggered CQI-only feedback. + */ +#define WMI_HECAP_PHY_NONTRIGCQIFEEDBK_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[2], 9, 1) +#define WMI_HECAP_PHY_NONTRIGCQIFEEDBK_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[2], 9, 1, value) + +/* + * For a non-AP STA, indicates support for the transmission of 1024-QAM on a 26-, 52-, and 106-tone RU. + * Reserved for an AP. + */ +#define WMI_HECAP_PHY_TX1024QAM242RUSUPRT_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[2], 10, 1) +#define WMI_HECAP_PHY_TX1024QAM242RUSUPRT_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[2], 10, 1, value) + +/* + * Indicates support for the reception of 1024-QAM on a 26-, 52-, and 106-tone RU. + */ +#define WMI_HECAP_PHY_RX1024QAM242RUSUPRT_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[2], 11, 1) +#define WMI_HECAP_PHY_RX1024QAM242RUSUPRT_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[2], 11, 1, value) + +/* + * Indicates support for reception of an HE MU PPDU with an RU spanning the entire PPDU bandwidth and a + * compressed HE-SIG-B format. + */ +#define WMI_HECAP_PHY_RXFULBWSUWCMPRSSIGB_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[2], 12, 1) +#define WMI_HECAP_PHY_RXFULBWSUWCMPRSSIGB_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[2], 12, 1, value) + +/* + * Indicates support for reception of an HE MU PPDU with a bandwidth less than or equal to 80 MHz, an RU + * spanning the entire PPDU bandwidth and a non-compressed HE-SIG-B format. + */ +#define WMI_HECAP_PHY_RXFULBWSUWNONCMPRSSIGB_GET_D3(he_cap_phy) WMI_GET_BITS(he_cap_phy[2], 13, 1) +#define WMI_HECAP_PHY_RXFULBWSUWNONCMPRSSIGB_SET_D3(he_cap_phy, value) WMI_SET_BITS(he_cap_phy[2], 13, 1, value) + +/* HE MAC Capabilities Information field format */ + +/* HTC + HE Support Set to 1 if STA supports reception of HE Variant HT control Field */ +#define WMI_HECAP_MAC_HECTRL_GET_D3(he_cap) WMI_GET_BITS(he_cap, 0, 1) +#define WMI_HECAP_MAC_HECTRL_SET_D3(he_cap, value) WMI_SET_BITS(he_cap, 0, 1, value) + +/* set to 1 to for TWT Requestor support */ +#define WMI_HECAP_MAC_TWTREQ_GET_D3(he_cap) WMI_GET_BITS(he_cap, 1, 1) +#define WMI_HECAP_MAC_TWTREQ_SET_D3(he_cap, value) WMI_SET_BITS(he_cap, 1, 1, value) + +/* set to 1 to for TWT Responder support */ +#define WMI_HECAP_MAC_TWTRSP_GET_D3(he_cap) WMI_GET_BITS(he_cap, 2, 1) +#define WMI_HECAP_MAC_TWTRSP_SET_D3(he_cap, value) WMI_SET_BITS(he_cap, 2, 1, value) + +/* Level of frag support + Set to 0 for no support for dynamic fragmentation. + Set to 1 for support for dynamic fragments that are contained within a S-MPDU + Set to 2 for support for dynamic fragments that are contained within a Single MPDU and support for up to + one dynamic fragment for each MSDU and each MMPDU within an A-MPDU or multi-TID A-MPDU. + Set to 3 for support for dynamic fragments that are contained within a Single MPDU and support for multiple + dynamic fragments for each MSDU within an AMPDU or multi-TID AMPDU and up to one dynamic fragment + for each MMPDU in a multi-TID A-MPDU that is not a Single MPDU +*/ +#define WMI_HECAP_MAC_HEFRAG_GET_D3(he_cap) WMI_GET_BITS(he_cap, 3, 2) +#define WMI_HECAP_MAC_HEFRAG_SET_D3(he_cap, value) WMI_SET_BITS(he_cap, 3, 2, value) + +/* The maximum number of fragmented MSDUs, Nmax,defined by this field is Nmax = 2 Maximum Number Of FMPDUs */ +#define WMI_HECAP_MAC_MAXFRAGMSDU_GET_D3(he_cap) WMI_GET_BITS(he_cap, 5, 3) +#define WMI_HECAP_MAC_MAXFRAGMSDU_SET_D3(he_cap, value) WMI_SET_BITS(he_cap, 5, 3, value) + + +/* 0 = no restriction on the minimum payload , 1 = 128 octets min, 2 = 256 octets min, 3 = 512 octets min */ +#define WMI_HECAP_MAC_MINFRAGSZ_GET_D3(he_cap) WMI_GET_BITS(he_cap, 8, 2) +#define WMI_HECAP_MAC_MINFRAGSZ_SET_D3(he_cap, value) WMI_SET_BITS(he_cap, 8, 2, value) + +/*0 = no additional processing time, 1 = 8us,2 = 16us */ +#define WMI_HECAP_MAC_TRIGPADDUR_GET_D3(he_cap) WMI_GET_BITS(he_cap, 10, 2) +#define WMI_HECAP_MAC_TRIGPADDUR_SET_D3(he_cap, value) WMI_SET_BITS(he_cap, 10, 2, value) + +/* Indicates the number of TIDs of QoS Data frames that an HE STA can receive in a multi-TID AMPDU */ +#define WMI_HECAP_MAC_MTID_RX_GET_D3(he_cap) WMI_GET_BITS(he_cap, 12, 3) +#define WMI_HECAP_MAC_MTID_RX_SET_D3(he_cap, value) WMI_SET_BITS(he_cap, 12, 3, value) + +/* Indicates support for link adaptation using the HLA Control subfield. */ +#define WMI_HECAP_MAC_HELINK_ADPT_GET_D3(he_cap) WMI_GET_BITS(he_cap, 15, 2) +#define WMI_HECAP_MAC_HELINK_ADPT_SET_D3(he_cap, value) WMI_SET_BITS(he_cap, 15, 2, value) + +/* Set to 1 for reception of AllAck support */ +#define WMI_HECAP_MAC_AACK_GET_D3(he_cap) WMI_GET_BITS(he_cap, 17, 1) +#define WMI_HECAP_MAC_AACK_SET_D3(he_cap, value) WMI_SET_BITS(he_cap, 17, 1, value) + +/* Set to 1 if the STA supports reception of the UL MU Response Scheduling A-Control field */ +#define WMI_HECAP_MAC_TRS_GET_D3(he_cap) WMI_GET_BITS(he_cap, 18, 1) +#define WMI_HECAP_MAC_TRS_SET_D3(he_cap, value) WMI_SET_BITS(he_cap, 18, 1, value) + +/* Set to 1 if the STA supports the BSR A-Control field functionality.*/ +#define WMI_HECAP_MAC_BSR_GET_D3(he_cap) WMI_GET_BITS(he_cap, 19, 1) +#define WMI_HECAP_MAC_BSR_SET_D3(he_cap, value) WMI_SET_BITS(he_cap, 19, 1, value) + +/* Set to 1 when the STA supports broadcast TWT functionality.*/ +#define WMI_HECAP_MAC_BCSTTWT_GET_D3(he_cap) WMI_GET_BITS(he_cap, 20, 1) +#define WMI_HECAP_MAC_BCSTTWT_SET_D3(he_cap, value) WMI_SET_BITS(he_cap, 20, 1, value) + +/* Set to 1 if STA supports rx of Multi-STA BA that has 32-bit Block Ack Bitmap */ +#define WMI_HECAP_MAC_32BITBA_GET_D3(he_cap) WMI_GET_BITS(he_cap, 21, 1) +#define WMI_HECAP_MAC_32BITBA_SET_D3(he_cap, value) WMI_SET_BITS(he_cap, 21, 1, value) + +/* Set to 1 if the STA supports MU cascading operation */ +#define WMI_HECAP_MAC_MUCASCADE_GET_D3(he_cap) WMI_GET_BITS(he_cap, 22, 1) +#define WMI_HECAP_MAC_MUCASCADE_SET_D3(he_cap, value) WMI_SET_BITS(he_cap, 22, 1, value) + +/* Set to 1 when the STA supports reception of this multi-TID A-MPDU format */ +#define WMI_HECAP_MAC_ACKMTIDAMPDU_GET_D3(he_cap) WMI_GET_BITS(he_cap, 23, 1) +#define WMI_HECAP_MAC_ACKMTIDAMPDU_SET_D3(he_cap, value) WMI_SET_BITS(he_cap, 23, 1, value) + +/* bit 24 - reserved */ + +/* Set to 1 if the STA supports reception of the OMI A-Control field */ +#define WMI_HECAP_MAC_OMI_GET_D3(he_cap) WMI_GET_BITS(he_cap, 25, 1) +#define WMI_HECAP_MAC_OMI_SET_D3(he_cap, value) WMI_SET_BITS(he_cap, 25, 1, value) + +/*1 if OFDMA Random Access Supported */ +#define WMI_HECAP_MAC_OFDMARA_GET_D3(he_cap) WMI_GET_BITS(he_cap, 26, 1) +#define WMI_HECAP_MAC_OFDMARA_SET_D3(he_cap, value) WMI_SET_BITS(he_cap, 26, 1, value) + +/* Maximum AMPDU Length Exponent. + * If the HE STA includes a VHT Capabilities element, the Maximum A-MPDU Length Exponent subfield in + * HE Capabilities element combined with the Maximum A-MPDU Length Exponent subfield in VHT + * Capabilities element indicate the maximum length of A-MPDU that the STA can Receive where EOF + * padding is not included in this limit. +*/ +#define WMI_HECAP_MAC_MAXAMPDULEN_EXP_GET_D3(he_cap) WMI_GET_BITS(he_cap, 27, 2) +#define WMI_HECAP_MAC_MAXAMPDULEN_EXP_SET_D3(he_cap, value) WMI_SET_BITS(he_cap, 27, 2, value) + + +/* A-MSDU Fragmentation Support */ +#define WMI_HECAP_MAC_AMSDUFRAG_GET_D3(he_cap) WMI_GET_BITS(he_cap, 29, 1) +#define WMI_HECAP_MAC_AMSDUFRAG_SET_D3(he_cap, value) WMI_SET_BITS(he_cap, 29, 1, value) + +/* Flexible TWT Schedule Support */ +#define WMI_HECAP_MAC_FLEXTWT_GET_D3(he_cap) WMI_GET_BITS(he_cap, 30, 1) +#define WMI_HECAP_MAC_FLEXTWT_SET_D3(he_cap, value) WMI_SET_BITS(he_cap, 30, 1, value) + +/* Rx Control Frame to MultiBSS */ +#define WMI_HECAP_MAC_MBSS_GET_D3(he_cap) WMI_GET_BITS(he_cap, 31, 1) +#define WMI_HECAP_MAC_MBSS_SET_D3(he_cap, value) WMI_SET_BITS(he_cap, 31, 1, value) + +/* 2nd DWORD of HE MAC Capabilities */ + +/* BSRP A-MPDU Aggregation + * maintaining compatability since we dont support this now so not wasting memory + */ +#define WMI_HECAP_MAC_BSRPAMPDU_GET_D3(he_cap2) WMI_GET_BITS(he_cap2, 0, 1) +#define WMI_HECAP_MAC_BSRPAMPDU_SET_D3(he_cap2, value) WMI_SET_BITS(he_cap2, 0, 1, value) + +/* Quiet Time Period (QTP) operation + * maintaining compatability since we dont support this now so not wasting memory + */ +#define WMI_HECAP_MAC_QTP_GET_D3(he_cap2) WMI_GET_BITS(he_cap2, 1, 1) +#define WMI_HECAP_MAC_QTP_SET_D3(he_cap2, value) WMI_SET_BITS(he_cap2, 1, 1, value) + +/* support by an AP for receiving an (A-)MPDU that contains a BQR in the + * A-Control subfield and support by a non-AP STA for generating an (A-)MPDU + * that contains a BQR in the A-Control subfield + * maintaining compatability since we dont support this now so not wasting memory + */ +#define WMI_HECAP_MAC_ABQR_GET_D3(he_cap2) WMI_GET_BITS(he_cap2, 2, 1) +#define WMI_HECAP_MAC_ABQR_SET_D3(he_cap2, value) WMI_SET_BITS(he_cap2, 2, 1, value) + +/* Indicates support by the STA for the role of SRP Responder.*/ +#define WMI_HECAP_MAC_SRPRESP_GET_D3(he_cap2) WMI_GET_BITS(he_cap2, 3, 1) +#define WMI_HECAP_MAC_SRPRESP_SET_D3(he_cap2, value) WMI_SET_BITS(he_cap2, 3, 1, value) + +/* Indicates support for a non-AP STA to follow the NDP feedback report procedure and respond to + * the NDP Feedback Report Poll Trigger frame. + */ +#define WMI_HECAP_MAC_NDPFDBKRPT_GET_D3(he_cap2) WMI_GET_BITS(he_cap2, 4, 1) +#define WMI_HECAP_MAC_NDPFDBKRPT_SET_D3(he_cap2, value) WMI_SET_BITS(he_cap2, 4, 1, value) + +/* Indicates support for an AP to encode OPS information to TIM element of the FILS Discovery + * frames or TIM frames as described in AP operation for opportunistic power save. + * Indicates support for a non-AP STA to receive the opportunistic power save encoded TIM elements + */ +#define WMI_HECAP_MAC_OPS_GET_D3(he_cap2) WMI_GET_BITS(he_cap2, 5, 1) +#define WMI_HECAP_MAC_OPS_SET_D3(he_cap2, value) WMI_SET_BITS(he_cap2, 5, 1, value) + +/* Indicates support by a STA to receive an ack-enabled A-MPDU in which an A-MSDU is carried in + * a QoS Data frame for which no block ack agreement exists. + */ +#define WMI_HECAP_MAC_AMSDUINAMPDU_GET_D3(he_cap2) WMI_GET_BITS(he_cap2, 6, 1) +#define WMI_HECAP_MAC_AMSDUINAMPDU_SET_D3(he_cap2, value) WMI_SET_BITS(he_cap2, 6, 1, value) + +/* Indicates the number of TIDs of QoS Data frames that an HE STA can transmit in a multi-TID AMPDU */ +#define WMI_HECAP_MAC_MTID_TX_GET_D3(he_cap2) WMI_GET_BITS(he_cap2, 7, 3) +#define WMI_HECAP_MAC_MTID_TX_SET_D3(he_cap2, value) WMI_SET_BITS(he_cap2, 7, 3, value) + +/* Indicates whether an HE STA supports an HE subchannel selective transmission operation */ +#define WMI_HECAP_MAC_SUBCHANSELTX_GET_D3(he_cap2) WMI_GET_BITS(he_cap2, 10, 1) +#define WMI_HECAP_MAC_SUBCHANSELTX_SET_D3(he_cap2, value) WMI_SET_BITS(he_cap2, 10, 1, value) + +/* Indicates support by a STA to receive a TRS Control subfield or a Trigger frame with a User Info + * field addressed to the STA with the RU Allocation subfield of the TRS Control subfield or the User + * Info field indicating 2x996-tone. + */ +#define WMI_HECAP_MAC_UL2X996RU_GET_D3(he_cap2) WMI_GET_BITS(he_cap2, 11, 1) +#define WMI_HECAP_MAC_UL2X996RU_SET_D3(he_cap2, value) WMI_SET_BITS(he_cap2, 11, 1, value) + +/* Indicates whether an AP supports interpretation of the UL MU Data Disable subfield of the OM Control subfield */ +#define WMI_HECAP_MAC_OMCULMUDDIS_GET_D3(he_cap2) WMI_GET_BITS(he_cap2, 12, 1) +#define WMI_HECAP_MAC_OMCULMUDDIS_SET_D3(he_cap2, value) WMI_SET_BITS(he_cap2, 12, 1, value) + +/* + * The following conditionally-defined macros can be used in systems + * which only support either 802.11ax draft 2 or 802.11ax draft 3, + * but not both, and which make this D2 vs. D3 selection at build time. + */ +#ifdef SUPPORT_11AX_D3 + #define WMI_HEOPS_COLOR_GET WMI_HEOPS_COLOR_GET_D3 + #define WMI_HEOPS_COLOR_SET WMI_HEOPS_COLOR_SET_D3 + #define WMI_HEOPS_DEFPE_GET WMI_HEOPS_DEFPE_GET_D3 + #define WMI_HEOPS_DEFPE_SET WMI_HEOPS_DEFPE_SET_D3 + #define WMI_HEOPS_TWT_REQUIRED_GET WMI_HEOPS_TWT_REQUIRED_GET_D3 + #define WMI_HEOPS_TWT_REQUIRED_SET WMI_HEOPS_TWT_REQUIRED_SET_D3 + #define WMI_HEOPS_TWT_GET WMI_HEOPS_TWT_REQUIRED_GET_D3 /* DEPRECATED, use WMI_HEOPS_TWT_REQUIRED_GET */ + #define WMI_HEOPS_TWT_SET WMI_HEOPS_TWT_REQUIRED_SET_D3 /* DEPRECATED, use WMI_HEOPS_TWT_REQUIRED_SET */ + #define WMI_HEOPS_RTSTHLD_GET WMI_HEOPS_RTSTHLD_GET_D3 + #define WMI_HEOPS_RTSTHLD_SET WMI_HEOPS_RTSTHLD_SET_D3 + #define WMI_HEOPS_PARTBSSCOLOR_GET WMI_HEOPS_PARTBSSCOLOR_GET_D3 + #define WMI_HEOPS_PARTBSSCOLOR_SET WMI_HEOPS_PARTBSSCOLOR_SET_D3 + #define WMI_HEOPS_COLOCBSS_GET WMI_HEOPS_COLOCBSS_GET_D3 + #define WMI_HEOPS_COLOCBSS_SET WMI_HEOPS_COLOCBSS_SET_D3 + #define WMI_HEOPS_VHTOPSPRSNT_GET WMI_HEOPS_VHTOPSPRSNT_GET_D3 + #define WMI_HEOPS_VHTOPSPRSNT_SET WMI_HEOPS_VHTOPSPRSNT_SET_D3 + #define WMI_HEOPS_ERSUDIS_GET WMI_HEOPS_ERSUDIS_GET_D3 + #define WMI_HEOPS_ERSUDIS_SET WMI_HEOPS_ERSUDIS_SET_D3 + #define WMI_HEOPS_BSSCOLORDISABLE_GET WMI_HEOPS_BSSCOLORDISABLE_GET_D3 + #define WMI_HEOPS_BSSCOLORDISABLE_SET WMI_HEOPS_BSSCOLORDISABLE_SET_D3 + #define WMI_HEOPS_TXBSSID_GET(he_ops) (0) /* DEPRECATED - DO NOT USE */ + #define WMI_HEOPS_TXBSSID_SET(he_ops, value) /* DEPRECATED - DO NOT USE */ + + #define WMI_HECAP_PHY_CBW_GET WMI_HECAP_PHY_CBW_GET_D3 + #define WMI_HECAP_PHY_CBW_SET WMI_HECAP_PHY_CBW_SET_D3 + #define WMI_HECAP_PHY_PREAMBLEPUNCRX_GET WMI_HECAP_PHY_PREAMBLEPUNCRX_GET_D3 + #define WMI_HECAP_PHY_PREAMBLEPUNCRX_SET WMI_HECAP_PHY_PREAMBLEPUNCRX_SET_D3 + #define WMI_HECAP_PHY_COD_GET WMI_HECAP_PHY_COD_GET_D3 + #define WMI_HECAP_PHY_COD_SET WMI_HECAP_PHY_COD_SET_D3 + #define WMI_HECAP_PHY_LDPC_GET WMI_HECAP_PHY_LDPC_GET_D3 + #define WMI_HECAP_PHY_LDPC_SET WMI_HECAP_PHY_LDPC_SET_D3 + #define WMI_HECAP_PHY_TXLDPC_GET WMI_HECAP_PHY_LDPC_GET /* Deprecated use WMI_HECAP_PHY_LDPC */ + #define WMI_HECAP_PHY_TXLDPC_SET WMI_HECAP_PHY_LDPC_SET /* Deprecated use WMI_HECAP_PHY_LDPC */ + #define WMI_HECAP_PHY_RXLDPC_GET WMI_HECAP_PHY_LDPC_GET /* Deprecated use WMI_HECAP_PHY_LDPC */ + #define WMI_HECAP_PHY_RXLDPC_SET WMI_HECAP_PHY_LDPC_SET /* Deprecated use WMI_HECAP_PHY_LDPC */ + #define WMI_HECAP_PHY_LTFGIFORHE_GET WMI_HECAP_PHY_LTFGIFORHE_GET_D3 + #define WMI_HECAP_PHY_LTFGIFORHE_SET WMI_HECAP_PHY_LTFGIFORHE_SET_D3 + #define WMI_HECAP_PHY_MIDAMBLETXRXMAXNSTS_GET WMI_HECAP_PHY_MIDAMBLETXRXMAXNSTS_GET_D3 + #define WMI_HECAP_PHY_MIDAMBLETXRXMAXNSTS_SET WMI_HECAP_PHY_MIDAMBLETXRXMAXNSTS_SET_D3 + #define WMI_HECAP_PHY_LTFGIFORNDP_GET WMI_HECAP_PHY_LTFGIFORNDP_GET_D3 + #define WMI_HECAP_PHY_LTFGIFORNDP_SET WMI_HECAP_PHY_LTFGIFORNDP_SET_D3 + #define WMI_HECAP_PHY_TXSTBC_GET WMI_HECAP_PHY_TXSTBC_GET_D3 + #define WMI_HECAP_PHY_TXSTBC_SET WMI_HECAP_PHY_TXSTBC_SET_D3 + #define WMI_HECAP_PHY_RXSTBC_GET WMI_HECAP_PHY_RXSTBC_GET_D3 + #define WMI_HECAP_PHY_RXSTBC_SET WMI_HECAP_PHY_RXSTBC_SET_D3 + #define WMI_HECAP_PHY_TXDOPPLER WMI_HECAP_PHY_TXDOPPLER_GET_D3 + #define WMI_HECAP_PHY_TXDOPPLER_SET WMI_HECAP_PHY_TXDOPPLER_SET_D3 + #define WMI_HECAP_PHY_RXDOPPLER_GET WMI_HECAP_PHY_RXDOPPLER_GET_D3 + #define WMI_HECAP_PHY_RXDOPPLER_SET WMI_HECAP_PHY_RXDOPPLER_SET_D3 + #define WMI_HECAP_PHY_UL_MU_MIMO_GET WMI_HECAP_PHY_UL_MU_MIMO_GET_D3 + #define WMI_HECAP_PHY_UL_MU_MIMO_SET WMI_HECAP_PHY_UL_MU_MIMO_SET_D3 + #define WMI_HECAP_PHY_ULMUMIMOOFDMA_GET WMI_HECAP_PHY_ULMUMIMOOFDMA_GET_D3 + #define WMI_HECAP_PHY_ULMUMIMOOFDMA_SET WMI_HECAP_PHY_ULMUMIMOOFDMA_SET_D3 + #define WMI_HECAP_PHY_DCMTX_GET WMI_HECAP_PHY_DCMTX_GET_D3 + #define WMI_HECAP_PHY_DCMTX_SET WMI_HECAP_PHY_DCMTX_SET_D3 + #define WMI_HECAP_PHY_DCMRX_GET WMI_HECAP_PHY_DCMRX_GET_D3 + #define WMI_HECAP_PHY_DCMRX_SET WMI_HECAP_PHY_DCMRX_SET_D3 + /* DEPRECATED - use WMI_HECAP_PHY_DCMRX or WMI_HECAP_PHY_DCMTX */ + #define WMI_HECAP_PHY_DCM_GET WMI_HECAP_PHY_DCMRX_GET_D3 + #define WMI_HECAP_PHY_DCM_SET WMI_HECAP_PHY_DCMRX_SET_D3 + #define WMI_HECAP_PHY_ULHEMU_GET WMI_HECAP_PHY_ULHEMU_GET_D3 + #define WMI_HECAP_PHY_ULHEMU_SET WMI_HECAP_PHY_ULHEMU_SET_D3 + #define WMI_HECAP_PHY_SUBFMR_GET WMI_HECAP_PHY_SUBFMR_GET_D3 + #define WMI_HECAP_PHY_SUBFMR_SET WMI_HECAP_PHY_SUBFMR_SET_D3 + #define WMI_HECAP_PHY_SUBFME_GET WMI_HECAP_PHY_SUBFME_GET_D3 + #define WMI_HECAP_PHY_SUBFME_SET WMI_HECAP_PHY_SUBFME_SET_D3 + #define WMI_HECAP_PHY_MUBFMR_GET WMI_HECAP_PHY_MUBFMR_GET_D3 + #define WMI_HECAP_PHY_MUBFMR_SET WMI_HECAP_PHY_MUBFMR_SET_D3 + #define WMI_HECAP_PHY_BFMESTSLT80MHZ_GET WMI_HECAP_PHY_BFMESTSLT80MHZ_GET_D3 + #define WMI_HECAP_PHY_BFMESTSLT80MHZ_SET WMI_HECAP_PHY_BFMESTSLT80MHZ_SET_D3 + #define WMI_HECAP_PHY_BFMESTSGT80MHZ_GET WMI_HECAP_PHY_BFMESTSGT80MHZ_GET_D3 + #define WMI_HECAP_PHY_BFMESTSGT80MHZ_SET WMI_HECAP_PHY_BFMESTSGT80MHZ_SET_D3 + #define WMI_HECAP_PHY_NSTSLT80MHZ_GET WMI_HECAP_PHY_BFMESTSLT80MHZ_GET_D3 + #define WMI_HECAP_PHY_NSTSLT80MHZ_SET WMI_HECAP_PHY_BFMESTSLT80MHZ_SET_D3 + #define WMI_HECAP_PHY_NSTSGT80MHZ_GET WMI_HECAP_PHY_BFMESTSGT80MHZ_GET_D3 + #define WMI_HECAP_PHY_NSTSGT80MHZ_SET WMI_HECAP_PHY_BFMESTSGT80MHZ_SET_D3 + #define WMI_HECAP_PHY_NUMSOUNDLT80MHZ_GET WMI_HECAP_PHY_NUMSOUNDLT80MHZ_GET_D3 + #define WMI_HECAP_PHY_NUMSOUNDLT80MHZ_SET WMI_HECAP_PHY_NUMSOUNDLT80MHZ_SET_D3 + #define WMI_HECAP_PHY_NUMSOUNDGT80MHZ_GET WMI_HECAP_PHY_NUMSOUNDGT80MHZ_GET_D3 + #define WMI_HECAP_PHY_NUMSOUNDGT80MHZ_SET WMI_HECAP_PHY_NUMSOUNDGT80MHZ_SET_D3 + #define WMI_HECAP_PHY_NG16SUFEEDBACKLT80_GET WMI_HECAP_PHY_NG16SUFEEDBACKLT80_GET_D3 + #define WMI_HECAP_PHY_NG16SUFEEDBACKLT80_SET WMI_HECAP_PHY_NG16SUFEEDBACKLT80_SET_D3 + #define WMI_HECAP_PHY_NG16MUFEEDBACKGT80_GET WMI_HECAP_PHY_NG16MUFEEDBACKGT80_GET_D3 + #define WMI_HECAP_PHY_NG16MUFEEDBACKGT80_SET WMI_HECAP_PHY_NG16MUFEEDBACKGT80_SET_D3 + #define WMI_HECAP_PHY_CODBK42SU_GET WMI_HECAP_PHY_CODBK42SU_GET_D3 + #define WMI_HECAP_PHY_CODBK42SU_SET WMI_HECAP_PHY_CODBK42SU_SET_D3 + #define WMI_HECAP_PHY_CODBK75MU_GET WMI_HECAP_PHY_CODBK75MU_GET_D3 + #define WMI_HECAP_PHY_CODBK75MU_SET WMI_HECAP_PHY_CODBK75MU_SET_D3 + #define WMI_HECAP_PHY_BFFEEDBACKTRIG_GET WMI_HECAP_PHY_BFFEEDBACKTRIG_GET_D3 + #define WMI_HECAP_PHY_BFFEEDBACKTRIG_SET WMI_HECAP_PHY_BFFEEDBACKTRIG_SET_D3 + #define WMI_HECAP_PHY_HEERSU_GET WMI_HECAP_PHY_HEERSU_GET_D3 + #define WMI_HECAP_PHY_HEERSU_SET WMI_HECAP_PHY_HEERSU_SET_D3 + #define WMI_HECAP_PHY_DLMUMIMOPARTIALBW_GET WMI_HECAP_PHY_DLMUMIMOPARTIALBW_GET_D3 + #define WMI_HECAP_PHY_DLMUMIMOPARTIALBW_SET WMI_HECAP_PHY_DLMUMIMOPARTIALBW_SET_D3 + #define WMI_HECAP_PHY_PETHRESPRESENT_GET WMI_HECAP_PHY_PETHRESPRESENT_GET_D3 + #define WMI_HECAP_PHY_PETHRESPRESENT_SET WMI_HECAP_PHY_PETHRESPRESENT_SET_D3 + #define WMI_HECAP_PHY_SRPSPRESENT_GET WMI_HECAP_PHY_SRPSPRESENT_GET_D3 + #define WMI_HECAP_PHY_SRPPRESENT_SET WMI_HECAP_PHY_SRPPRESENT_SET_D3 + #define WMI_HECAP_PHY_PWRBOOSTAR_GET WMI_HECAP_PHY_PWRBOOSTAR_GET_D3 + #define WMI_HECAP_PHY_PWRBOOSTAR_SET WMI_HECAP_PHY_PWRBOOSTAR_SET_D3 + #define WMI_HECAP_PHY_4XLTFAND800NSECSGI_GET WMI_HECAP_PHY_4XLTFAND800NSECSGI_GET_D3 + #define WMI_HECAP_PHY_4XLTFAND800NSECSGI_SET WMI_HECAP_PHY_4XLTFAND800NSECSGI_SET_D3 + #define WMI_HECAP_PHY_MAXNC_GET WMI_HECAP_PHY_MAXNC_GET_D3 + #define WMI_HECAP_PHY_MAXNC_SET WMI_HECAP_PHY_MAXNC_SET_D3 + #define WMI_HECAP_PHY_STBCTXGT80_GET WMI_HECAP_PHY_STBCTXGT80_GET_D3 + #define WMI_HECAP_PHY_STBCTXGT80_SET WMI_HECAP_PHY_STBCTXGT80_SET_D3 + #define WMI_HECAP_PHY_STBCRXGT80_GET WMI_HECAP_PHY_STBCRXGT80_GET_D3 + #define WMI_HECAP_PHY_STBCRXGT80_SET WMI_HECAP_PHY_STBCRXGT80_SET_D3 + #define WMI_HECAP_PHY_ERSU4X800NSECGI_GET WMI_HECAP_PHY_ERSU4X800NSECGI_GET_D3 + #define WMI_HECAP_PHY_ERSU4X800NSECGI_SET WMI_HECAP_PHY_ERSU4X800NSECGI_SET_D3 + #define WMI_HECAP_PHY_HEPPDU20IN40MHZ2G_GET WMI_HECAP_PHY_HEPPDU20IN40MHZ2G_GET_D3 + #define WMI_HECAP_PHY_HEPPDU20IN40MHZ2G_SET WMI_HECAP_PHY_HEPPDU20IN40MHZ2G_SET_D3 + #define WMI_HECAP_PHY_HEPPDU20IN160OR80P80MHZ_GET WMI_HECAP_PHY_HEPPDU20IN160OR80P80MHZ_GET_D3 + #define WMI_HECAP_PHY_HEPPDU20IN160OR80P80MHZ_SET WMI_HECAP_PHY_HEPPDU20IN160OR80P80MHZ_SET_D3 + #define WMI_HECAP_PHY_HEPPDU80IN160OR80P80MHZ_GET WMI_HECAP_PHY_HEPPDU80IN160OR80P80MHZ_GET_D3 + #define WMI_HECAP_PHY_HEPPDU80IN160OR80P80MHZ_SET WMI_HECAP_PHY_HEPPDU80IN160OR80P80MHZ_SET_D3 + #define WMI_HECAP_PHY_ERSU1X800NSECGI_GET WMI_HECAP_PHY_ERSU1X800NSECGI_GET_D3 + #define WMI_HECAP_PHY_ERSU1X800NSECGI_SET WMI_HECAP_PHY_ERSU1X800NSECGI_SET_D3 + #define WMI_HECAP_PHY_MIDAMBLETXRX2XAND1XHELTF_GET WMI_HECAP_PHY_MIDAMBLETXRX2XAND1XHELTF_GET_D3 + #define WMI_HECAP_PHY_MIDAMBLETXRX2XAND1XHELTF_SET WMI_HECAP_PHY_MIDAMBLETXRX2XAND1XHELTF_SET_D3 + #define WMI_HECAP_PHY_MIDAMBLERX2XAND1XHELTF_GET WMI_HECAP_PHY_MIDAMBLETXRX2XAND1XHELTF_GET /* DEPRECATED */ + #define WMI_HECAP_PHY_MIDAMBLERX2XAND1XHELTF_SET WMI_HECAP_PHY_MIDAMBLETXRX2XAND1XHELTF_SET /* DEPRECATED */ + #define WMI_HECAP_PHY_DCMMAXBW_GET WMI_HECAP_PHY_DCMMAXBW_GET_D3 + #define WMI_HECAP_PHY_DCMMAXBW_SET WMI_HECAP_PHY_DCMMAXBW_SET_D3 + #define WMI_HECAP_PHY_LNG16SIGBSYMBSUPRT_GET WMI_HECAP_PHY_LNG16SIGBSYMBSUPRT_GET_D3 + #define WMI_HECAP_PHY_LNG16SIGBSYMBSUPRT_SET WMI_HECAP_PHY_LNG16SIGBSYMBSUPRT_SET_D3 + #define WMI_HECAP_PHY_NONTRIGCQIFEEDBK_GET WMI_HECAP_PHY_NONTRIGCQIFEEDBK_GET_D3 + #define WMI_HECAP_PHY_NONTRIGCQIFEEDBK_SET WMI_HECAP_PHY_NONTRIGCQIFEEDBK_SET_D3 + #define WMI_HECAP_PHY_TX1024QAM242RUSUPRT_GET WMI_HECAP_PHY_TX1024QAM242RUSUPRT_GET_D3 + #define WMI_HECAP_PHY_TX1024QAM242RUSUPRT_SET WMI_HECAP_PHY_TX1024QAM242RUSUPRT_SET_D3 + #define WMI_HECAP_PHY_RX1024QAM242RUSUPRT_GET WMI_HECAP_PHY_RX1024QAM242RUSUPRT_GET_D3 + #define WMI_HECAP_PHY_RX1024QAM242RUSUPRT_SET WMI_HECAP_PHY_RX1024QAM242RUSUPRT_SET_D3 + #define WMI_HECAP_PHY_RXFULBWSUWCMPRSSIGB_GET WMI_HECAP_PHY_RXFULBWSUWCMPRSSIGB_GET_D3 + #define WMI_HECAP_PHY_RXFULBWSUWCMPRSSIGB_SET WMI_HECAP_PHY_RXFULBWSUWCMPRSSIGB_SET_D3 + #define WMI_HECAP_PHY_RXFULBWSUWNONCMPRSSIGB_GET WMI_HECAP_PHY_RXFULBWSUWNONCMPRSSIGB_GET_D3 + #define WMI_HECAP_PHY_RXFULBWSUWNONCMPRSSIGB_SET WMI_HECAP_PHY_RXFULBWSUWNONCMPRSSIGB_SET_D3 + #define WMI_HECAP_PHY_DB_GET(he_phy_cap) (0) /* DEPRECATED - DO NOT USE */ + #define WMI_HECAP_PHY_DB_SET(he_phy_cap, value) /* DEPRECATED - DO NOT USE */ + #define WMI_HECAP_MAC_HECTRL_GET WMI_HECAP_MAC_HECTRL_GET_D3 + #define WMI_HECAP_MAC_HECTRL_SET WMI_HECAP_MAC_HECTRL_SET_D3 + #define WMI_HECAP_MAC_TWTREQ_GET WMI_HECAP_MAC_TWTREQ_GET_D3 + #define WMI_HECAP_MAC_TWTREQ_SET WMI_HECAP_MAC_TWTREQ_SET_D3 + #define WMI_HECAP_MAC_TWTRSP_GET WMI_HECAP_MAC_TWTRSP_GET_D3 + #define WMI_HECAP_MAC_TWTRSP_SET WMI_HECAP_MAC_TWTRSP_SET_D3 + #define WMI_HECAP_MAC_HEFRAG_GET WMI_HECAP_MAC_HEFRAG_GET_D3 + #define WMI_HECAP_MAC_HEFRAG_SET WMI_HECAP_MAC_HEFRAG_SET_D3 + #define WMI_HECAP_MAC_MAXFRAGMSDU_GET WMI_HECAP_MAC_MAXFRAGMSDU_GET_D3 + #define WMI_HECAP_MAC_MAXFRAGMSDU_SET WMI_HECAP_MAC_MAXFRAGMSDU_SET_D3 + #define WMI_HECAP_MAC_MINFRAGSZ_GET WMI_HECAP_MAC_MINFRAGSZ_GET_D3 + #define WMI_HECAP_MAC_MINFRAGSZ_SET WMI_HECAP_MAC_MINFRAGSZ_SET_D3 + #define WMI_HECAP_MAC_TRIGPADDUR_GET WMI_HECAP_MAC_TRIGPADDUR_GET_D3 + #define WMI_HECAP_MAC_TRIGPADDUR_SET WMI_HECAP_MAC_TRIGPADDUR_SET_D3 + #define WMI_HECAP_MAC_MTID_RX_GET WMI_HECAP_MAC_MTID_RX_GET_D3 + #define WMI_HECAP_MAC_MTID_RX_SET WMI_HECAP_MAC_MTID_RX_SET_D3 + #define WMI_HECAP_MAC_HELINK_ADPT_GET WMI_HECAP_MAC_HELINK_ADPT_GET_D3 + #define WMI_HECAP_MAC_HELINK_ADPT_SET WMI_HECAP_MAC_HELINK_ADPT_SET_D3 + #define WMI_HECAP_MAC_AACK_GET WMI_HECAP_MAC_AACK_GET_D3 + #define WMI_HECAP_MAC_AACK_SET WMI_HECAP_MAC_AACK_SET_D3 + #define WMI_HECAP_MAC_TRS_GET WMI_HECAP_MAC_TRS_GET_D3 + #define WMI_HECAP_MAC_TRS_SET WMI_HECAP_MAC_TRS_SET_D3 + #define WMI_HECAP_MAC_ULMURSP_GET(he_cap) (0) /* DEPRECATED, DO NOT USE */ + #define WMI_HECAP_MAC_ULMURSP_SET(he_cap, value) /* DEPRECATED, DO NOT USE */ + #define WMI_HECAP_MAC_BSR_GET WMI_HECAP_MAC_BSR_GET_D3 + #define WMI_HECAP_MAC_BSR_SET WMI_HECAP_MAC_BSR_SET_D3 + #define WMI_HECAP_MAC_BCSTTWT_GET WMI_HECAP_MAC_BCSTTWT_GET_D3 + #define WMI_HECAP_MAC_BCSTTWT_SET WMI_HECAP_MAC_BCSTTWT_SET_D3 + #define WMI_HECAP_MAC_32BITBA_GET WMI_HECAP_MAC_32BITBA_GET_D3 + #define WMI_HECAP_MAC_32BITBA_SET WMI_HECAP_MAC_32BITBA_SET_D3 + #define WMI_HECAP_MAC_MUCASCADE_GET WMI_HECAP_MAC_MUCASCADE_GET_D3 + #define WMI_HECAP_MAC_MUCASCADE_SET WMI_HECAP_MAC_MUCASCADE_SET_D3 + #define WMI_HECAP_MAC_ACKMTIDAMPDU_GET WMI_HECAP_MAC_ACKMTIDAMPDU_GET_D3 + #define WMI_HECAP_MAC_ACKMTIDAMPDU_SET WMI_HECAP_MAC_ACKMTIDAMPDU_SET_D3 + #define WMI_HECAP_MAC_GROUPMSTABA_GET(he_cap) (0) /* DEPRECATED, DO NOT USE */ + #define WMI_HECAP_MAC_GROUPMSTABA_SET(he_cap, value) /* DEPRECATED, DO NOT USE */ + #define WMI_HECAP_MAC_OMI_GET WMI_HECAP_MAC_OMI_GET_D3 + #define WMI_HECAP_MAC_OMI_SET WMI_HECAP_MAC_OMI_SET_D3 + #define WMI_HECAP_MAC_OFDMARA_GET WMI_HECAP_MAC_OFDMARA_GET_D3 + #define WMI_HECAP_MAC_OFDMARA_SET WMI_HECAP_MAC_OFDMARA_SET_D3 + #define WMI_HECAP_MAC_MAXAMPDULEN_EXP_GET WMI_HECAP_MAC_MAXAMPDULEN_EXP_GET_D3 + #define WMI_HECAP_MAC_MAXAMPDULEN_EXP_SET WMI_HECAP_MAC_MAXAMPDULEN_EXP_SET_D3 + #define WMI_HECAP_MAC_AMSDUFRAG_GET WMI_HECAP_MAC_AMSDUFRAG_GET_D3 + #define WMI_HECAP_MAC_AMSDUFRAG_SET WMI_HECAP_MAC_AMSDUFRAG_SET_D3 + #define WMI_HECAP_MAC_FLEXTWT_GET WMI_HECAP_MAC_FLEXTWT_GET_D3 + #define WMI_HECAP_MAC_FLEXTWT_SET WMI_HECAP_MAC_FLEXTWT_SET_D3 + #define WMI_HECAP_MAC_MBSS_GET WMI_HECAP_MAC_MBSS_GET_D3 + #define WMI_HECAP_MAC_MBSS_SET WMI_HECAP_MAC_MBSS_SET_D3 + #define WMI_HECAP_MAC_BSRPAMPDU_GET WMI_HECAP_MAC_BSRPAMPDU_GET_D3 + #define WMI_HECAP_MAC_BSRPAMPDU_SET WMI_HECAP_MAC_BSRPAMPDU_SET_D3 + #define WMI_HECAP_MAC_QTP_GET WMI_HECAP_MAC_QTP_GET_D3 + #define WMI_HECAP_MAC_QTP_SET WMI_HECAP_MAC_QTP_SET_D3 + #define WMI_HECAP_MAC_ABQR_GET WMI_HECAP_MAC_ABQR_GET_D3 + #define WMI_HECAP_MAC_ABQR_SET WMI_HECAP_MAC_ABQR_SET_D3 + #define WMI_HECAP_MAC_SRPRESP_GET WMI_HECAP_MAC_SRPRESP_GET_D3 + #define WMI_HECAP_MAC_SRPRESP_SET WMI_HECAP_MAC_SRPRESP_SET_D3 + #define WMI_HECAP_MAC_SRRESP_GET(he_cap2) (0) /* DEPRECATED, DO NOT USE */ + #define WMI_HECAP_MAC_SRRESP_SET(he_cap2, value) /* DEPRECATED, DO NOT USE */ + #define WMI_HECAP_MAC_NDPFDBKRPT_GET WMI_HECAP_MAC_NDPFDBKRPT_GET_D3 + #define WMI_HECAP_MAC_NDPFDBKRPT_SET WMI_HECAP_MAC_NDPFDBKRPT_SET_D3 + #define WMI_HECAP_MAC_OPS_GET WMI_HECAP_MAC_OPS_GET_D3 + #define WMI_HECAP_MAC_OPS_SET WMI_HECAP_MAC_OPS_SET_D3 + #define WMI_HECAP_MAC_AMSDUINAMPDU_GET WMI_HECAP_MAC_AMSDUINAMPDU_GET_D3 + #define WMI_HECAP_MAC_AMSDUINAMPDU_SET WMI_HECAP_MAC_AMSDUINAMPDU_SET_D3 + #define WMI_HECAP_MAC_MTID_TX_GET WMI_HECAP_MAC_MTID_TX_GET_D3 + #define WMI_HECAP_MAC_MTID_TX_SET WMI_HECAP_MAC_MTID_TX_SET_D3 + #define WMI_HECAP_MAC_SUBCHANSELTX_GET WMI_HECAP_MAC_SUBCHANSELTX_GET_D3 + #define WMI_HECAP_MAC_SUBCHANSELTX_SET WMI_HECAP_MAC_SUBCHANSELTX_SET_D3 + #define WMI_HECAP_MAC_UL2X996RU_GET WMI_HECAP_MAC_UL2X996RU_GET_D3 + #define WMI_HECAP_MAC_UL2X996RU_SET WMI_HECAP_MAC_UL2X996RU_SET_D3 + #define WMI_HECAP_MAC_OMCULMUDDIS_GET WMI_HECAP_MAC_OMCULMUDDIS_GET_D3 + #define WMI_HECAP_MAC_OMCULMUDDIS_SET WMI_HECAP_MAC_OMCULMUDDIS_SET_D3 + #define WMI_HECAP_MAC_HELKAD_GET(he_cap) (0) /* DEPRECATED, DO NOT USE */ + #define WMI_HECAP_MAC_HELKAD_SET(he_cap, value) /* DEPRECATED, DO NOT USE */ + #define WMI_HECAP_PHY_MIDAMBLERXMAXNSTS_GET WMI_HECAP_PHY_MIDAMBLETXRXMAXNSTS_GET_D3 /* DEPRECATED - DO NOT USE */ + #define WMI_HECAP_PHY_MIDAMBLERXMAXNSTS_SET WMI_HECAP_PHY_MIDAMBLETXRXMAXNSTS_SET_D3 /* DEPRECATED - DO NOT USE */ +#else /* SUPPORT_11AX_D3 vs. D2 */ + /* D2 and D2- */ + #define WMI_HEOPS_COLOR_GET WMI_HEOPS_COLOR_GET_D2 + #define WMI_HEOPS_COLOR_SET WMI_HEOPS_COLOR_SET_D2 + #define WMI_HEOPS_DEFPE_GET WMI_HEOPS_DEFPE_GET_D2 + #define WMI_HEOPS_DEFPE_SET WMI_HEOPS_DEFPE_SET_D2 + #define WMI_HEOPS_TWT_REQUIRED_GET WMI_HEOPS_TWT_REQUIRED_GET_D2 + #define WMI_HEOPS_TWT_REQUIRED_SET WMI_HEOPS_TWT_REQUIRED_SET_D2 + #define WMI_HEOPS_TWT_GET WMI_HEOPS_TWT_GET_D2 /* Depricated */ + #define WMI_HEOPS_TWT_SET WMI_HEOPS_TWT_SET_D2 /* Depricated */ + #define WMI_HEOPS_RTSTHLD_GET WMI_HEOPS_RTSTHLD_GET_D2 + #define WMI_HEOPS_RTSTHLD_SET WMI_HEOPS_RTSTHLD_SET_D2 + #define WMI_HEOPS_PARTBSSCOLOR_GET WMI_HEOPS_PARTBSSCOLOR_GET_D2 + #define WMI_HEOPS_PARTBSSCOLOR_SET WMI_HEOPS_PARTBSSCOLOR_SET_D2 + #define WMI_HEOPS_MAXBSSID_GET WMI_HEOPS_MAXBSSID_GET_D2 + #define WMI_HEOPS_MAXBSSID_SET WMI_HEOPS_MAXBSSID_SET_D2 + #define WMI_HEOPS_TXBSSID_GET WMI_HEOPS_TXBSSID_GET_D2 + #define WMI_HEOPS_TXBSSID_SET WMI_HEOPS_TXBSSID_SET_D2 + #define WMI_HEOPS_BSSCOLORDISABLE_GET WMI_HEOPS_BSSCOLORDISABLE_GET_D2 + #define WMI_HEOPS_BSSCOLORDISABLE_SET WMI_HEOPS_BSSCOLORDISABLE_SET_D2 + #define WMI_HEOPS_DUALBEACON_GET WMI_HEOPS_DUALBEACON_GET_D2 + #define WMI_HEOPS_DUALBEACON_SET WMI_HEOPS_DUALBEACON_SET_D2 + #define WMI_HECAP_PHY_DB_GET WMI_HECAP_PHY_DB_GET_D2 + #define WMI_HECAP_PHY_DB_SET WMI_HECAP_PHY_DB_SET_D2 + #define WMI_HECAP_PHY_CBW_GET WMI_HECAP_PHY_CBW_GET_D2 + #define WMI_HECAP_PHY_CBW_SET WMI_HECAP_PHY_CBW_SET_D2 + #define WMI_HECAP_PHY_PREAMBLEPUNCRX_GET WMI_HECAP_PHY_PREAMBLEPUNCRX_GET_D2 + #define WMI_HECAP_PHY_PREAMBLEPUNCRX_SET WMI_HECAP_PHY_PREAMBLEPUNCRX_SET_D2 + #define WMI_HECAP_PHY_COD_GET WMI_HECAP_PHY_COD_GET_D2 + #define WMI_HECAP_PHY_COD_SET WMI_HECAP_PHY_COD_SET_D2 + #define WMI_HECAP_PHY_LDPC_GET WMI_HECAP_PHY_LDPC_GET_D2 + #define WMI_HECAP_PHY_LDPC_SET WMI_HECAP_PHY_LDPC_SET_D2 + #define WMI_HECAP_PHY_TXLDPC_GET WMI_HECAP_PHY_TXLDPC_GET_D2 + #define WMI_HECAP_PHY_TXLDPC_SET WMI_HECAP_PHY_TXLDPC_SET_D2 + #define WMI_HECAP_PHY_RXLDPC_GET WMI_HECAP_PHY_RXLDPC_GET_D2 + #define WMI_HECAP_PHY_RXLDPC_SET WMI_HECAP_PHY_RXLDPC_SET_D2 + #define WMI_HECAP_PHY_LTFGIFORHE_GET WMI_HECAP_PHY_LTFGIFORHE_GET_D2 + #define WMI_HECAP_PHY_LTFGIFORHE_SET WMI_HECAP_PHY_LTFGIFORHE_SET_D2 + #define WMI_HECAP_PHY_MIDAMBLERXMAXNSTS_GET WMI_HECAP_PHY_MIDAMBLERXMAXNSTS_GET_D2 + #define WMI_HECAP_PHY_MIDAMBLERXMAXNSTS_SET WMI_HECAP_PHY_MIDAMBLERXMAXNSTS_SET_D2 + #define WMI_HECAP_PHY_LTFGIFORNDP_GET WMI_HECAP_PHY_LTFGIFORNDP_GET_D2 + #define WMI_HECAP_PHY_LTFGIFORNDP_SET WMI_HECAP_PHY_LTFGIFORNDP_SET_D2 + #define WMI_HECAP_PHY_TXSTBC_GET WMI_HECAP_PHY_TXSTBC_GET_D2 + #define WMI_HECAP_PHY_TXSTBC_SET WMI_HECAP_PHY_TXSTBC_SET_D2 + #define WMI_HECAP_PHY_RXSTBC_GET WMI_HECAP_PHY_RXSTBC_GET_D2 + #define WMI_HECAP_PHY_RXSTBC_SET WMI_HECAP_PHY_RXSTBC_SET_D2 + #define WMI_HECAP_PHY_TXDOPPLER_GET WMI_HECAP_PHY_TXDOPPLER_GET_D2 + #define WMI_HECAP_PHY_TXDOPPLER_SET WMI_HECAP_PHY_TXDOPPLER_SET_D2 + #define WMI_HECAP_PHY_RXDOPPLER_GET WMI_HECAP_PHY_RXDOPPLER_GET_D2 + #define WMI_HECAP_PHY_RXDOPPLER_SET WMI_HECAP_PHY_RXDOPPLER_SET_D2 + #define WMI_HECAP_PHY_UL_MU_MIMO_GET WMI_HECAP_PHY_UL_MU_MIMO_GET_D2 + #define WMI_HECAP_PHY_UL_MU_MIMO_SET WMI_HECAP_PHY_UL_MU_MIMO_SET_D2 + #define WMI_HECAP_PHY_ULMUMIMOOFDMA_GET WMI_HECAP_PHY_ULMUMIMOOFDMA_GET_D2 + #define WMI_HECAP_PHY_ULMUMIMOOFDMA_SET WMI_HECAP_PHY_ULMUMIMOOFDMA_SET_D2 + #define WMI_HECAP_PHY_DCMTX_GET WMI_HECAP_PHY_DCMTX_GET_D2 + #define WMI_HECAP_PHY_DCMTX_SET WMI_HECAP_PHY_DCMTX_SET_D2 + #define WMI_HECAP_PHY_DCMRX_GET WMI_HECAP_PHY_DCMRX_GET_D2 + #define WMI_HECAP_PHY_DCMRX_SET WMI_HECAP_PHY_DCMRX_SET_D2 + #define WMI_HECAP_PHY_ULHEMU_GET WMI_HECAP_PHY_ULHEMU_GET_D2 + #define WMI_HECAP_PHY_ULHEMU_SET WMI_HECAP_PHY_ULHEMU_SET_D2 + #define WMI_HECAP_PHY_SUBFMR_GET WMI_HECAP_PHY_SUBFMR_GET_D2 + #define WMI_HECAP_PHY_SUBFMR_SET WMI_HECAP_PHY_SUBFMR_SET_D2 + #define WMI_HECAP_PHY_SUBFME_GET WMI_HECAP_PHY_SUBFME_GET_D2 + #define WMI_HECAP_PHY_SUBFME_SET WMI_HECAP_PHY_SUBFME_SET_D2 + #define WMI_HECAP_PHY_MUBFMR_GET WMI_HECAP_PHY_MUBFMR_GET_D2 + #define WMI_HECAP_PHY_MUBFMR_SET WMI_HECAP_PHY_MUBFMR_SET_D2 + #define WMI_HECAP_PHY_BFMESTSLT80MHZ_GET WMI_HECAP_PHY_BFMESTSLT80MHZ_GET_D2 + #define WMI_HECAP_PHY_BFMESTSLT80MHZ_SET WMI_HECAP_PHY_BFMESTSLT80MHZ_SET_D2 + #define WMI_HECAP_PHY_BFMESTSGT80MHZ_GET WMI_HECAP_PHY_BFMESTSGT80MHZ_GET_D2 + #define WMI_HECAP_PHY_BFMESTSGT80MHZ_SET WMI_HECAP_PHY_BFMESTSGT80MHZ_SET_D2 + #define WMI_HECAP_PHY_NUMSOUNDLT80MHZ_GET WMI_HECAP_PHY_NUMSOUNDLT80MHZ_GET_D2 + #define WMI_HECAP_PHY_NUMSOUNDLT80MHZ_SET WMI_HECAP_PHY_NUMSOUNDLT80MHZ_SET_D2 + #define WMI_HECAP_PHY_NUMSOUNDGT80MHZ_GET WMI_HECAP_PHY_NUMSOUNDGT80MHZ_GET_D2 + #define WMI_HECAP_PHY_NUMSOUNDGT80MHZ_SET WMI_HECAP_PHY_NUMSOUNDGT80MHZ_SET_D2 + #define WMI_HECAP_PHY_NG16SUFEEDBACKLT80_GET WMI_HECAP_PHY_NG16SUFEEDBACKLT80_GET_D2 + #define WMI_HECAP_PHY_NG16SUFEEDBACKLT80_SET WMI_HECAP_PHY_NG16SUFEEDBACKLT80_SET_D2 + #define WMI_HECAP_PHY_NG16MUFEEDBACKGT80_GET WMI_HECAP_PHY_NG16MUFEEDBACKGT80_GET_D2 + #define WMI_HECAP_PHY_NG16MUFEEDBACKGT80_SET WMI_HECAP_PHY_NG16MUFEEDBACKGT80_SET_D2 + #define WMI_HECAP_PHY_CODBK42SU_GET WMI_HECAP_PHY_CODBK42SU_GET_D2 + #define WMI_HECAP_PHY_CODBK42SU_SET WMI_HECAP_PHY_CODBK42SU_SET_D2 + #define WMI_HECAP_PHY_CODBK75MU_GET WMI_HECAP_PHY_CODBK75MU_GET_D2 + #define WMI_HECAP_PHY_CODBK75MU_SET WMI_HECAP_PHY_CODBK75MU_SET_D2 + #define WMI_HECAP_PHY_BFFEEDBACKTRIG_GET WMI_HECAP_PHY_BFFEEDBACKTRIG_GET_D2 + #define WMI_HECAP_PHY_BFFEEDBACKTRIG_SET WMI_HECAP_PHY_BFFEEDBACKTRIG_SET_D2 + #define WMI_HECAP_PHY_HEERSU_GET WMI_HECAP_PHY_HEERSU_GET_D2 + #define WMI_HECAP_PHY_HEERSU_SET WMI_HECAP_PHY_HEERSU_SET_D2 + #define WMI_HECAP_PHY_DLMUMIMOPARTIALBW_GET WMI_HECAP_PHY_DLMUMIMOPARTIALBW_GET_D2 + #define WMI_HECAP_PHY_DLMUMIMOPARTIALBW_SET WMI_HECAP_PHY_DLMUMIMOPARTIALBW_SET_D2 + #define WMI_HECAP_PHY_PETHRESPRESENT_GET WMI_HECAP_PHY_PETHRESPRESENT_GET_D2 + #define WMI_HECAP_PHY_PETHRESPRESENT_SET WMI_HECAP_PHY_PETHRESPRESENT_SET_D2 + #define WMI_HECAP_PHY_SRPSPRESENT_GET WMI_HECAP_PHY_SRPSPRESENT_GET_D2 + #define WMI_HECAP_PHY_SRPPRESENT_SET WMI_HECAP_PHY_SRPPRESENT_SET_D2 + #define WMI_HECAP_PHY_PWRBOOSTAR_GET WMI_HECAP_PHY_PWRBOOSTAR_GET_D2 + #define WMI_HECAP_PHY_PWRBOOSTAR_SET WMI_HECAP_PHY_PWRBOOSTAR_SET_D2 + #define WMI_HECAP_PHY_4XLTFAND800NSECSGI_GET WMI_HECAP_PHY_4XLTFAND800NSECSGI_GET_D2 + #define WMI_HECAP_PHY_4XLTFAND800NSECSGI_SET WMI_HECAP_PHY_4XLTFAND800NSECSGI_SET_D2 + #define WMI_HECAP_PHY_MAXNC_GET WMI_HECAP_PHY_MAXNC_GET_D2 + #define WMI_HECAP_PHY_MAXNC_SET WMI_HECAP_PHY_MAXNC_SET_D2 + #define WMI_HECAP_PHY_STBCTXGT80_GET WMI_HECAP_PHY_STBCTXGT80_GET_D2 + #define WMI_HECAP_PHY_STBCTXGT80_SET WMI_HECAP_PHY_STBCTXGT80_SET_D2 + #define WMI_HECAP_PHY_STBCRXGT80_GET WMI_HECAP_PHY_STBCRXGT80_GET_D2 + #define WMI_HECAP_PHY_STBCRXGT80_SET WMI_HECAP_PHY_STBCRXGT80_SET_D2 + #define WMI_HECAP_PHY_ERSU4X800NSECGI_GET WMI_HECAP_PHY_ERSU4X800NSECGI_GET_D2 + #define WMI_HECAP_PHY_ERSU4X800NSECGI_SET WMI_HECAP_PHY_ERSU4X800NSECGI_SET_D2 + #define WMI_HECAP_PHY_HEPPDU20IN40MHZ2G_GET WMI_HECAP_PHY_HEPPDU20IN40MHZ2G_GET_D2 + #define WMI_HECAP_PHY_HEPPDU20IN40MHZ2G_SET WMI_HECAP_PHY_HEPPDU20IN40MHZ2G_SET_D2 + #define WMI_HECAP_PHY_HEPPDU20IN160OR80P80MHZ_GET WMI_HECAP_PHY_HEPPDU20IN160OR80P80MHZ_GET_D2 + #define WMI_HECAP_PHY_HEPPDU20IN160OR80P80MHZ_SET WMI_HECAP_PHY_HEPPDU20IN160OR80P80MHZ_SET_D2 + #define WMI_HECAP_PHY_HEPPDU80IN160OR80P80MHZ_GET WMI_HECAP_PHY_HEPPDU80IN160OR80P80MHZ_GET_D2 + #define WMI_HECAP_PHY_HEPPDU80IN160OR80P80MHZ_SET WMI_HECAP_PHY_HEPPDU80IN160OR80P80MHZ_SET_D2 + #define WMI_HECAP_PHY_ERSU1X800NSECGI_GET WMI_HECAP_PHY_ERSU1X800NSECGI_GET_D2 + #define WMI_HECAP_PHY_ERSU1X800NSECGI_SET WMI_HECAP_PHY_ERSU1X800NSECGI_SET_D2 + #define WMI_HECAP_PHY_MIDAMBLERX2XAND1XHELTF_GET WMI_HECAP_PHY_MIDAMBLERX2XAND1XHELTF_GET_D2 + #define WMI_HECAP_PHY_MIDAMBLERX2XAND1XHELTF_SET WMI_HECAP_PHY_MIDAMBLERX2XAND1XHELTF_SET_D2 + #define WMI_HECAP_MAC_HECTRL_GET WMI_HECAP_MAC_HECTRL_GET_D2 + #define WMI_HECAP_MAC_HECTRL_SET WMI_HECAP_MAC_HECTRL_SET_D2 + #define WMI_HECAP_MAC_TWTREQ_GET WMI_HECAP_MAC_TWTREQ_GET_D2 + #define WMI_HECAP_MAC_TWTREQ_SET WMI_HECAP_MAC_TWTREQ_SET_D2 + #define WMI_HECAP_MAC_TWTRSP_GET WMI_HECAP_MAC_TWTRSP_GET_D2 + #define WMI_HECAP_MAC_TWTRSP_SET WMI_HECAP_MAC_TWTRSP_SET_D2 + #define WMI_HECAP_MAC_HEFRAG_GET WMI_HECAP_MAC_HEFRAG_GET_D2 + #define WMI_HECAP_MAC_HEFRAG_SET WMI_HECAP_MAC_HEFRAG_SET_D2 + #define WMI_HECAP_MAC_MAXFRAGMSDU_GET WMI_HECAP_MAC_MAXFRAGMSDU_GET_D2 + #define WMI_HECAP_MAC_MAXFRAGMSDU_SET WMI_HECAP_MAC_MAXFRAGMSDU_SET_D2 + #define WMI_HECAP_MAC_MINFRAGSZ_GET WMI_HECAP_MAC_MINFRAGSZ_GET_D2 + #define WMI_HECAP_MAC_MINFRAGSZ_SET WMI_HECAP_MAC_MINFRAGSZ_SET_D2 + #define WMI_HECAP_MAC_TRIGPADDUR_GET WMI_HECAP_MAC_TRIGPADDUR_GET_D2 + #define WMI_HECAP_MAC_TRIGPADDUR_SET WMI_HECAP_MAC_TRIGPADDUR_SET_D2 + #define WMI_HECAP_MAC_MTID_GET WMI_HECAP_MAC_MTID_GET_D2 + #define WMI_HECAP_MAC_MTID_SET WMI_HECAP_MAC_MTID_SET_D2 + #define WMI_HECAP_MAC_AMSDUINAMPDU_GET WMI_HECAP_MAC_AMSDUINAMPDU_GET_D2 + #define WMI_HECAP_MAC_AMSDUINAMPDU_SET WMI_HECAP_MAC_AMSDUINAMPDU_SET_D2 + #define WMI_HECAP_MAC_HELKAD_GET WMI_HECAP_MAC_HELKAD_GET_D2 + #define WMI_HECAP_MAC_HELKAD_SET WMI_HECAP_MAC_HELKAD_SET_D2 + #define WMI_HECAP_MAC_AACK_GET WMI_HECAP_MAC_AACK_GET_D2 + #define WMI_HECAP_MAC_AACK_SET WMI_HECAP_MAC_AACK_SET_D2 + #define WMI_HECAP_MAC_ULMURSP_GET WMI_HECAP_MAC_ULMURSP_GET_D2 + #define WMI_HECAP_MAC_ULMURSP_SET WMI_HECAP_MAC_ULMURSP_SET_D2 + #define WMI_HECAP_MAC_BSR_GET WMI_HECAP_MAC_BSR_GET_D2 + #define WMI_HECAP_MAC_BSR_SET WMI_HECAP_MAC_BSR_SET_D2 + #define WMI_HECAP_MAC_BCSTTWT_GET WMI_HECAP_MAC_BCSTTWT_GET_D2 + #define WMI_HECAP_MAC_BCSTTWT_SET WMI_HECAP_MAC_BCSTTWT_SET_D2 + #define WMI_HECAP_MAC_32BITBA_GET WMI_HECAP_MAC_32BITBA_GET_D2 + #define WMI_HECAP_MAC_32BITBA_SET WMI_HECAP_MAC_32BITBA_SET_D2 + #define WMI_HECAP_MAC_MUCASCADE_GET WMI_HECAP_MAC_MUCASCADE_GET_D2 + #define WMI_HECAP_MAC_MUCASCADE_SET WMI_HECAP_MAC_MUCASCADE_SET_D2 + #define WMI_HECAP_MAC_ACKMTIDAMPDU_GET WMI_HECAP_MAC_ACKMTIDAMPDU_GET_D2 + #define WMI_HECAP_MAC_ACKMTIDAMPDU_SET WMI_HECAP_MAC_ACKMTIDAMPDU_SET_D2 + #define WMI_HECAP_MAC_GROUPMSTABA_GET WMI_HECAP_MAC_GROUPMSTABA_GET_D2 + #define WMI_HECAP_MAC_GROUPMSTABA_SET WMI_HECAP_MAC_GROUPMSTABA_SET_D2 + #define WMI_HECAP_MAC_OMI_GET WMI_HECAP_MAC_OMI_GET_D2 + #define WMI_HECAP_MAC_OMI_SET WMI_HECAP_MAC_OMI_SET_D2 + #define WMI_HECAP_MAC_OFDMARA_GET WMI_HECAP_MAC_OFDMARA_GET_D2 + #define WMI_HECAP_MAC_OFDMARA_SET WMI_HECAP_MAC_OFDMARA_SET_D2 + #define WMI_HECAP_MAC_MAXAMPDULEN_EXP_GET WMI_HECAP_MAC_MAXAMPDULEN_EXP_GET_D2 + #define WMI_HECAP_MAC_MAXAMPDULEN_EXP_SET WMI_HECAP_MAC_MAXAMPDULEN_EXP_SET_D2 + #define WMI_HECAP_MAC_AMSDUFRAG_GET WMI_HECAP_MAC_AMSDUFRAG_GET_D2 + #define WMI_HECAP_MAC_AMSDUFRAG_SET WMI_HECAP_MAC_AMSDUFRAG_SET_D2 + #define WMI_HECAP_MAC_FLEXTWT_GET WMI_HECAP_MAC_FLEXTWT_GET_D2 + #define WMI_HECAP_MAC_FLEXTWT_SET WMI_HECAP_MAC_FLEXTWT_SET_D2 + #define WMI_HECAP_MAC_MBSS_GET WMI_HECAP_MAC_MBSS_GET_D2 + #define WMI_HECAP_MAC_MBSS_SET WMI_HECAP_MAC_MBSS_SET_D2 + #define WMI_HECAP_MAC_BSRPAMPDU_GET WMI_HECAP_MAC_BSRPAMPDU_GET_D2 + #define WMI_HECAP_MAC_BSRPAMPDU_SET WMI_HECAP_MAC_BSRPAMPDU_SET_D2 + #define WMI_HECAP_MAC_QTP_GET WMI_HECAP_MAC_QTP_GET_D2 + #define WMI_HECAP_MAC_QTP_SET WMI_HECAP_MAC_QTP_SET_D2 + #define WMI_HECAP_MAC_ABQR_GET WMI_HECAP_MAC_ABQR_GET_D2 + #define WMI_HECAP_MAC_ABQR_SET WMI_HECAP_MAC_ABQR_SET_D2 + #define WMI_HECAP_MAC_SRRESP_GET WMI_HECAP_MAC_SRRESP_GET_D2 + #define WMI_HECAP_MAC_SRRESP_SET WMI_HECAP_MAC_SRRESP_SET_D2 + #define WMI_HECAP_MAC_OPS_GET WMI_HECAP_MAC_OPS_GET_D2 + #define WMI_HECAP_MAC_OPS_SET WMI_HECAP_MAC_OPS_SET_D2 + #define WMI_HECAP_MAC_NDPFDBKRPT_GET WMI_HECAP_MAC_NDPFDBKRPT_GET_D2 + #define WMI_HECAP_MAC_NDPFDBKRPT_SET WMI_HECAP_MAC_NDPFDBKRPT_SET_D2 + #define WMI_HECAP_MAC_MBAHECTRL_GET WMI_HECAP_MAC_MBAHECTRL_GET_D2 + #define WMI_HECAP_MAC_MBAHECTRL_SET WMI_HECAP_MAC_MBAHECTRL_SET_D2 + #define WMI_HECAP_MAC_MURTS_GET WMI_HECAP_MAC_MURTS_GET_D2 + #define WMI_HECAP_MAC_MURTS_SET WMI_HECAP_MAC_MURTS_SET_D2 + #define WMI_HECAP_PHY_CBMODE_GET WMI_HECAP_PHY_CBMODE_GET_D2 + #define WMI_HECAP_PHY_CBMODE_SET WMI_HECAP_PHY_CBMODE_SET_D2 + #define WMI_HECAP_PHY_OLTF_GET WMI_HECAP_PHY_OLTF_GET_D2 + #define WMI_HECAP_PHY_OLTF_SET WMI_HECAP_PHY_OLTF_SET_D2 + #define WMI_HECAP_PHY_SUBFMESTS_GET WMI_HECAP_PHY_SUBFMESTS_GET_D2 + #define WMI_HECAP_PHY_SUBFMESTS_SET WMI_HECAP_PHY_SUBFMESTS_SET_D2 + #define WMI_HECAP_PHY_PADDING_GET WMI_HECAP_PHY_PADDING_GET_D2 + #define WMI_HECAP_PHY_PADDING_SET WMI_HECAP_PHY_PADDING_SET_D2 + #define WMI_HECAP_PHY_DLOFMAMUMIMO_GET WMI_HECAP_PHY_DLOFMAMUMIMO_GET_D2 + #define WMI_HECAP_PHY_DLOFDMAMUMIO_SET WMI_HECAP_PHY_DLOFDMAMUMIO_SET_D2 + #define WMI_HECAP_PHY_32GI_GET WMI_HECAP_PHY_32GI_GET_D2 + #define WMI_HECAP_PHY_32GI_SET WMI_HECAP_PHY_32GI_SET_D2 + #define WMI_HECAP_PHY_NOSUNDIMENS_GET WMI_HECAP_PHY_NOSUNDIMENS_GET_D2 + #define WMI_HECAP_PHY_NOSUNDIMENS_SET WMI_HECAP_PHY_NOSUNDIMENS_SET_D2 + #define WMI_HECAP_PHY_40MHZNSS_GET WMI_HECAP_PHY_40MHZNSS_GET_D2 + #define WMI_HECAP_PHY_40MHZNSS_SET WMI_HECAP_PHY_40MHZNSS_SET_D2 + #define WMI_HECAP_PHY_ULOFDMA_GET WMI_HECAP_PHY_ULOFDMA_GET_D2 + #define WMI_HECAP_PHY_ULOFDMA_SET WMI_HECAP_PHY_ULOFDMA_SET_D2 + #define WMI_HECAP_PHY_DCM_GET WMI_HECAP_PHY_DCM_GET_D2 + #define WMI_HECAP_PHY_DCM_SET WMI_HECAP_PHY_DCM_SET_D2 + #define WMI_HECAP_PHY_NSTSLT80MHZ_GET WMI_HECAP_PHY_NSTSLT80MHZ_GET_D2 + #define WMI_HECAP_PHY_NSTSLT80MHZ_SET WMI_HECAP_PHY_NSTSLT80MHZ_SET_D2 + #define WMI_HECAP_PHY_NSTSGT80MHZ_GET WMI_HECAP_PHY_NSTSGT80MHZ_GET_D2 + #define WMI_HECAP_PHY_NSTSGT80MHZ_SET WMI_HECAP_PHY_NSTSGT80MHZ_SET_D2 +#endif /* SUPPORT_11AX_D3 */ + + /* ADD NEW DEFS HERE */ diff --git a/fw/wmi_version.h b/fw/wmi_version.h index 5ca527a3e227..b4d2f04fb35c 100755 --- a/fw/wmi_version.h +++ b/fw/wmi_version.h @@ -36,7 +36,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 564 +#define __WMI_REVISION_ 570 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work |