diff options
| author | Sachin Bhayare <sachin.bhayare@codeaurora.org> | 2017-04-13 16:03:32 +0530 |
|---|---|---|
| committer | Gerrit - the friendly Code Review server <code-review@localhost> | 2017-05-04 02:07:22 -0700 |
| commit | c25dba2a0b67379987dc94a3b40175efdf456a84 (patch) | |
| tree | b9f4859c7a8d201e1066d4ecfcab757c652917dd | |
| parent | 5d78c03af8ffb440d418cbc45ad0d68928354e48 (diff) | |
msm: mdss: add support for mdss throttle clock handling
Update mdss throttle clock status based on status of display.
Change-Id: Ife21df0c570240c075f039b8d49514bb323021da
Signed-off-by: Sachin Bhayare <sachin.bhayare@codeaurora.org>
| -rw-r--r-- | drivers/video/fbdev/msm/mdss.h | 1 | ||||
| -rw-r--r-- | drivers/video/fbdev/msm/mdss_mdp.c | 11 |
2 files changed, 10 insertions, 2 deletions
diff --git a/drivers/video/fbdev/msm/mdss.h b/drivers/video/fbdev/msm/mdss.h index 796246a856b4..1c984d02755e 100644 --- a/drivers/video/fbdev/msm/mdss.h +++ b/drivers/video/fbdev/msm/mdss.h @@ -45,6 +45,7 @@ enum mdss_mdp_clk_type { MDSS_CLK_MDP_LUT, MDSS_CLK_MDP_VSYNC, MDSS_CLK_MNOC_AHB, + MDSS_CLK_THROTTLE_AXI, MDSS_MAX_CLK }; diff --git a/drivers/video/fbdev/msm/mdss_mdp.c b/drivers/video/fbdev/msm/mdss_mdp.c index a645a3495593..d88d87bd2092 100644 --- a/drivers/video/fbdev/msm/mdss_mdp.c +++ b/drivers/video/fbdev/msm/mdss_mdp.c @@ -1373,7 +1373,9 @@ static inline void __mdss_mdp_reg_access_clk_enable( mdss_mdp_clk_update(MDSS_CLK_AHB, 1); mdss_mdp_clk_update(MDSS_CLK_AXI, 1); mdss_mdp_clk_update(MDSS_CLK_MDP_CORE, 1); + mdss_mdp_clk_update(MDSS_CLK_THROTTLE_AXI, 1); } else { + mdss_mdp_clk_update(MDSS_CLK_THROTTLE_AXI, 0); mdss_mdp_clk_update(MDSS_CLK_MDP_CORE, 0); mdss_mdp_clk_update(MDSS_CLK_AXI, 0); mdss_mdp_clk_update(MDSS_CLK_AHB, 0); @@ -1415,6 +1417,7 @@ static void __mdss_mdp_clk_control(struct mdss_data_type *mdata, bool enable) mdss_mdp_clk_update(MDSS_CLK_AXI, 1); mdss_mdp_clk_update(MDSS_CLK_MDP_CORE, 1); mdss_mdp_clk_update(MDSS_CLK_MDP_LUT, 1); + mdss_mdp_clk_update(MDSS_CLK_THROTTLE_AXI, 1); if (mdata->vsync_ena) mdss_mdp_clk_update(MDSS_CLK_MDP_VSYNC, 1); } else { @@ -1430,6 +1433,7 @@ static void __mdss_mdp_clk_control(struct mdss_data_type *mdata, bool enable) mdss_mdp_clk_update(MDSS_CLK_AXI, 0); mdss_mdp_clk_update(MDSS_CLK_AHB, 0); mdss_mdp_clk_update(MDSS_CLK_MNOC_AHB, 0); + mdss_mdp_clk_update(MDSS_CLK_THROTTLE_AXI, 0); /* release iommu control */ mdss_iommu_ctrl(0); @@ -1915,8 +1919,7 @@ static int mdss_mdp_irq_clk_setup(struct mdss_data_type *mdata) if (mdss_mdp_irq_clk_register(mdata, "bus_clk", MDSS_CLK_AXI) || mdss_mdp_irq_clk_register(mdata, "iface_clk", MDSS_CLK_AHB) || - mdss_mdp_irq_clk_register(mdata, "core_clk", - MDSS_CLK_MDP_CORE)) + mdss_mdp_irq_clk_register(mdata, "core_clk", MDSS_CLK_MDP_CORE)) return -EINVAL; /* lut_clk is not present on all MDSS revisions */ @@ -1928,6 +1931,10 @@ static int mdss_mdp_irq_clk_setup(struct mdss_data_type *mdata) /* this clk is not present on all MDSS revisions */ mdss_mdp_irq_clk_register(mdata, "mnoc_clk", MDSS_CLK_MNOC_AHB); + /* this clk is not present on all MDSS revisions */ + mdss_mdp_irq_clk_register(mdata, "throttle_bus_clk", + MDSS_CLK_THROTTLE_AXI); + /* Setting the default clock rate to the max supported.*/ mdss_mdp_set_clk_rate(mdata->max_mdp_clk_rate, false); pr_debug("mdp clk rate=%ld\n", |