Merge "drm/msm/sde: enable pixel extension and qseed3 along with VIG pipes"

4 files changed, 91 insertions, 2 deletions

diff --git a/arch/arm64/configs/msm-perf_defconfig b/arch/arm64/configs/msm-perf_defconfig
index 176bd7fad9a9..03c5bc89b6f5 100644
--- a/arch/arm64/configs/msm-perf_defconfig
+++ b/arch/arm64/configs/msm-perf_defconfig
@@ -345,6 +345,7 @@ CONFIG_THERMAL_TSENS8974=y
 CONFIG_THERMAL_QPNP_ADC_TM=y
 CONFIG_MFD_SPMI_PMIC=y
 CONFIG_WCD9335_CODEC=y
+CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_REGULATOR_RPM_SMD=y
 CONFIG_REGULATOR_QPNP=y
@@ -394,7 +395,7 @@ CONFIG_MSM_VIDC_VMEM=y
 CONFIG_MSM_VIDC_GOVERNORS=y
 CONFIG_MSM_SDE_ROTATOR=y
 CONFIG_QCOM_KGSL=y
-CONFIG_DRM=y
+CONFIG_FB=y
 CONFIG_FB_MSM=y
 CONFIG_FB_MSM_MDSS=y
 CONFIG_FB_MSM_MDSS_WRITEBACK=y
@@ -518,6 +519,7 @@ CONFIG_MSM_IPC_ROUTER_MHI_XPRT=y
 CONFIG_MSM_IPC_ROUTER_GLINK_XPRT=y
 CONFIG_MSM_GLINK_PKT=y
 CONFIG_MSM_SPM=y
+CONFIG_QCOM_SCM=y
 CONFIG_QCOM_SCM_XPU=y
 CONFIG_QCOM_WATCHDOG_V2=y
 CONFIG_QCOM_MEMORY_DUMP_V2=y
@@ -562,6 +564,7 @@ CONFIG_EXT4_FS_ICE_ENCRYPTION=y
 CONFIG_FUSE_FS=y
 CONFIG_MSDOS_FS=y
 CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
 CONFIG_TMPFS_POSIX_ACL=y
 CONFIG_ECRYPT_FS=y
 CONFIG_ECRYPT_FS_MESSAGING=y
diff --git a/arch/arm64/configs/msm_defconfig b/arch/arm64/configs/msm_defconfig
index a7d2b895e08c..b4ddd9a2bed5 100644
--- a/arch/arm64/configs/msm_defconfig
+++ b/arch/arm64/configs/msm_defconfig
@@ -332,6 +332,7 @@ CONFIG_THERMAL_TSENS8974=y
 CONFIG_THERMAL_QPNP_ADC_TM=y
 CONFIG_MFD_SPMI_PMIC=y
 CONFIG_WCD9335_CODEC=y
+CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_REGULATOR_RPM_SMD=y
 CONFIG_REGULATOR_QPNP=y
@@ -382,7 +383,7 @@ CONFIG_MSM_VIDC_VMEM=y
 CONFIG_MSM_VIDC_GOVERNORS=y
 CONFIG_MSM_SDE_ROTATOR=y
 CONFIG_QCOM_KGSL=y
-CONFIG_DRM=y
+CONFIG_FB=y
 CONFIG_FB_MSM=y
 CONFIG_FB_MSM_MDSS=y
 CONFIG_FB_MSM_MDSS_WRITEBACK=y
@@ -519,6 +520,7 @@ CONFIG_MSM_IPC_ROUTER_MHI_XPRT=y
 CONFIG_MSM_IPC_ROUTER_GLINK_XPRT=y
 CONFIG_MSM_GLINK_PKT=y
 CONFIG_MSM_SPM=y
+CONFIG_QCOM_SCM=y
 CONFIG_QCOM_SCM_XPU=y
 CONFIG_QCOM_WATCHDOG_V2=y
 CONFIG_QCOM_MEMORY_DUMP_V2=y
@@ -568,6 +570,7 @@ CONFIG_EXT4_FS_ICE_ENCRYPTION=y
 CONFIG_FUSE_FS=y
 CONFIG_MSDOS_FS=y
 CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
 CONFIG_TMPFS_POSIX_ACL=y
 CONFIG_ECRYPT_FS=y
 CONFIG_ECRYPT_FS_MESSAGING=y
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_sspp.h b/drivers/gpu/drm/msm/sde/sde_hw_sspp.h
index 743f5e72d1a8..ceb48282081d 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_sspp.h
+++ b/drivers/gpu/drm/msm/sde/sde_hw_sspp.h
@@ -64,6 +64,18 @@ enum sde_hw_filter {
 	SDE_SCALE_FILTER_MAX
 };
 
+enum sde_hw_filter_alpa {
+	SDE_SCALE_ALPHA_PIXEL_REP,
+	SDE_SCALE_ALPHA_BIL
+};
+
+enum sde_hw_filter_yuv {
+	SDE_SCALE_2D_4X4,
+	SDE_SCALE_2D_CIR,
+	SDE_SCALE_1D_SEP,
+	SDE_SCALE_BIL
+};
+
 struct sde_hw_sharp_cfg {
 	u32 strength;
 	u32 edge_thr;
diff --git a/drivers/gpu/drm/msm/sde/sde_plane.c b/drivers/gpu/drm/msm/sde/sde_plane.c
index 3ca74926cfac..b3de45302dea 100644
--- a/drivers/gpu/drm/msm/sde/sde_plane.c
+++ b/drivers/gpu/drm/msm/sde/sde_plane.c
@@ -60,6 +60,9 @@
 #define SDE_PLANE_DIRTY_SHARPEN	0x4
 #define SDE_PLANE_DIRTY_ALL	0xFFFFFFFF
 
+#define SDE_QSEED3_DEFAULT_PRELOAD_H 0x4
+#define SDE_QSEED3_DEFAULT_PRELOAD_V 0x3
+
 /**
  * enum sde_plane_qos - Different qos configurations for each pipe
  *
@@ -615,6 +618,73 @@ static void _sde_plane_setup_scaler3(struct sde_plane *psde,
 		const struct sde_format *fmt,
 		uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v)
 {
+	uint32_t decimated, i;
+
+	if (!psde || !scale_cfg || !fmt || !chroma_subsmpl_h ||
+			!chroma_subsmpl_v) {
+		SDE_ERROR("psde %pK scale_cfg %pK fmt %pK smp_h %d smp_v %d\n"
+			, psde, scale_cfg, fmt, chroma_subsmpl_h,
+			chroma_subsmpl_v);
+		return;
+	}
+
+	memset(scale_cfg, 0, sizeof(*scale_cfg));
+
+	decimated = DECIMATED_DIMENSION(src_w,
+			psde->pipe_cfg.horz_decimation);
+	scale_cfg->phase_step_x[SDE_SSPP_COMP_0] =
+		mult_frac((1 << PHASE_STEP_SHIFT), decimated, dst_w);
+	decimated = DECIMATED_DIMENSION(src_h,
+			psde->pipe_cfg.vert_decimation);
+	scale_cfg->phase_step_y[SDE_SSPP_COMP_0] =
+		mult_frac((1 << PHASE_STEP_SHIFT), decimated, dst_h);
+
+
+	scale_cfg->phase_step_y[SDE_SSPP_COMP_1_2] =
+		scale_cfg->phase_step_y[SDE_SSPP_COMP_0] / chroma_subsmpl_v;
+	scale_cfg->phase_step_x[SDE_SSPP_COMP_1_2] =
+		scale_cfg->phase_step_x[SDE_SSPP_COMP_0] / chroma_subsmpl_h;
+
+	scale_cfg->phase_step_x[SDE_SSPP_COMP_2] =
+		scale_cfg->phase_step_x[SDE_SSPP_COMP_1_2];
+	scale_cfg->phase_step_y[SDE_SSPP_COMP_2] =
+		scale_cfg->phase_step_y[SDE_SSPP_COMP_1_2];
+
+	scale_cfg->phase_step_x[SDE_SSPP_COMP_3] =
+		scale_cfg->phase_step_x[SDE_SSPP_COMP_0];
+	scale_cfg->phase_step_y[SDE_SSPP_COMP_3] =
+		scale_cfg->phase_step_y[SDE_SSPP_COMP_0];
+
+	for (i = 0; i < SDE_MAX_PLANES; i++) {
+		scale_cfg->src_width[i] = DECIMATED_DIMENSION(src_w,
+				psde->pipe_cfg.horz_decimation);
+		scale_cfg->src_height[i] = DECIMATED_DIMENSION(src_h,
+				psde->pipe_cfg.vert_decimation);
+		if (SDE_FORMAT_IS_YUV(fmt))
+			scale_cfg->src_width[i] &= ~0x1;
+		if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2) {
+			scale_cfg->src_width[i] /= chroma_subsmpl_h;
+			scale_cfg->src_height[i] /= chroma_subsmpl_v;
+		}
+		scale_cfg->preload_x[i] = SDE_QSEED3_DEFAULT_PRELOAD_H;
+		scale_cfg->preload_y[i] = SDE_QSEED3_DEFAULT_PRELOAD_V;
+		psde->pixel_ext.num_ext_pxls_top[i] =
+			scale_cfg->src_height[i];
+		psde->pixel_ext.num_ext_pxls_left[i] =
+			scale_cfg->src_width[i];
+	}
+	if (!(SDE_FORMAT_IS_YUV(fmt)) && (src_h == dst_h)
+		&& (src_w == dst_w))
+		return;
+
+	scale_cfg->dst_width = dst_w;
+	scale_cfg->dst_height = dst_h;
+	scale_cfg->y_rgb_filter_cfg = SDE_SCALE_BIL;
+	scale_cfg->uv_filter_cfg = SDE_SCALE_BIL;
+	scale_cfg->alpha_filter_cfg = SDE_SCALE_ALPHA_BIL;
+	scale_cfg->lut_flag = 0;
+	scale_cfg->blend_cfg = 1;
+	scale_cfg->enable = 1;
 }
 
 /**
@@ -901,6 +971,7 @@ static void _sde_plane_setup_scaler(struct sde_plane *psde,
 
 		error = _sde_plane_setup_scaler3_lut(psde, pstate);
 		if (error || !psde->pixel_ext_usr) {
+			memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
 			/* calculate default config for QSEED3 */
 			_sde_plane_setup_scaler3(psde,
 					psde->pipe_cfg.src_rect.w,