diff options
| author | Huaibin Yang <huaibiny@codeaurora.org> | 2014-12-16 11:45:56 -0800 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-23 20:41:37 -0700 |
| commit | bbf226f890adac65afabfb41b2c4489d1b07c864 (patch) | |
| tree | fb7e4634c63669762c524b79b69b4cc8ba719514 | |
| parent | c47167a9bedac245d6982fa6a4cc644cf973f7e7 (diff) | |
clk: mdss: add delay for new pll locking sequence
This change is corresponding to the update from h/w documentation.
Change-Id: I74ac06ce0cd1b0a8b52be6fa7dab123ebb2fc79e
Signed-off-by: Huaibin Yang <huaibiny@codeaurora.org>
| -rw-r--r-- | drivers/clk/msm/mdss/mdss-dsi-20nm-pll-util.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/msm/mdss/mdss-dsi-20nm-pll-util.c b/drivers/clk/msm/mdss/mdss-dsi-20nm-pll-util.c index 493c1634f50f..01891514503f 100644 --- a/drivers/clk/msm/mdss/mdss-dsi-20nm-pll-util.c +++ b/drivers/clk/msm/mdss/mdss-dsi-20nm-pll-util.c @@ -921,6 +921,7 @@ static void pll_20nm_config_vco_start(void __iomem *pll_base) MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_PLL_VCOTAIL_EN, 0x03); MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_RESETSM_CNTRL3, 0x02); + udelay(10); MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_RESETSM_CNTRL3, 0x03); } |