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authorVamsi Krishna Samavedam <vskrishn@codeaurora.org>2016-08-08 18:59:34 -0700
committerVamsi Krishna Samavedam <vskrishn@codeaurora.org>2016-08-30 12:25:33 -0700
commitb7c8e2b080d5214d9ee25e9b644eb8d5b548be04 (patch)
treeb780c3445d0a87b001ed20026fdc8aaca57db617
parent299063819e84815164f8111cb33b45ce74942444 (diff)
ARM: dts: msm: Update tcsr_clmap signal for msmcobalt
Update the tcsr_clamp_dig_n signal and phy init sequence to reduce the random leakage from qusb2 phy. Random leakage can result from turning on/off analog power rails before/after digital power rails. Change-Id: Id51a2d34f61c0a41891551d15b706872abf13809 Signed-off-by: Vamsi Krishna Samavedam <vskrishn@codeaurora.org>
-rw-r--r--arch/arm/boot/dts/qcom/msmcobalt.dtsi9
1 files changed, 6 insertions, 3 deletions
diff --git a/arch/arm/boot/dts/qcom/msmcobalt.dtsi b/arch/arm/boot/dts/qcom/msmcobalt.dtsi
index f830b2172050..b69e340cee28 100644
--- a/arch/arm/boot/dts/qcom/msmcobalt.dtsi
+++ b/arch/arm/boot/dts/qcom/msmcobalt.dtsi
@@ -1835,15 +1835,18 @@
qusb_phy0: qusb@c012000 {
compatible = "qcom,qusb2phy-v2";
- reg = <0x0c012000 0x2a8>;
- reg-names = "qusb_phy_base";
+ reg = <0x0c012000 0x2a8>,
+ <0x01fcb24c 0x4>;
+ reg-names = "qusb_phy_base",
+ "tcsr_clamp_dig_n_1p8";
vdd-supply = <&pmcobalt_l1>;
vdda18-supply = <&pmcobalt_l12>;
vdda33-supply = <&pmcobalt_l24>;
qcom,vdd-voltage-level = <0 880000 880000>;
qcom,qusb-phy-init-seq =
/* <value reg_offset> */
- <0x13 0x04
+ <0x80 0x0
+ 0x13 0x04
0x7c 0x18c
0x80 0x2c
0x0a 0x184