diff options
| author | Chunhuan Zhan <zhanc@codeaurora.org> | 2018-03-06 21:10:15 +0800 |
|---|---|---|
| committer | Gerrit - the friendly Code Review server <code-review@localhost> | 2018-03-14 03:03:47 -0700 |
| commit | b5e111203e2650e45ec1d6de8f51d9e4acca515f (patch) | |
| tree | 77e6dc5ce96b9721b107215c770da655ca3abd38 | |
| parent | 3e1f25e9559f01dcaf266c4ece9fee779af3e244 (diff) | |
ARM: dts: msm: change early camera on msm8996 agave
make this change to avoid the clk warning logs
1. remove the repeated clks
2. change the sequence of clks , make the parent clks before children clks
3. add clock-control for early-camera
Change-Id: I1746cbdce3a7335187433ae993637d2db9cdf58e
Signed-off-by: Chunhuan Zhan <zhanc@codeaurora.org>
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8996-agave-adp.dtsi | 35 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8996-auto-cdp.dtsi | 35 |
2 files changed, 46 insertions, 24 deletions
diff --git a/arch/arm/boot/dts/qcom/msm8996-agave-adp.dtsi b/arch/arm/boot/dts/qcom/msm8996-agave-adp.dtsi index 9c6d12f38563..9e14211bdac8 100644 --- a/arch/arm/boot/dts/qcom/msm8996-agave-adp.dtsi +++ b/arch/arm/boot/dts/qcom/msm8996-agave-adp.dtsi @@ -828,15 +828,14 @@ <&clock_mmss clk_camss_vfe0_ahb_clk>, <&clock_mmss clk_camss_vfe1_ahb_clk>, <&clock_mmss clk_camss_vfe_axi_clk>, - <&clock_mmss clk_camss_vfe0_stream_clk>, - <&clock_mmss clk_camss_vfe1_stream_clk>, <&clock_mmss clk_smmu_vfe_axi_clk>, <&clock_mmss clk_smmu_vfe_ahb_clk>, - <&clock_mmss clk_camss_csi_vfe0_clk>, - <&clock_mmss clk_camss_csi_vfe1_clk>, <&clock_mmss clk_vfe0_clk_src>, <&clock_mmss clk_vfe1_clk_src>, + <&clock_mmss clk_camss_vfe0_stream_clk>, + <&clock_mmss clk_camss_vfe1_stream_clk>, <&clock_mmss clk_camss_csi_vfe0_clk>, + <&clock_mmss clk_camss_csi_vfe1_clk>, <&clock_mmss clk_camss_csi2_ahb_clk>, <&clock_mmss clk_camss_csi2_clk>, <&clock_mmss clk_camss_csi2phy_clk>, @@ -858,15 +857,14 @@ "camss_vfe0_ahb_clk", "camss_vfe1_ahb_clk", "camss_vfe_axi_clk", - "camss_vfe0_stream_clk", - "camss_vfe1_stream_clk", "smmu_vfe_axi_clk", "smmu_vfe_ahb_clk", - "camss_csi_vfe0_clk", - "camss_csi_vfe1_clk", "vfe0_clk_src", "vfe1_clk_src", + "camss_vfe0_stream_clk", + "camss_vfe1_stream_clk", "camss_csi_vfe0_clk", + "camss_csi_vfe1_clk", "camss_csi2_ahb_clk", "camss_csi2_clk", "camss_csi2phy_clk", @@ -876,7 +874,6 @@ "camss_ispif_ahb_clk", "clk_camss_vfe0_clk", "clk_camss_vfe1_clk"; - qcom,clock-rates = <19200000 19200000 19200000 @@ -890,13 +887,12 @@ 320000000 0 0 + 320000000 + 320000000 0 0 0 0 - 320000000 - 320000000 - 0 0 200000000 200000000 @@ -906,6 +902,21 @@ 0 100000000 100000000>; + qcom,clock-cntl-support; + qcom,clock-control = "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "INIT_RATE", + "INIT_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE","NO_SET_RATE", + "INIT_RATE","NO_SET_RATE", + "INIT_RATE", "NO_SET_RATE", + "NO_SET_RATE","NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE"; }; qcom,ntn_avb { diff --git a/arch/arm/boot/dts/qcom/msm8996-auto-cdp.dtsi b/arch/arm/boot/dts/qcom/msm8996-auto-cdp.dtsi index 0c648a93aaab..5c08acbbcd19 100644 --- a/arch/arm/boot/dts/qcom/msm8996-auto-cdp.dtsi +++ b/arch/arm/boot/dts/qcom/msm8996-auto-cdp.dtsi @@ -593,15 +593,14 @@ <&clock_mmss clk_camss_vfe0_ahb_clk>, <&clock_mmss clk_camss_vfe1_ahb_clk>, <&clock_mmss clk_camss_vfe_axi_clk>, - <&clock_mmss clk_camss_vfe0_stream_clk>, - <&clock_mmss clk_camss_vfe1_stream_clk>, <&clock_mmss clk_smmu_vfe_axi_clk>, <&clock_mmss clk_smmu_vfe_ahb_clk>, - <&clock_mmss clk_camss_csi_vfe0_clk>, - <&clock_mmss clk_camss_csi_vfe1_clk>, <&clock_mmss clk_vfe0_clk_src>, <&clock_mmss clk_vfe1_clk_src>, + <&clock_mmss clk_camss_vfe0_stream_clk>, + <&clock_mmss clk_camss_vfe1_stream_clk>, <&clock_mmss clk_camss_csi_vfe0_clk>, + <&clock_mmss clk_camss_csi_vfe1_clk>, <&clock_mmss clk_camss_csi2_ahb_clk>, <&clock_mmss clk_camss_csi2_clk>, <&clock_mmss clk_camss_csi2phy_clk>, @@ -623,15 +622,14 @@ "camss_vfe0_ahb_clk", "camss_vfe1_ahb_clk", "camss_vfe_axi_clk", - "camss_vfe0_stream_clk", - "camss_vfe1_stream_clk", "smmu_vfe_axi_clk", "smmu_vfe_ahb_clk", - "camss_csi_vfe0_clk", - "camss_csi_vfe1_clk", "vfe0_clk_src", "vfe1_clk_src", + "camss_vfe0_stream_clk", + "camss_vfe1_stream_clk", "camss_csi_vfe0_clk", + "camss_csi_vfe1_clk", "camss_csi2_ahb_clk", "camss_csi2_clk", "camss_csi2phy_clk", @@ -641,7 +639,6 @@ "camss_ispif_ahb_clk", "clk_camss_vfe0_clk", "clk_camss_vfe1_clk"; - qcom,clock-rates = <19200000 19200000 19200000 @@ -655,13 +652,12 @@ 320000000 0 0 + 320000000 + 320000000 0 0 0 0 - 320000000 - 320000000 - 0 0 200000000 200000000 @@ -671,6 +667,21 @@ 0 100000000 100000000>; + qcom,clock-cntl-support; + qcom,clock-control = "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "INIT_RATE", + "INIT_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE","NO_SET_RATE", + "INIT_RATE","NO_SET_RATE", + "INIT_RATE", "NO_SET_RATE", + "NO_SET_RATE","NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE"; }; ntn1: ntn_avb@1 { /* Neutrno device on RC1*/ |