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authorLinux Build Service Account <lnxbuild@localhost>2017-03-21 05:00:54 -0700
committerGerrit - the friendly Code Review server <code-review@localhost>2017-03-21 05:00:54 -0700
commitb23c3fca0596a7e23dc26cb54b719774eb7d3045 (patch)
treed452e0f606211b7c70215c60226ad90211e35d59
parent5c25f22a6c50d5851c2917599fa65c7bb3cca1ae (diff)
parent4cd60f6e04f2f682b46abc3d703e6446b14b21dc (diff)
Merge "msm: mdss: add support for multiple DSI host escape clk frequencies"
-rw-r--r--Documentation/devicetree/bindings/fb/mdss-dsi-panel.txt3
-rw-r--r--drivers/video/fbdev/msm/mdss_dsi.c18
-rw-r--r--drivers/video/fbdev/msm/mdss_dsi.h1
-rw-r--r--drivers/video/fbdev/msm/mdss_dsi_panel.c7
-rw-r--r--drivers/video/fbdev/msm/mdss_panel.h6
5 files changed, 28 insertions, 7 deletions
diff --git a/Documentation/devicetree/bindings/fb/mdss-dsi-panel.txt b/Documentation/devicetree/bindings/fb/mdss-dsi-panel.txt
index 4fd0c2ecbc6e..90ccfa7c62e2 100644
--- a/Documentation/devicetree/bindings/fb/mdss-dsi-panel.txt
+++ b/Documentation/devicetree/bindings/fb/mdss-dsi-panel.txt
@@ -271,6 +271,8 @@ Optional properties:
"trigger_sw_te" = Software trigger and TE
- qcom,mdss-dsi-panel-framerate: Specifies the frame rate for the panel.
60 = 60 frames per second (default)
+- qcom,mdss-dsi-host-esc-clk-freq-hz: Specifies the escape clock needed for the host.
+ 19200000 = 19.2 MHz (default)
- qcom,mdss-dsi-panel-clockrate: A 64 bit value specifies the panel clock speed in Hz.
0 = default value.
- qcom,mdss-mdp-kickoff-threshold: This property can be used to define a region
@@ -657,6 +659,7 @@ Example:
qcom,mdss-dsi-mdp-trigger = <0>;
qcom,mdss-dsi-dma-trigger = <0>;
qcom,mdss-dsi-panel-framerate = <60>;
+ qcom,mdss-dsi-host-esc-clk-freq-hz = <19200000>;
qcom,mdss-dsi-panel-clockrate = <424000000>;
qcom,mdss-mdp-kickoff-threshold = <11 2430>;
qcom,mdss-mdp-kickoff-delay = <1000>;
diff --git a/drivers/video/fbdev/msm/mdss_dsi.c b/drivers/video/fbdev/msm/mdss_dsi.c
index 88eb794a5ff5..ed6ef75b0719 100644
--- a/drivers/video/fbdev/msm/mdss_dsi.c
+++ b/drivers/video/fbdev/msm/mdss_dsi.c
@@ -34,7 +34,6 @@
#include "mdss_dsi_phy.h"
#include "mdss_dba_utils.h"
-#define XO_CLK_RATE 19200000
#define CMDLINE_DSI_CTL_NUM_STRING_LEN 2
/* Master structure to hold all the information about the DSI/panel */
@@ -1871,7 +1870,7 @@ static void __mdss_dsi_dyn_refresh_config(
static void __mdss_dsi_calc_dfps_delay(struct mdss_panel_data *pdata)
{
- u32 esc_clk_rate = XO_CLK_RATE;
+ u32 esc_clk_rate_hz;
u32 pipe_delay, pipe_delay2 = 0, pll_delay;
u32 hsync_period = 0;
u32 pclk_to_esc_ratio, byte_to_esc_ratio, hr_bit_to_esc_ratio;
@@ -1898,9 +1897,11 @@ static void __mdss_dsi_calc_dfps_delay(struct mdss_panel_data *pdata)
pinfo = &pdata->panel_info;
pd = &(pinfo->mipi.dsi_phy_db);
- pclk_to_esc_ratio = (ctrl_pdata->pclk_rate / esc_clk_rate);
- byte_to_esc_ratio = (ctrl_pdata->byte_clk_rate / esc_clk_rate);
- hr_bit_to_esc_ratio = ((ctrl_pdata->byte_clk_rate * 4) / esc_clk_rate);
+ esc_clk_rate_hz = ctrl_pdata->esc_clk_rate_hz;
+ pclk_to_esc_ratio = (ctrl_pdata->pclk_rate / esc_clk_rate_hz);
+ byte_to_esc_ratio = (ctrl_pdata->byte_clk_rate / esc_clk_rate_hz);
+ hr_bit_to_esc_ratio = ((ctrl_pdata->byte_clk_rate * 4) /
+ esc_clk_rate_hz);
hsync_period = mdss_panel_get_htotal(pinfo, true);
pipe_delay = (hsync_period + 1) / pclk_to_esc_ratio;
@@ -1922,7 +1923,7 @@ static void __mdss_dsi_calc_dfps_delay(struct mdss_panel_data *pdata)
((pd->timing[4] >> 1) + 1)) / hr_bit_to_esc_ratio);
/* 130 us pll delay recommended by h/w doc */
- pll_delay = ((130 * esc_clk_rate) / 1000000) * 2;
+ pll_delay = ((130 * esc_clk_rate_hz) / 1000000) * 2;
MIPI_OUTP((ctrl_pdata->ctrl_base) + DSI_DYNAMIC_REFRESH_PIPE_DELAY,
pipe_delay);
@@ -3057,7 +3058,7 @@ static int mdss_dsi_set_clk_rates(struct mdss_dsi_ctrl_pdata *ctrl_pdata)
rc = mdss_dsi_clk_set_link_rate(ctrl_pdata->dsi_clk_handle,
MDSS_DSI_LINK_ESC_CLK,
- 19200000,
+ ctrl_pdata->esc_clk_rate_hz,
MDSS_DSI_CLK_UPDATE_CLK_RATE_AT_ON);
if (rc) {
pr_err("%s: dsi_esc_clk - clk_set_rate failed\n",
@@ -4236,6 +4237,9 @@ int dsi_panel_device_register(struct platform_device *ctrl_pdev,
pr_debug("%s: pclk=%d, bclk=%d\n", __func__,
ctrl_pdata->pclk_rate, ctrl_pdata->byte_clk_rate);
+ ctrl_pdata->esc_clk_rate_hz = pinfo->esc_clk_rate_hz;
+ pr_debug("%s: esc clk=%d\n", __func__,
+ ctrl_pdata->esc_clk_rate_hz);
rc = mdss_dsi_get_dt_vreg_data(&ctrl_pdev->dev, pan_node,
&ctrl_pdata->panel_power_data, DSI_PANEL_PM);
diff --git a/drivers/video/fbdev/msm/mdss_dsi.h b/drivers/video/fbdev/msm/mdss_dsi.h
index bd9fd6c7d6c5..14c2732a5789 100644
--- a/drivers/video/fbdev/msm/mdss_dsi.h
+++ b/drivers/video/fbdev/msm/mdss_dsi.h
@@ -477,6 +477,7 @@ struct mdss_dsi_ctrl_pdata {
u32 byte_clk_rate;
u32 pclk_rate_bkp;
u32 byte_clk_rate_bkp;
+ u32 esc_clk_rate_hz;
bool refresh_clk_rate; /* flag to recalculate clk_rate */
struct dss_module_power panel_power_data;
struct dss_module_power power_data[DSI_MAX_PM]; /* for 8x10 */
diff --git a/drivers/video/fbdev/msm/mdss_dsi_panel.c b/drivers/video/fbdev/msm/mdss_dsi_panel.c
index 7cc9ce6e034d..bf701e2a4ac5 100644
--- a/drivers/video/fbdev/msm/mdss_dsi_panel.c
+++ b/drivers/video/fbdev/msm/mdss_dsi_panel.c
@@ -2819,6 +2819,13 @@ static int mdss_panel_parse_dt(struct device_node *np,
MSM_DBA_CHIP_NAME_MAX_LEN);
}
+ rc = of_property_read_u32(np,
+ "qcom,mdss-dsi-host-esc-clk-freq-hz",
+ &pinfo->esc_clk_rate_hz);
+ if (rc)
+ pinfo->esc_clk_rate_hz = MDSS_DSI_MAX_ESC_CLK_RATE_HZ;
+ pr_debug("%s: esc clk %d\n", __func__, pinfo->esc_clk_rate_hz);
+
return 0;
error:
diff --git a/drivers/video/fbdev/msm/mdss_panel.h b/drivers/video/fbdev/msm/mdss_panel.h
index e75c4a3a7cc1..44394596f63c 100644
--- a/drivers/video/fbdev/msm/mdss_panel.h
+++ b/drivers/video/fbdev/msm/mdss_panel.h
@@ -29,6 +29,9 @@ struct panel_id {
#define DEFAULT_FRAME_RATE 60
#define DEFAULT_ROTATOR_FRAME_RATE 120
#define ROTATOR_LOW_FRAME_RATE 30
+
+#define MDSS_DSI_MAX_ESC_CLK_RATE_HZ 19200000
+
#define MDSS_DSI_RST_SEQ_LEN 10
/* worst case prefill lines for all chipsets including all vertical blank */
#define MDSS_MDP_MAX_PREFILL_FETCH 25
@@ -909,6 +912,9 @@ struct mdss_panel_info {
/* HDR properties of display panel*/
struct mdss_panel_hdr_properties hdr_properties;
+
+ /* esc clk recommended for the panel */
+ u32 esc_clk_rate_hz;
};
struct mdss_panel_timing {