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authorTony Truong <truong@codeaurora.org>2015-09-16 17:28:14 -0700
committerDavid Keitel <dkeitel@codeaurora.org>2016-03-22 11:09:30 -0700
commitaedf29f7b606dc44722ccad38828cbc27009eaa5 (patch)
treecc2c29e69444f40969a952007d2198e778d484f0
parent7a18379427ef530d391cd414be9bf89d241cba56 (diff)
msm: pcie: update PCIe PHY for MSM8996v3/v4 based on si learning
Based on si learning, new PCIe PHY settings improve the overall stability of PCIe PHY on MSM8996 v3 and on v4. Thus, update the PCIe PHY sequence for MSM8996 v3 and v4. Change-Id: Ia1ab0af4c4dcf483d3b3dc05b7b13003de788f40 Signed-off-by: Tony Truong <truong@codeaurora.org>
-rw-r--r--drivers/pci/host/pci-msm.c10
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/pci/host/pci-msm.c b/drivers/pci/host/pci-msm.c
index 716e7d3c7aae..e4732fd493f8 100644
--- a/drivers/pci/host/pci-msm.c
+++ b/drivers/pci/host/pci-msm.c
@@ -1239,6 +1239,16 @@ static void pcie_pcs_port_phy_init(struct msm_pcie_dev_t *dev)
PCIE_N_POWER_STATE_CONFIG1(dev->rc_idx, common_phy),
0xA3);
+ if (dev->phy_ver == 0x3) {
+ msm_pcie_write_reg(dev->phy,
+ QSERDES_RX_N_SIGDET_LVL(dev->rc_idx, common_phy),
+ 0x19);
+
+ msm_pcie_write_reg(dev->phy,
+ PCIE_N_TXDEEMPH_M3P5DB_V0(dev->rc_idx, common_phy),
+ 0x0E);
+ }
+
msm_pcie_write_reg(dev->phy,
PCIE_N_POWER_DOWN_CONTROL(dev->rc_idx, common_phy),
0x03);