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authorNarender Ankam <nankam@codeaurora.org>2017-10-17 13:31:11 +0530
committerGerrit - the friendly Code Review server <code-review@localhost>2017-11-26 23:21:02 -0800
commitae5cb0939c002310380f8605183e0d13c5bf4e6d (patch)
treeabeaa276caeadb599d3b985f30dd398189d1546a
parent0d4729533f498d35c495a5b800686e6ca09981e2 (diff)
msm: mdss: hdmi: reset hdmi max supported TMDS clock
In current HDMI driver, SVDs and DTDs derived from EDID of a DS HDMI sink are checked for supportness based on previous connection's max TMDS clock. Always reset the max TMDS clock supported by source before reading EDID from DS HDMI device. Change-Id: If5f58562f186634b1ed066fdebfc9fa6b55c6e8a Signed-off-by: Narender Ankam <nankam@codeaurora.org>
-rw-r--r--drivers/video/fbdev/msm/mdss_hdmi_tx.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/video/fbdev/msm/mdss_hdmi_tx.c b/drivers/video/fbdev/msm/mdss_hdmi_tx.c
index 5eb17ab27e4c..5cb436261115 100644
--- a/drivers/video/fbdev/msm/mdss_hdmi_tx.c
+++ b/drivers/video/fbdev/msm/mdss_hdmi_tx.c
@@ -2223,6 +2223,9 @@ static int hdmi_tx_read_sink_info(struct hdmi_tx_ctrl *hdmi_ctrl)
DSS_REG_W_ND(io, HDMI_DDC_ARBITRATION,
DSS_REG_R(io, HDMI_DDC_ARBITRATION) & ~(BIT(4)));
+ /* Set/Reset HDMI max TMDS clock supported by source */
+ hdmi_edid_set_max_pclk_rate(data, hdmi_ctrl->max_pclk_khz);
+
if (!hdmi_ctrl->custom_edid && !hdmi_ctrl->sim_mode) {
hdmi_ddc_config(&hdmi_ctrl->ddc_ctrl);