diff options
| author | Shashank Mittal <mittals@codeaurora.org> | 2016-06-06 17:48:36 -0700 |
|---|---|---|
| committer | Kyle Yan <kyan@codeaurora.org> | 2016-06-23 14:00:28 -0700 |
| commit | ac49540967880d389fa20db1a043096e29678fec (patch) | |
| tree | a52c4a4e27a1e3096ce387a0dc207ac3e131f9cc | |
| parent | 4d4523f6d93984aa6febffdec86bb3d52a84104d (diff) | |
ARM: dts: msm: add apss ctis on msmcobalt
Add APSS CTIs on msmcobalt. These devices can be used to configure CTIs
for LMH and OLC blocks.
Change-Id: I76de8cd4c1d26015b26524e445d6a5ba00ce2a43
Signed-off-by: Shashank Mittal <mittals@codeaurora.org>
| -rw-r--r-- | arch/arm/boot/dts/qcom/msmcobalt-coresight.dtsi | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom/msmcobalt-coresight.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-coresight.dtsi index 733d36aa43b8..aaafe42ce2a1 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-coresight.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-coresight.dtsi @@ -888,6 +888,42 @@ clock-names = "core_clk", "core_a_clk"; }; + cti_apss: cti@7b80000 { + compatible = "arm,coresight-cti"; + reg = <0x7b80000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-apss"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti_apss_dl: cti@7bc1000 { + compatible = "arm,coresight-cti"; + reg = <0x7bc1000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-apss-dl"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + + cti_olc: cti@7b91000 { + compatible = "arm,coresight-cti"; + reg = <0x7b91000 0x1000>; + reg-names = "cti-base"; + + coresight-name = "coresight-cti-olc"; + + clocks = <&clock_gcc clk_qdss_clk>, + <&clock_gcc clk_qdss_a_clk>; + clock-names = "core_clk", "core_a_clk"; + }; + funnel_qatb: funnel@6005000 { compatible = "arm,primecell"; arm,primecell-periphid = <0x0003b908>; |