diff options
| author | Trilok Soni <tsoni@codeaurora.org> | 2016-01-27 18:23:25 -0800 |
|---|---|---|
| committer | Jeevan Shriram <jshriram@codeaurora.org> | 2016-04-18 17:06:15 -0700 |
| commit | a63df786422a0dda04423157fdd9dd2ff4125ff7 (patch) | |
| tree | 4b2ae55d421cc30cacdad4e7b74a0ae72ca17445 | |
| parent | c42e1feb92d87020cc277637cc03a887d9cfc202 (diff) | |
arm64: errata: Enable #845719 Errataum for Kryo2xx Silver
Errata#845719 is also applicable for Kryo2xx Silver. Enable
the appropriate entry for it with rAp4 revision.
Please note that default midr_range logic depends on the
less or greather than logic with "min" and "max" range,
assuming that rX where X will be zero only. This is not
true for all the processors and since it is 4-bit field
it can be greater than the the "max" or pY bits.
We are specifying the direct match values like
0xA00004 instead here to keep the logic consistent.
CRs-Fixed: 969563
Change-Id: I16b0c2106ae649b8a23b7ebb534c967aebd72774
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
| -rw-r--r-- | arch/arm64/kernel/cpu_errata.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index feb6b4efa641..34aa4b3b47e9 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -24,6 +24,8 @@ #define MIDR_CORTEX_A53 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) #define MIDR_CORTEX_A57 MIDR_CPU_PART(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57) #define MIDR_THUNDERX MIDR_CPU_PART(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) +#define MIDR_KRYO2XX_SILVER \ + MIDR_CPU_PART(ARM_CPU_IMP_QCOM, ARM_CPU_PART_KRYO2XX_SILVER) #define CPU_MODEL_MASK (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | \ MIDR_ARCHITECTURE_MASK) @@ -91,6 +93,12 @@ const struct arm64_cpu_capabilities arm64_errata[] = { .capability = ARM64_WORKAROUND_845719, MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x04), }, + { + /* Kryo2xx Silver rAp4 */ + .desc = "Kryo2xx Silver erratum 845719", + .capability = ARM64_WORKAROUND_845719, + MIDR_RANGE(MIDR_KRYO2XX_SILVER, 0xA00004, 0xA00004), + }, #endif #ifdef CONFIG_CAVIUM_ERRATUM_23154 { |