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authorArun Kumar Neelakantam <aneela@codeaurora.org>2016-05-26 16:18:42 +0530
committerKyle Yan <kyan@codeaurora.org>2016-07-05 15:35:19 -0700
commita619160ab22b336bbc3f005bed9b29911ab2ca47 (patch)
tree5a23c93e80ef2fe25caf9ae3d53c44add4bab1df
parentc458c3a519401e44dbfa2cc1687f7801d9c27072 (diff)
ARM: dts: msm: Add node for QSEE IPC IRQ bridge for msmcobalt
Add the device for bridging an Inter-Processor Communication(IPC) interrupt from a remote subsystem directed towards Qualcomm Technologies, Inc. Secure Execution Environment(QSEE). CRs-Fixed: 1021749 Change-Id: Ib86b3f70a71f222f0ddc1ea49c75cd7d94c47546 Signed-off-by: Arun Kumar Neelakantam <aneela@codeaurora.org>
-rw-r--r--arch/arm/boot/dts/qcom/msmcobalt.dtsi12
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom/msmcobalt.dtsi b/arch/arm/boot/dts/qcom/msmcobalt.dtsi
index 7d61d8f1d341..8d778ac3f104 100644
--- a/arch/arm/boot/dts/qcom/msmcobalt.dtsi
+++ b/arch/arm/boot/dts/qcom/msmcobalt.dtsi
@@ -2707,6 +2707,18 @@
qcom,smmu-support;
status = "disabled";
};
+
+ qcom,qsee_ipc_irq_bridge {
+ compatible = "qcom,qsee-ipc-irq-bridge";
+
+ qcom,qsee-ipc-irq-spss {
+ qcom,rx-irq-clr = <0x1d08008 0x4>;
+ qcom,rx-irq-clr-mask = <0x2>;
+ qcom,dev-name = "qsee_ipc_irq_spss";
+ interrupts = <0 349 4>;
+ label = "spss";
+ };
+ };
};
&clock_cpu {