diff options
| author | Tony Truong <truong@codeaurora.org> | 2015-02-18 15:45:32 -0800 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-22 11:09:06 -0700 |
| commit | a30643faeea8b2d2b24b16b8435d13ee693fe18a (patch) | |
| tree | d690079f678a2a4cdf0f84e8b323fe88904a9265 | |
| parent | c6c800ef6bb4f9961b38dbf263c5243a16813600 (diff) | |
msm: pcie: only look for EP CAP reg for certain testcases
Not all the testcases for debugfs needs the calculated offset
of an endpoint's capability register. Therefore, only calculate
the offset of an endpoint's capanility register if that testcase
needs it.
Change-Id: Iffddcea682d8c9344f51a04b57f60ba906b01dc6
Signed-off-by: Tony Truong <truong@codeaurora.org>
| -rw-r--r-- | drivers/pci/host/pci-msm.c | 39 |
1 files changed, 22 insertions, 17 deletions
diff --git a/drivers/pci/host/pci-msm.c b/drivers/pci/host/pci-msm.c index 9f6caa0c650e..e10812311fc0 100644 --- a/drivers/pci/host/pci-msm.c +++ b/drivers/pci/host/pci-msm.c @@ -1318,26 +1318,31 @@ static void msm_pcie_sel_debug_testcase(struct msm_pcie_dev_t *dev, u32 ep_link_ctrlstts_offset = 0; u32 ep_dev_ctrl2stts2_offset = 0; - current_offset = readl_relaxed(dev->conf + PCIE_CAP_PTR_OFFSET) & 0xff; + if (testcase >= 5 && testcase <= 10) { + current_offset = + readl_relaxed(dev->conf + PCIE_CAP_PTR_OFFSET) & 0xff; - while (current_offset) { - val = readl_relaxed(dev->conf + current_offset); - if ((val & 0xff) == PCIE20_CAP_ID) { - ep_link_ctrlstts_offset = current_offset + 0x10; - ep_dev_ctrl2stts2_offset = current_offset + 0x28; - break; + while (current_offset) { + val = readl_relaxed(dev->conf + current_offset); + if ((val & 0xff) == PCIE20_CAP_ID) { + ep_link_ctrlstts_offset = current_offset + + 0x10; + ep_dev_ctrl2stts2_offset = current_offset + + 0x28; + break; + } + current_offset = (val >> 8) & 0xff; } - current_offset = (val >> 8) & 0xff; - } - if (!ep_link_ctrlstts_offset) - PCIE_DBG(dev, - "RC%d endpoint does not support PCIe capability registers\n", - dev->rc_idx); - else - PCIE_DBG(dev, - "RC%d: ep_link_ctrlstts_offset: 0x%x\n", - dev->rc_idx, ep_link_ctrlstts_offset); + if (!ep_link_ctrlstts_offset) + PCIE_DBG(dev, + "RC%d endpoint does not support PCIe capability registers\n", + dev->rc_idx); + else + PCIE_DBG(dev, + "RC%d: ep_link_ctrlstts_offset: 0x%x\n", + dev->rc_idx, ep_link_ctrlstts_offset); + } switch (testcase) { case 0: /* output status */ |