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authorJordan Crouse <jcrouse@codeaurora.org>2017-07-20 12:04:52 -0600
committerJordan Crouse <jcrouse@codeaurora.org>2017-07-24 13:01:13 -0600
commita0c5da88c9bdcd496ab1d587e00871fa2634fc73 (patch)
tree0bbf6ecc3f6a024bb5741d991c5bf1aef3f4fb9f
parent74910dd6a289792505852c6c071ec9923e891cc4 (diff)
drm/msm: Remember the state of A5XX hardware clock gating
Remember if the A5XX hardware clock gating is currently enabled or disabled to avoid inadvertently enabling it. Change-Id: Ic0dedbada3734a257ac966c041d06695f3521ad4 Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
-rw-r--r--drivers/gpu/drm/msm/adreno/a5xx_gpu.c6
-rw-r--r--drivers/gpu/drm/msm/adreno/a5xx_gpu.h1
2 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
index 47f437fa4fb3..e66079cdd53e 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
@@ -375,6 +375,7 @@ static const struct {
void a5xx_set_hwcg(struct msm_gpu *gpu, bool state)
{
struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
+ struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);
unsigned int i;
for (i = 0; i < ARRAY_SIZE(a5xx_hwcg); i++)
@@ -391,6 +392,11 @@ void a5xx_set_hwcg(struct msm_gpu *gpu, bool state)
gpu_write(gpu, REG_A5XX_RBBM_CLOCK_CNTL, state ? 0xAAA8AA00 : 0);
gpu_write(gpu, REG_A5XX_RBBM_ISDB_CNT, state ? 0x182 : 0x180);
+
+ if (state)
+ set_bit(A5XX_HWCG_ENABLED, &a5xx_gpu->flags);
+ else
+ clear_bit(A5XX_HWCG_ENABLED, &a5xx_gpu->flags);
}
static int a5xx_me_init(struct msm_gpu *gpu)
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.h b/drivers/gpu/drm/msm/adreno/a5xx_gpu.h
index f8b00982fe86..e637237fa811 100644
--- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.h
@@ -23,6 +23,7 @@
enum {
A5XX_ZAP_SHADER_LOADED = 1,
+ A5XX_HWCG_ENABLED = 2,
};
struct a5xx_gpu {