qcacld: Add support to dump copy engine debug registers

When target assert happens, sometimes host driver fails to access target
RAM area to collect RAM dump because of copy engine failure. Add support
to print copy engine debug registers in order to debug this case.

Change-Id: I1305db88fc754e898054a823682f4aea344a7fa6
CRs-Fixed: 613150

7 files changed, 337 insertions, 21 deletions

diff --git a/CORE/SERVICES/BMI/ol_fw.c b/CORE/SERVICES/BMI/ol_fw.c
index 138806ab8ee6..4f5534af58b8 100644
--- a/CORE/SERVICES/BMI/ol_fw.c
+++ b/CORE/SERVICES/BMI/ol_fw.c
@@ -35,6 +35,7 @@
 #include "wma_api.h"
 #include "wma.h"
 #include "if_pci.h"
+#include "regtable.h"
 
 #define ATH_MODULE_NAME bmi
 #include "a_debug.h"
@@ -494,23 +495,33 @@ u_int32_t host_interest_item_address(u_int32_t target_type, u_int32_t item_offse
 #if defined(QCA_WIFI_2_0) && !defined(QCA_WIFI_ISOC)
 int dump_CE_register(struct ol_softc *scn)
 {
-	A_UINT32 CE_reg_address = CE7_LOCATION;
-	A_UINT32 CE_reg_values[CE_USEFUL_SIZE>>2];
+	struct hif_pci_softc *sc = scn->hif_sc;
+	A_UINT32 CE_reg_address = CE0_BASE_ADDRESS;
+	A_UINT32 CE_reg_values[8][CE_USEFUL_SIZE>>2];
 	A_UINT32 CE_reg_word_size = CE_USEFUL_SIZE>>2;
-	A_UINT16 i;
+	A_UINT16 i, j;
 
-	if (HIFDiagReadMem(scn->hif_hdl, CE_reg_address,
-		(A_UCHAR*)&CE_reg_values[0],
-		CE_reg_word_size * sizeof(A_UINT32)) != A_OK)
-	{
-		printk(KERN_ERR "Dumping CE register failed!\n");
-		return -EACCES;
+	for(i = 0; i < 8; i++, CE_reg_address += CE_OFFSET) {
+		if (HIFDiagReadMem(scn->hif_hdl, CE_reg_address,
+			(A_UCHAR*)&CE_reg_values[i][0],
+			CE_reg_word_size * sizeof(A_UINT32)) != A_OK)
+		{
+			printk(KERN_ERR "Dumping CE register failed!\n");
+			return -EACCES;
+		}
 	}
 
-	printk("CE7 Register Dump:\n");
-	for (i = 0; i < CE_reg_word_size; i++) {
-		printk("[%02d] : 0x%08X\n", i, CE_reg_values[i]);
+	for (i = 0; i < 8; i++) {
+		printk("CE%d Registers:\n", i);
+		for (j = 0; j < CE_reg_word_size; j++) {
+			printk("0x%08x ", CE_reg_values[i][j]);
+			if (!((j+1)%5) || (CE_reg_word_size - 1) == j)
+				printk("\n");
+		}
+
+		msleep(1);
 	}
+
 	return EOK;
 }
 #endif
@@ -531,6 +542,7 @@ static void ramdump_work_handler(struct work_struct *ramdump)
 		goto out_fail;
 	}
 
+#ifdef DEBUG
 	ret = hif_pci_check_soc_status(ramdump_scn->hif_sc);
 	if (ret)
 		goto out_fail;
@@ -539,16 +551,20 @@ static void ramdump_work_handler(struct work_struct *ramdump)
 	if (ret)
 		goto out_fail;
 
+	dump_CE_debug_register(ramdump_scn->hif_sc);
+#endif
+
 	if (HIFDiagReadMem(ramdump_scn->hif_hdl,
 		host_interest_item_address(ramdump_scn->target_type,
 		offsetof(struct host_interest_s, hi_failure_state)),
 		(A_UCHAR*) &host_interest_address, sizeof(u_int32_t)) != A_OK) {
 		printk(KERN_ERR "HifDiagReadiMem FW Dump Area Pointer failed!\n");
 		dump_CE_register(ramdump_scn);
+		dump_CE_debug_register(ramdump_scn->hif_sc);
 
 		goto out_fail;
 	}
-	printk("Host interest item address: 0x%08X\n", host_interest_address);
+	printk("Host interest item address: 0x%08x\n", host_interest_address);
 
 	/* Get RAM dump memory address and size */
 	if (cnss_get_ramdump_mem(&address, &size)) {
@@ -585,6 +601,12 @@ out_fail:
 }
 
 static DECLARE_WORK(ramdump_work, ramdump_work_handler);
+
+void schedule_ramdump_work(struct ol_softc *scn)
+{
+	ramdump_scn = scn;
+	schedule_work(&ramdump_work);
+}
 #endif
 
 #define REGISTER_DUMP_LEN_MAX   60
@@ -697,8 +719,7 @@ void ol_target_failure(void *instance, A_STATUS status)
 
 #if defined(QCA_WIFI_2_0) && !defined(QCA_WIFI_ISOC) && defined(CONFIG_CNSS)
 	/* Collect the RAM dump through a workqueue */
-	ramdump_scn = scn;
-	schedule_work(&ramdump_work);
+	schedule_ramdump_work(scn);
 #endif
 
 	return;
@@ -1060,6 +1081,7 @@ int ol_target_coredump(void *inst, void *memoryBlock, u_int32_t blockLength)
 			} else {
 				printk(KERN_ERR "Could not read dump section!\n");
 				dump_CE_register(scn);
+				dump_CE_debug_register(scn->hif_sc);
 				ret = -EACCES;
 				break; /* Could not read the section */
 			}
diff --git a/CORE/SERVICES/BMI/ol_fw.h b/CORE/SERVICES/BMI/ol_fw.h
index f15e2d3b501f..4b81a01005ab 100644
--- a/CORE/SERVICES/BMI/ol_fw.h
+++ b/CORE/SERVICES/BMI/ol_fw.h
@@ -62,7 +62,7 @@
 #define AXI_LOCATION            0x000a0000
 #define AXI_SIZE                0x00018000
 
-#define CE7_LOCATION            0x00036000
+#define CE_OFFSET               0x00000400
 #define CE_USEFUL_SIZE          0x00000058
 
 #define TOTAL_DUMP_SIZE         0x00200000
@@ -72,6 +72,7 @@ int ol_target_coredump(void *instance, void* memoryBlock,
                         u_int32_t blockLength);
 int ol_diag_read(struct ol_softc *scn, u_int8_t* buffer,
                  u_int32_t pos, size_t count);
+void schedule_ramdump_work(struct ol_softc *scn);
 #endif
 int ol_download_firmware(struct ol_softc *scn);
 int ol_configure_target(struct ol_softc *scn);
diff --git a/CORE/SERVICES/HIF/PCIe/ar6320def.h b/CORE/SERVICES/HIF/PCIe/ar6320def.h
index bdaaa574e126..e644920448bc 100644
--- a/CORE/SERVICES/HIF/PCIe/ar6320def.h
+++ b/CORE/SERVICES/HIF/PCIe/ar6320def.h
@@ -217,6 +217,37 @@
 #define AR6320_SOC_CHIP_ID_VERSION_LSB                  18
 #define AR6320_SOC_CHIP_ID_REVISION_MASK                0x00000f00
 #define AR6320_SOC_CHIP_ID_REVISION_LSB                 8
+#define AR6320_SOC_POWER_REG_OFFSET                     0x0000010c
+
+/* Copy Engine Debug */
+#define AR6320_WLAN_DEBUG_INPUT_SEL_OFFSET              0x0000010c
+#define AR6320_WLAN_DEBUG_INPUT_SEL_SRC_MSB             3
+#define AR6320_WLAN_DEBUG_INPUT_SEL_SRC_LSB             0
+#define AR6320_WLAN_DEBUG_INPUT_SEL_SRC_MASK            0x0000000f
+#define AR6320_WLAN_DEBUG_CONTROL_OFFSET                0x00000108
+#define AR6320_WLAN_DEBUG_CONTROL_ENABLE_MSB            0
+#define AR6320_WLAN_DEBUG_CONTROL_ENABLE_LSB            0
+#define AR6320_WLAN_DEBUG_CONTROL_ENABLE_MASK           0x00000001
+#define AR6320_WLAN_DEBUG_OUT_OFFSET                    0x00000110
+#define AR6320_WLAN_DEBUG_OUT_DATA_MSB                  19
+#define AR6320_WLAN_DEBUG_OUT_DATA_LSB                  0
+#define AR6320_WLAN_DEBUG_OUT_DATA_MASK                 0x000fffff
+#define AR6320_AMBA_DEBUG_BUS_OFFSET                    0x0000011c
+#define AR6320_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB        13
+#define AR6320_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB        8
+#define AR6320_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK       0x00003f00
+#define AR6320_AMBA_DEBUG_BUS_SEL_MSB                   4
+#define AR6320_AMBA_DEBUG_BUS_SEL_LSB                   0
+#define AR6320_AMBA_DEBUG_BUS_SEL_MASK                  0x0000001f
+#define AR6320_CE_WRAPPER_DEBUG_OFFSET                  0x0008
+#define AR6320_CE_WRAPPER_DEBUG_SEL_MSB                 5
+#define AR6320_CE_WRAPPER_DEBUG_SEL_LSB                 0
+#define AR6320_CE_WRAPPER_DEBUG_SEL_MASK                0x0000003f
+#define AR6320_CE_DEBUG_OFFSET                          0x0054
+#define AR6320_CE_DEBUG_SEL_MSB                         5
+#define AR6320_CE_DEBUG_SEL_LSB                         0
+#define AR6320_CE_DEBUG_SEL_MASK                        0x0000003f
+/* End */
 
 #define AR6320_PCIE_INTR_CE_MASK(n)                    (AR6320_PCIE_INTR_CE0_MASK << (n))
 #define AR6320_DRAM_BASE_ADDRESS                       AR6320_TARG_DRAM_START
@@ -440,7 +471,34 @@ struct targetdef_s ar6320_targetdef = {
     .d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK =   AR6320_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK,
     .d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB =    AR6320_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB,
     .d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB =    AR6320_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB,
-
+    .d_WLAN_DEBUG_INPUT_SEL_OFFSET =           AR6320_WLAN_DEBUG_INPUT_SEL_OFFSET,
+    .d_WLAN_DEBUG_INPUT_SEL_SRC_MSB =          AR6320_WLAN_DEBUG_INPUT_SEL_SRC_MSB,
+    .d_WLAN_DEBUG_INPUT_SEL_SRC_LSB =          AR6320_WLAN_DEBUG_INPUT_SEL_SRC_LSB,
+    .d_WLAN_DEBUG_INPUT_SEL_SRC_MASK =         AR6320_WLAN_DEBUG_INPUT_SEL_SRC_MASK,
+    .d_WLAN_DEBUG_CONTROL_OFFSET =             AR6320_WLAN_DEBUG_CONTROL_OFFSET,
+    .d_WLAN_DEBUG_CONTROL_ENABLE_MSB =         AR6320_WLAN_DEBUG_CONTROL_ENABLE_MSB,
+    .d_WLAN_DEBUG_CONTROL_ENABLE_LSB =         AR6320_WLAN_DEBUG_CONTROL_ENABLE_LSB,
+    .d_WLAN_DEBUG_CONTROL_ENABLE_MASK =        AR6320_WLAN_DEBUG_CONTROL_ENABLE_MASK,
+    .d_WLAN_DEBUG_OUT_OFFSET =                 AR6320_WLAN_DEBUG_OUT_OFFSET,
+    .d_WLAN_DEBUG_OUT_DATA_MSB =               AR6320_WLAN_DEBUG_OUT_DATA_MSB,
+    .d_WLAN_DEBUG_OUT_DATA_LSB =               AR6320_WLAN_DEBUG_OUT_DATA_LSB,
+    .d_WLAN_DEBUG_OUT_DATA_MASK =              AR6320_WLAN_DEBUG_OUT_DATA_MASK,
+    .d_AMBA_DEBUG_BUS_OFFSET =                 AR6320_AMBA_DEBUG_BUS_OFFSET,
+    .d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB =     AR6320_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB,
+    .d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB =     AR6320_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB,
+    .d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK =    AR6320_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK,
+    .d_AMBA_DEBUG_BUS_SEL_MSB =                AR6320_AMBA_DEBUG_BUS_SEL_MSB,
+    .d_AMBA_DEBUG_BUS_SEL_LSB =                AR6320_AMBA_DEBUG_BUS_SEL_LSB,
+    .d_AMBA_DEBUG_BUS_SEL_MASK =               AR6320_AMBA_DEBUG_BUS_SEL_MASK,
+    .d_CE_WRAPPER_DEBUG_OFFSET =               AR6320_CE_WRAPPER_DEBUG_OFFSET,
+    .d_CE_WRAPPER_DEBUG_SEL_MSB =              AR6320_CE_WRAPPER_DEBUG_SEL_MSB,
+    .d_CE_WRAPPER_DEBUG_SEL_LSB =              AR6320_CE_WRAPPER_DEBUG_SEL_LSB,
+    .d_CE_WRAPPER_DEBUG_SEL_MASK =             AR6320_CE_WRAPPER_DEBUG_SEL_MASK,
+    .d_CE_DEBUG_OFFSET =                       AR6320_CE_DEBUG_OFFSET,
+    .d_CE_DEBUG_SEL_MSB =                      AR6320_CE_DEBUG_SEL_MSB,
+    .d_CE_DEBUG_SEL_LSB =                      AR6320_CE_DEBUG_SEL_LSB,
+    .d_CE_DEBUG_SEL_MASK =                     AR6320_CE_DEBUG_SEL_MASK,
+    .d_SOC_POWER_REG_OFFSET =                  AR6320_SOC_POWER_REG_OFFSET,
     .d_PCIE_INTR_CAUSE_ADDRESS =               AR6320_PCIE_INTR_CAUSE_ADDRESS,
     .d_SOC_RESET_CONTROL_ADDRESS =             AR6320_SOC_RESET_CONTROL_ADDRESS,
     .d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK = AR6320_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK,
diff --git a/CORE/SERVICES/HIF/PCIe/ar6320v2def.h b/CORE/SERVICES/HIF/PCIe/ar6320v2def.h
index 4df34dd8a51e..516e68ff8cb9 100644
--- a/CORE/SERVICES/HIF/PCIe/ar6320v2def.h
+++ b/CORE/SERVICES/HIF/PCIe/ar6320v2def.h
@@ -216,6 +216,37 @@
 #define AR6320V2_SOC_CHIP_ID_VERSION_LSB                  18
 #define AR6320V2_SOC_CHIP_ID_REVISION_MASK                0x00000f00
 #define AR6320V2_SOC_CHIP_ID_REVISION_LSB                 8
+#define AR6320V2_SOC_POWER_REG_OFFSET                     0x0000010c
+
+/* Copy Engine Debug */
+#define AR6320V2_WLAN_DEBUG_INPUT_SEL_OFFSET              0x0000010c
+#define AR6320V2_WLAN_DEBUG_INPUT_SEL_SRC_MSB             3
+#define AR6320V2_WLAN_DEBUG_INPUT_SEL_SRC_LSB             0
+#define AR6320V2_WLAN_DEBUG_INPUT_SEL_SRC_MASK            0x0000000f
+#define AR6320V2_WLAN_DEBUG_CONTROL_OFFSET                0x00000108
+#define AR6320V2_WLAN_DEBUG_CONTROL_ENABLE_MSB            0
+#define AR6320V2_WLAN_DEBUG_CONTROL_ENABLE_LSB            0
+#define AR6320V2_WLAN_DEBUG_CONTROL_ENABLE_MASK           0x00000001
+#define AR6320V2_WLAN_DEBUG_OUT_OFFSET                    0x00000110
+#define AR6320V2_WLAN_DEBUG_OUT_DATA_MSB                  19
+#define AR6320V2_WLAN_DEBUG_OUT_DATA_LSB                  0
+#define AR6320V2_WLAN_DEBUG_OUT_DATA_MASK                 0x000fffff
+#define AR6320V2_AMBA_DEBUG_BUS_OFFSET                    0x0000011c
+#define AR6320V2_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB        13
+#define AR6320V2_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB        8
+#define AR6320V2_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK       0x00003f00
+#define AR6320V2_AMBA_DEBUG_BUS_SEL_MSB                   4
+#define AR6320V2_AMBA_DEBUG_BUS_SEL_LSB                   0
+#define AR6320V2_AMBA_DEBUG_BUS_SEL_MASK                  0x0000001f
+#define AR6320V2_CE_WRAPPER_DEBUG_OFFSET                  0x0008
+#define AR6320V2_CE_WRAPPER_DEBUG_SEL_MSB                 5
+#define AR6320V2_CE_WRAPPER_DEBUG_SEL_LSB                 0
+#define AR6320V2_CE_WRAPPER_DEBUG_SEL_MASK                0x0000003f
+#define AR6320V2_CE_DEBUG_OFFSET                          0x0054
+#define AR6320V2_CE_DEBUG_SEL_MSB                         5
+#define AR6320V2_CE_DEBUG_SEL_LSB                         0
+#define AR6320V2_CE_DEBUG_SEL_MASK                        0x0000003f
+/* End */
 
 #define AR6320V2_PCIE_INTR_CE_MASK(n)                    (AR6320V2_PCIE_INTR_CE0_MASK << (n))
 #define AR6320V2_DRAM_BASE_ADDRESS                       AR6320V2_TARG_DRAM_START
@@ -437,7 +468,34 @@ struct targetdef_s ar6320v2_targetdef = {
     .d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK =   AR6320V2_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK,
     .d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB =    AR6320V2_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB,
     .d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB =    AR6320V2_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB,
-
+    .d_WLAN_DEBUG_INPUT_SEL_OFFSET =           AR6320V2_WLAN_DEBUG_INPUT_SEL_OFFSET,
+    .d_WLAN_DEBUG_INPUT_SEL_SRC_MSB =          AR6320V2_WLAN_DEBUG_INPUT_SEL_SRC_MSB,
+    .d_WLAN_DEBUG_INPUT_SEL_SRC_LSB =          AR6320V2_WLAN_DEBUG_INPUT_SEL_SRC_LSB,
+    .d_WLAN_DEBUG_INPUT_SEL_SRC_MASK =         AR6320V2_WLAN_DEBUG_INPUT_SEL_SRC_MASK,
+    .d_WLAN_DEBUG_CONTROL_OFFSET =             AR6320V2_WLAN_DEBUG_CONTROL_OFFSET,
+    .d_WLAN_DEBUG_CONTROL_ENABLE_MSB =         AR6320V2_WLAN_DEBUG_CONTROL_ENABLE_MSB,
+    .d_WLAN_DEBUG_CONTROL_ENABLE_LSB =         AR6320V2_WLAN_DEBUG_CONTROL_ENABLE_LSB,
+    .d_WLAN_DEBUG_CONTROL_ENABLE_MASK =        AR6320V2_WLAN_DEBUG_CONTROL_ENABLE_MASK,
+    .d_WLAN_DEBUG_OUT_OFFSET =                 AR6320V2_WLAN_DEBUG_OUT_OFFSET,
+    .d_WLAN_DEBUG_OUT_DATA_MSB =               AR6320V2_WLAN_DEBUG_OUT_DATA_MSB,
+    .d_WLAN_DEBUG_OUT_DATA_LSB =               AR6320V2_WLAN_DEBUG_OUT_DATA_LSB,
+    .d_WLAN_DEBUG_OUT_DATA_MASK =              AR6320V2_WLAN_DEBUG_OUT_DATA_MASK,
+    .d_AMBA_DEBUG_BUS_OFFSET =                 AR6320V2_AMBA_DEBUG_BUS_OFFSET,
+    .d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB =     AR6320V2_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB,
+    .d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB =     AR6320V2_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB,
+    .d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK =    AR6320V2_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK,
+    .d_AMBA_DEBUG_BUS_SEL_MSB =                AR6320V2_AMBA_DEBUG_BUS_SEL_MSB,
+    .d_AMBA_DEBUG_BUS_SEL_LSB =                AR6320V2_AMBA_DEBUG_BUS_SEL_LSB,
+    .d_AMBA_DEBUG_BUS_SEL_MASK =               AR6320V2_AMBA_DEBUG_BUS_SEL_MASK,
+    .d_CE_WRAPPER_DEBUG_OFFSET =               AR6320V2_CE_WRAPPER_DEBUG_OFFSET,
+    .d_CE_WRAPPER_DEBUG_SEL_MSB =              AR6320V2_CE_WRAPPER_DEBUG_SEL_MSB,
+    .d_CE_WRAPPER_DEBUG_SEL_LSB =              AR6320V2_CE_WRAPPER_DEBUG_SEL_LSB,
+    .d_CE_WRAPPER_DEBUG_SEL_MASK =             AR6320V2_CE_WRAPPER_DEBUG_SEL_MASK,
+    .d_CE_DEBUG_OFFSET =                       AR6320V2_CE_DEBUG_OFFSET,
+    .d_CE_DEBUG_SEL_MSB =                      AR6320V2_CE_DEBUG_SEL_MSB,
+    .d_CE_DEBUG_SEL_LSB =                      AR6320V2_CE_DEBUG_SEL_LSB,
+    .d_CE_DEBUG_SEL_MASK =                     AR6320V2_CE_DEBUG_SEL_MASK,
+    .d_SOC_POWER_REG_OFFSET =                  AR6320V2_SOC_POWER_REG_OFFSET,
     .d_PCIE_INTR_CAUSE_ADDRESS =               AR6320V2_PCIE_INTR_CAUSE_ADDRESS,
     .d_SOC_RESET_CONTROL_ADDRESS =             AR6320V2_SOC_RESET_CONTROL_ADDRESS,
     .d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK = AR6320V2_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK,
diff --git a/CORE/SERVICES/HIF/PCIe/if_pci.c b/CORE/SERVICES/HIF/PCIe/if_pci.c
index cccd9f64221e..90e1f71ed4fb 100644
--- a/CORE/SERVICES/HIF/PCIe/if_pci.c
+++ b/CORE/SERVICES/HIF/PCIe/if_pci.c
@@ -36,6 +36,7 @@
 #include "hif_msg_based.h"
 #include "hif_pci.h"
 #include "copy_engine_api.h"
+#include "copy_engine_internal.h"
 #include "bmi_msg.h" /* TARGET_TYPE_ */
 #include "regtable.h"
 #include "ol_fw.h"
@@ -374,12 +375,117 @@ int hif_pci_check_soc_status(struct hif_pci_softc *sc)
         timeout_count += 100;
     }
 
-    /* Check BAR + 0x10c register for SoC internal bus issues */
-    val = A_PCI_READ32(sc->mem + 0x10c);
-    printk("BAR + 0x10c is %08x\n", val);
+    /* Check Power register for SoC internal bus issues */
+    val = A_PCI_READ32(sc->mem + RTC_SOC_BASE_ADDRESS + SOC_POWER_REG_OFFSET);
+    printk("Power register is %08x\n", val);
+
     return EOK;
 }
 
+void dump_CE_debug_register(struct hif_pci_softc *sc)
+{
+    struct HIF_CE_state *hif_state = (struct HIF_CE_state *)sc->hif_device;
+    A_target_id_t targid = hif_state->targid;
+    void __iomem *mem = sc->mem;
+    u_int32_t val, i, j;
+    u_int32_t wrapper_idx[] = {1, 2, 3, 4, 5, 6, 8, 9};
+    u_int32_t ce_base;
+
+    A_TARGET_ACCESS_BEGIN(targid);
+
+    /* DEBUG_INPUT_SEL_SRC = 0x6 */
+    val = A_PCI_READ32(mem + GPIO_BASE_ADDRESS + WLAN_DEBUG_INPUT_SEL_OFFSET);
+    val &= ~WLAN_DEBUG_INPUT_SEL_SRC_MASK;
+    val |= WLAN_DEBUG_INPUT_SEL_SRC_SET(0x6);
+    A_PCI_WRITE32(mem + GPIO_BASE_ADDRESS + WLAN_DEBUG_INPUT_SEL_OFFSET, val);
+
+    /* DEBUG_CONTROL_ENABLE = 0x1 */
+    val = A_PCI_READ32(mem + GPIO_BASE_ADDRESS + WLAN_DEBUG_CONTROL_OFFSET);
+    val &= ~WLAN_DEBUG_CONTROL_ENABLE_MASK;
+    val |= WLAN_DEBUG_CONTROL_ENABLE_SET(0x1);
+    A_PCI_WRITE32(mem + GPIO_BASE_ADDRESS + WLAN_DEBUG_CONTROL_OFFSET, val);
+
+    printk("Debug: inputsel: %x dbgctrl: %x\n",
+        A_PCI_READ32(mem + GPIO_BASE_ADDRESS + WLAN_DEBUG_INPUT_SEL_OFFSET),
+        A_PCI_READ32(mem + GPIO_BASE_ADDRESS + WLAN_DEBUG_CONTROL_OFFSET));
+
+    printk("Debug CE: \n");
+    /* Loop CE debug output */
+    /* AMBA_DEBUG_BUS_SEL = 0xc */
+    val = A_PCI_READ32(mem + GPIO_BASE_ADDRESS + AMBA_DEBUG_BUS_OFFSET);
+    val &= ~AMBA_DEBUG_BUS_SEL_MASK;
+    val |= AMBA_DEBUG_BUS_SEL_SET(0xc);
+    A_PCI_WRITE32(mem + GPIO_BASE_ADDRESS + AMBA_DEBUG_BUS_OFFSET, val);
+
+    for (i = 0; i < sizeof(wrapper_idx)/sizeof(A_UINT32); i++) {
+        /* For (i=1,2,3,4,8,9) write CE_WRAPPER_DEBUG_SEL = i */
+        val = A_PCI_READ32(mem + CE_WRAPPER_BASE_ADDRESS +
+                           CE_WRAPPER_DEBUG_OFFSET);
+        val &= ~CE_WRAPPER_DEBUG_SEL_MASK;
+        val |= CE_WRAPPER_DEBUG_SEL_SET(wrapper_idx[i]);
+        A_PCI_WRITE32(mem + CE_WRAPPER_BASE_ADDRESS +
+                      CE_WRAPPER_DEBUG_OFFSET, val);
+
+        printk("ce wrapper: %d amdbg: %x cewdbg: %x\n", wrapper_idx[i],
+            A_PCI_READ32(mem + GPIO_BASE_ADDRESS + AMBA_DEBUG_BUS_OFFSET),
+            A_PCI_READ32(mem + CE_WRAPPER_BASE_ADDRESS +
+                         CE_WRAPPER_DEBUG_OFFSET));
+
+        if (wrapper_idx[i] <= 7) {
+            for (j = 0; j <= 5; j++) {
+                ce_base = CE_BASE_ADDRESS(wrapper_idx[i]);
+                /* For (j=0~5) write CE_DEBUG_SEL = j */
+                val = A_PCI_READ32(mem + ce_base + CE_DEBUG_OFFSET);
+                val &= ~CE_DEBUG_SEL_MASK;
+                val |= CE_DEBUG_SEL_SET(j);
+                A_PCI_WRITE32(mem + ce_base + CE_DEBUG_OFFSET, val);
+
+                /* read (@gpio_athr_wlan_reg) WLAN_DEBUG_OUT_DATA */
+                val = A_PCI_READ32(mem + GPIO_BASE_ADDRESS +
+                                   WLAN_DEBUG_OUT_OFFSET);
+                val = WLAN_DEBUG_OUT_DATA_GET(val);
+
+                printk("    module%d: cedbg: %x out: %x\n", j,
+                    A_PCI_READ32(mem + ce_base + CE_DEBUG_OFFSET), val);
+            }
+        } else {
+            /* read (@gpio_athr_wlan_reg) WLAN_DEBUG_OUT_DATA */
+            val = A_PCI_READ32(mem + GPIO_BASE_ADDRESS + WLAN_DEBUG_OUT_OFFSET);
+            val = WLAN_DEBUG_OUT_DATA_GET(val);
+
+            printk("    out: %x\n", val);
+        }
+
+        msleep(1);
+    }
+
+    printk("Debug PCIe: \n");
+    /* Loop PCIe debug output */
+    /* Write AMBA_DEBUG_BUS_SEL = 0x1c */
+    val = A_PCI_READ32(mem + GPIO_BASE_ADDRESS + AMBA_DEBUG_BUS_OFFSET);
+    val &= ~AMBA_DEBUG_BUS_SEL_MASK;
+    val |= AMBA_DEBUG_BUS_SEL_SET(0x1c);
+    A_PCI_WRITE32(mem + GPIO_BASE_ADDRESS + AMBA_DEBUG_BUS_OFFSET, val);
+
+    for (i = 0; i <= 8; i++) {
+        /* For (i=1~8) write AMBA_DEBUG_BUS_PCIE_DEBUG_SEL = i */
+        val = A_PCI_READ32(mem + GPIO_BASE_ADDRESS + AMBA_DEBUG_BUS_OFFSET);
+        val &= ~AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK;
+        val |= AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_SET(i);
+        A_PCI_WRITE32(mem + GPIO_BASE_ADDRESS + AMBA_DEBUG_BUS_OFFSET, val);
+
+        /* read (@gpio_athr_wlan_reg) WLAN_DEBUG_OUT_DATA */
+        val = A_PCI_READ32(mem + GPIO_BASE_ADDRESS + WLAN_DEBUG_OUT_OFFSET);
+        val = WLAN_DEBUG_OUT_DATA_GET(val);
+
+        printk("amdbg: %x out: %x %x\n",
+            A_PCI_READ32(mem + GPIO_BASE_ADDRESS + WLAN_DEBUG_OUT_OFFSET), val,
+            A_PCI_READ32(mem + GPIO_BASE_ADDRESS + WLAN_DEBUG_OUT_OFFSET));
+    }
+
+    A_TARGET_ACCESS_END(targid);
+}
+
 /*
  * Handler for a per-engine interrupt on a PARTICULAR CE.
  * This is used in cases where each CE has a private
diff --git a/CORE/SERVICES/HIF/PCIe/if_pci.h b/CORE/SERVICES/HIF/PCIe/if_pci.h
index d3955f7f0e5a..38ee30e9569c 100644
--- a/CORE/SERVICES/HIF/PCIe/if_pci.h
+++ b/CORE/SERVICES/HIF/PCIe/if_pci.h
@@ -122,6 +122,7 @@ extern void pktlogmod_exit(void *context);
 #endif
 
 int hif_pci_check_soc_status(struct hif_pci_softc *sc);
+void dump_CE_debug_register(struct hif_pci_softc *sc);
 
 /*
  * A firmware interrupt to the Host is indicated by the
diff --git a/CORE/SERVICES/HIF/PCIe/regtable.h b/CORE/SERVICES/HIF/PCIe/regtable.h
index b530188f5f8c..87c8d8be0643 100644
--- a/CORE/SERVICES/HIF/PCIe/regtable.h
+++ b/CORE/SERVICES/HIF/PCIe/regtable.h
@@ -189,7 +189,35 @@ typedef struct targetdef_s {
     u_int32_t d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK;
     u_int32_t d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB;
     u_int32_t d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB;
+    u_int32_t d_WLAN_DEBUG_INPUT_SEL_OFFSET;
+    u_int32_t d_WLAN_DEBUG_INPUT_SEL_SRC_MSB;
+    u_int32_t d_WLAN_DEBUG_INPUT_SEL_SRC_LSB;
+    u_int32_t d_WLAN_DEBUG_INPUT_SEL_SRC_MASK;
+    u_int32_t d_WLAN_DEBUG_CONTROL_OFFSET;
+    u_int32_t d_WLAN_DEBUG_CONTROL_ENABLE_MSB;
+    u_int32_t d_WLAN_DEBUG_CONTROL_ENABLE_LSB;
+    u_int32_t d_WLAN_DEBUG_CONTROL_ENABLE_MASK;
+    u_int32_t d_WLAN_DEBUG_OUT_OFFSET;
+    u_int32_t d_WLAN_DEBUG_OUT_DATA_MSB;
+    u_int32_t d_WLAN_DEBUG_OUT_DATA_LSB;
+    u_int32_t d_WLAN_DEBUG_OUT_DATA_MASK;
+    u_int32_t d_AMBA_DEBUG_BUS_OFFSET;
+    u_int32_t d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB;
+    u_int32_t d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB;
+    u_int32_t d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK;
+    u_int32_t d_AMBA_DEBUG_BUS_SEL_MSB;
+    u_int32_t d_AMBA_DEBUG_BUS_SEL_LSB;
+    u_int32_t d_AMBA_DEBUG_BUS_SEL_MASK;
+    u_int32_t d_CE_WRAPPER_DEBUG_OFFSET;
+    u_int32_t d_CE_WRAPPER_DEBUG_SEL_MSB;
+    u_int32_t d_CE_WRAPPER_DEBUG_SEL_LSB;
+    u_int32_t d_CE_WRAPPER_DEBUG_SEL_MASK;
+    u_int32_t d_CE_DEBUG_OFFSET;
+    u_int32_t d_CE_DEBUG_SEL_MSB;
+    u_int32_t d_CE_DEBUG_SEL_LSB;
+    u_int32_t d_CE_DEBUG_SEL_MASK;
     /* end */
+    u_int32_t d_SOC_POWER_REG_OFFSET;
     u_int32_t d_PCIE_INTR_CAUSE_ADDRESS;
     u_int32_t d_SOC_RESET_CONTROL_ADDRESS;
     u_int32_t d_SOC_RESET_CONTROL_PCIE_RST_SHORT_OVRD_MASK;
@@ -311,6 +339,7 @@ typedef struct targetdef_s {
 /* misc */
 #define SR_WR_INDEX_ADDRESS                      (sc->targetdef->d_SR_WR_INDEX_ADDRESS)
 #define DST_WATERMARK_ADDRESS                    (sc->targetdef->d_DST_WATERMARK_ADDRESS)
+#define SOC_POWER_REG_OFFSET                     (sc->targetdef->d_SOC_POWER_REG_OFFSET)
 /* end */
 
 /* htt_rx.c */
@@ -388,6 +417,33 @@ typedef struct targetdef_s {
 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK      (sc->targetdef->d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK)
 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB       (sc->targetdef->d_CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB)
 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB       (sc->targetdef->d_CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB)
+#define WLAN_DEBUG_INPUT_SEL_OFFSET              (sc->targetdef->d_WLAN_DEBUG_INPUT_SEL_OFFSET)
+#define WLAN_DEBUG_INPUT_SEL_SRC_MSB             (sc->targetdef->d_WLAN_DEBUG_INPUT_SEL_SRC_MSB)
+#define WLAN_DEBUG_INPUT_SEL_SRC_LSB             (sc->targetdef->d_WLAN_DEBUG_INPUT_SEL_SRC_LSB)
+#define WLAN_DEBUG_INPUT_SEL_SRC_MASK            (sc->targetdef->d_WLAN_DEBUG_INPUT_SEL_SRC_MASK)
+#define WLAN_DEBUG_CONTROL_OFFSET                (sc->targetdef->d_WLAN_DEBUG_CONTROL_OFFSET)
+#define WLAN_DEBUG_CONTROL_ENABLE_MSB            (sc->targetdef->d_WLAN_DEBUG_CONTROL_ENABLE_MSB)
+#define WLAN_DEBUG_CONTROL_ENABLE_LSB            (sc->targetdef->d_WLAN_DEBUG_CONTROL_ENABLE_LSB)
+#define WLAN_DEBUG_CONTROL_ENABLE_MASK           (sc->targetdef->d_WLAN_DEBUG_CONTROL_ENABLE_MASK)
+#define WLAN_DEBUG_OUT_OFFSET                    (sc->targetdef->d_WLAN_DEBUG_OUT_OFFSET)
+#define WLAN_DEBUG_OUT_DATA_MSB                  (sc->targetdef->d_WLAN_DEBUG_OUT_DATA_MSB)
+#define WLAN_DEBUG_OUT_DATA_LSB                  (sc->targetdef->d_WLAN_DEBUG_OUT_DATA_LSB)
+#define WLAN_DEBUG_OUT_DATA_MASK                 (sc->targetdef->d_WLAN_DEBUG_OUT_DATA_MASK)
+#define AMBA_DEBUG_BUS_OFFSET                    (sc->targetdef->d_AMBA_DEBUG_BUS_OFFSET)
+#define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB        (sc->targetdef->d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MSB)
+#define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB        (sc->targetdef->d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB)
+#define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK       (sc->targetdef->d_AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK)
+#define AMBA_DEBUG_BUS_SEL_MSB                   (sc->targetdef->d_AMBA_DEBUG_BUS_SEL_MSB)
+#define AMBA_DEBUG_BUS_SEL_LSB                   (sc->targetdef->d_AMBA_DEBUG_BUS_SEL_LSB)
+#define AMBA_DEBUG_BUS_SEL_MASK                  (sc->targetdef->d_AMBA_DEBUG_BUS_SEL_MASK)
+#define CE_WRAPPER_DEBUG_OFFSET                  (sc->targetdef->d_CE_WRAPPER_DEBUG_OFFSET)
+#define CE_WRAPPER_DEBUG_SEL_MSB                 (sc->targetdef->d_CE_WRAPPER_DEBUG_SEL_MSB)
+#define CE_WRAPPER_DEBUG_SEL_LSB                 (sc->targetdef->d_CE_WRAPPER_DEBUG_SEL_LSB)
+#define CE_WRAPPER_DEBUG_SEL_MASK                (sc->targetdef->d_CE_WRAPPER_DEBUG_SEL_MASK)
+#define CE_DEBUG_OFFSET                          (sc->targetdef->d_CE_DEBUG_OFFSET)
+#define CE_DEBUG_SEL_MSB                         (sc->targetdef->d_CE_DEBUG_SEL_MSB)
+#define CE_DEBUG_SEL_LSB                         (sc->targetdef->d_CE_DEBUG_SEL_LSB)
+#define CE_DEBUG_SEL_MASK                        (sc->targetdef->d_CE_DEBUG_SEL_MASK)
 /* end */
 
 /* SET macros */
@@ -413,6 +469,20 @@ typedef struct targetdef_s {
 #define CE_CTRL1_DMAX_LENGTH_SET(x)              (((x) << CE_CTRL1_DMAX_LENGTH_LSB) & CE_CTRL1_DMAX_LENGTH_MASK)
 #define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_SET(x)    (((x) << CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB) & CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK)
 #define CE_CTRL1_DST_RING_BYTE_SWAP_EN_SET(x)    (((x) << CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB) & CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK)
+#define WLAN_DEBUG_INPUT_SEL_SRC_GET(x)          (((x) & WLAN_DEBUG_INPUT_SEL_SRC_MASK) >> WLAN_DEBUG_INPUT_SEL_SRC_LSB)
+#define WLAN_DEBUG_INPUT_SEL_SRC_SET(x)          (((x) << WLAN_DEBUG_INPUT_SEL_SRC_LSB) & WLAN_DEBUG_INPUT_SEL_SRC_MASK)
+#define WLAN_DEBUG_CONTROL_ENABLE_GET(x)         (((x) & WLAN_DEBUG_CONTROL_ENABLE_MASK) >> WLAN_DEBUG_CONTROL_ENABLE_LSB)
+#define WLAN_DEBUG_CONTROL_ENABLE_SET(x)         (((x) << WLAN_DEBUG_CONTROL_ENABLE_LSB) & WLAN_DEBUG_CONTROL_ENABLE_MASK)
+#define WLAN_DEBUG_OUT_DATA_GET(x)               (((x) & WLAN_DEBUG_OUT_DATA_MASK) >> WLAN_DEBUG_OUT_DATA_LSB)
+#define WLAN_DEBUG_OUT_DATA_SET(x)               (((x) << WLAN_DEBUG_OUT_DATA_LSB) & WLAN_DEBUG_OUT_DATA_MASK)
+#define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_GET(x)     (((x) & AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK) >> AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB)
+#define AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_SET(x)     (((x) << AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_LSB) & AMBA_DEBUG_BUS_PCIE_DEBUG_SEL_MASK)
+#define AMBA_DEBUG_BUS_SEL_GET(x)                (((x) & AMBA_DEBUG_BUS_SEL_MASK) >> AMBA_DEBUG_BUS_SEL_LSB)
+#define AMBA_DEBUG_BUS_SEL_SET(x)                (((x) << AMBA_DEBUG_BUS_SEL_LSB) & AMBA_DEBUG_BUS_SEL_MASK)
+#define CE_WRAPPER_DEBUG_SEL_GET(x)              (((x) & CE_WRAPPER_DEBUG_SEL_MASK) >> CE_WRAPPER_DEBUG_SEL_LSB)
+#define CE_WRAPPER_DEBUG_SEL_SET(x)              (((x) << CE_WRAPPER_DEBUG_SEL_LSB) & CE_WRAPPER_DEBUG_SEL_MASK)
+#define CE_DEBUG_SEL_GET(x)                      (((x) & CE_DEBUG_SEL_MASK) >> CE_DEBUG_SEL_LSB)
+#define CE_DEBUG_SEL_SET(x)                      (((x) << CE_DEBUG_SEL_LSB) & CE_DEBUG_SEL_MASK)
 /* end */
 
 typedef struct hostdef_s {