diff options
| author | Viswanadha Raju Thotakura <viswanad@codeaurora.org> | 2016-05-26 11:28:41 -0700 |
|---|---|---|
| committer | Kyle Yan <kyan@codeaurora.org> | 2016-06-03 14:48:27 -0700 |
| commit | 93dd7f4807bd7a2252dae2b3c19e2adbfe5a7242 (patch) | |
| tree | 3ab995108e88a29876aa85c7eb156bbede444155 | |
| parent | 42ab5394f4dfd680e5e742194e0b0687140360b5 (diff) | |
ARM: dts: msm: Add missing clocks for csid on msmcobalt
Add missing clocks for csid node. Update csiphytimer clock
to 269MHz.
CRs-Fixed: 1021009
Change-Id: I9242849d4da84007d1384de0e3e2bf63e7f57ea9
Signed-off-by: Viswanadha Raju Thotakura <viswanad@codeaurora.org>
| -rw-r--r-- | arch/arm/boot/dts/qcom/msmcobalt-camera.dtsi | 42 |
1 files changed, 27 insertions, 15 deletions
diff --git a/arch/arm/boot/dts/qcom/msmcobalt-camera.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-camera.dtsi index a17fc360e2d0..574f1e33f36d 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-camera.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-camera.dtsi @@ -48,7 +48,7 @@ "csi_src_clk", "csi_clk", "cphy_csid_clk", "csiphy_timer_src_clk", "csiphy_timer_clk", "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk"; - qcom,clock-rates = <0 0 0 0 0 0 256000000 0 0 200000000 0 + qcom,clock-rates = <0 0 0 0 0 0 256000000 0 0 269333333 0 0 256000000 0>; }; @@ -79,7 +79,7 @@ "csi_src_clk", "csi_clk", "cphy_csid_clk", "csiphy_timer_src_clk", "csiphy_timer_clk", "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk"; - qcom,clock-rates = <0 0 0 0 0 0 256000000 0 0 200000000 0 + qcom,clock-rates = <0 0 0 0 0 0 256000000 0 0 269333333 0 0 256000000 0>; }; @@ -110,7 +110,7 @@ "csi_src_clk", "csi_clk", "cphy_csid_clk", "csiphy_timer_src_clk", "csiphy_timer_clk", "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk"; - qcom,clock-rates = <0 0 0 0 0 0 256000000 0 0 200000000 0 + qcom,clock-rates = <0 0 0 0 0 0 256000000 0 0 269333333 0 0 256000000 0>; }; @@ -138,14 +138,17 @@ <&clock_mmss clk_mmss_camss_csiphy0_clk>, <&clock_mmss clk_mmss_camss_csi0_ahb_clk>, <&clock_mmss clk_mmss_camss_csi0rdi_clk>, - <&clock_mmss clk_mmss_camss_csi0pix_clk>; + <&clock_mmss clk_mmss_camss_csi0pix_clk>, + <&clock_mmss clk_mmss_camss_cphy_csid0_clk>, + <&clock_mmss clk_csiphy_clk_src>; clock-names = "mnoc_maxi", "mnoc_ahb", "bmic_smmu_ahb", "bmic_smmu_axi", "camss_ahb_clk", "camss_top_ahb_clk", "ispif_ahb_clk", "csi_src_clk", "csi_clk", "csi_phy_clk", "csi_ahb_clk", "csi_rdi_clk", - "csi_pix_clk"; - qcom,clock-rates = <0 0 0 0 0 0 0 256000000 0 0 0 0 0>; + "csi_pix_clk", "cphy_csid_clk", "cphy_clk_src"; + qcom,clock-rates = <0 0 0 0 0 0 0 256000000 0 0 0 0 0 0 + 256000000>; status = "ok"; }; @@ -173,14 +176,17 @@ <&clock_mmss clk_mmss_camss_csiphy1_clk>, <&clock_mmss clk_mmss_camss_csi1_ahb_clk>, <&clock_mmss clk_mmss_camss_csi1rdi_clk>, - <&clock_mmss clk_mmss_camss_csi1pix_clk>; + <&clock_mmss clk_mmss_camss_csi1pix_clk>, + <&clock_mmss clk_mmss_camss_cphy_csid1_clk>, + <&clock_mmss clk_csiphy_clk_src>; clock-names = "mnoc_maxi", "mnoc_ahb", "bmic_smmu_ahb", "bmic_smmu_axi", "camss_ahb_clk", "camss_top_ahb_clk", "ispif_ahb_clk", "csi_src_clk", "csi_clk", "csi_phy_clk", "csi_ahb_clk", "csi_rdi_clk", - "csi_pix_clk"; - qcom,clock-rates = <0 0 0 0 0 0 0 256000000 0 0 0 0 0>; + "csi_pix_clk", "cphy_csid_clk", "cphy_clk_src"; + qcom,clock-rates = <0 0 0 0 0 0 0 256000000 0 0 0 0 0 0 + 256000000>; }; qcom,csid@ca30800 { @@ -207,14 +213,17 @@ <&clock_mmss clk_mmss_camss_csiphy2_clk>, <&clock_mmss clk_mmss_camss_csi2_ahb_clk>, <&clock_mmss clk_mmss_camss_csi2rdi_clk>, - <&clock_mmss clk_mmss_camss_csi2pix_clk>; + <&clock_mmss clk_mmss_camss_csi2pix_clk>, + <&clock_mmss clk_mmss_camss_cphy_csid2_clk>, + <&clock_mmss clk_csiphy_clk_src>; clock-names = "mnoc_maxi", "mnoc_ahb", "bmic_smmu_ahb", "bmic_smmu_axi", "camss_ahb_clk", "camss_top_ahb_clk", "ispif_ahb_clk", "csi_src_clk", "csi_clk", "csi_phy_clk", "csi_ahb_clk", "csi_rdi_clk", - "csi_pix_clk"; - qcom,clock-rates = <0 0 0 0 0 0 0 256000000 0 0 0 0 0>; + "csi_pix_clk", "cphy_csid_clk", "cphy_clk_src"; + qcom,clock-rates = <0 0 0 0 0 0 0 256000000 0 0 0 0 0 0 + 256000000>; }; qcom,csid@ca30c00 { @@ -240,14 +249,17 @@ <&clock_mmss clk_mmss_camss_csi3_clk>, <&clock_mmss clk_mmss_camss_csi3_ahb_clk>, <&clock_mmss clk_mmss_camss_csi3rdi_clk>, - <&clock_mmss clk_mmss_camss_csi3pix_clk>; + <&clock_mmss clk_mmss_camss_csi3pix_clk>, + <&clock_mmss clk_mmss_camss_cphy_csid1_clk>, + <&clock_mmss clk_csiphy_clk_src>; clock-names = "mnoc_maxi", "mnoc_ahb", "bmic_smmu_ahb", "bmic_smmu_axi", "camss_ahb_clk", "camss_top_ahb_clk", "ispif_ahb_clk", "csi_src_clk", "csi_clk", "csi_ahb_clk", "csi_rdi_clk", - "csi_pix_clk"; - qcom,clock-rates = <0 0 0 0 0 0 0 256000000 0 0 0 0>; + "csi_pix_clk", "cphy_csid_clk", "cphy_clk_src"; + qcom,clock-rates = <0 0 0 0 0 0 0 256000000 0 0 0 0 0 + 256000000>; }; qcom,cam_smmu { compatible = "qcom,msm-cam-smmu"; |