diff options
| author | Huaibin Yang <huaibiny@codeaurora.org> | 2014-12-22 14:18:35 -0800 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-23 20:41:38 -0700 |
| commit | 92b7d7917b67c8deb51bcd5df7e3fa9dd6087176 (patch) | |
| tree | 3d91797520c4e0ec17e27a3d4f7ca15ebd94bb95 | |
| parent | 452b3b89ff9048c66a9436afc6e4cd3f581db02f (diff) | |
clk: mdss: fix pll 1 leakage issue by calling power down sequence
To completely shutdown pll 1, power down sequence has to be
called. This is different from the old sequence where disable pll
sequence acturally turn off pll.
Change-Id: Ia8b9adb8f78241e34420c0966c3c25b7684b1262
Signed-off-by: Huaibin Yang <huaibiny@codeaurora.org>
| -rw-r--r-- | drivers/clk/msm/mdss/mdss-dsi-20nm-pll-util.c | 31 |
1 files changed, 15 insertions, 16 deletions
diff --git a/drivers/clk/msm/mdss/mdss-dsi-20nm-pll-util.c b/drivers/clk/msm/mdss/mdss-dsi-20nm-pll-util.c index 81d517059bb7..b3b334f18e61 100644 --- a/drivers/clk/msm/mdss/mdss-dsi-20nm-pll-util.c +++ b/drivers/clk/msm/mdss/mdss-dsi-20nm-pll-util.c @@ -500,6 +500,19 @@ void __dsi_pll_disable(void __iomem *pll_base) MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_RESETSM_CNTRL3, 0x06); } +static void pll_20nm_config_powerdown(void __iomem *pll_base) +{ + if (!pll_base) { + pr_err("Invalid pll base.\n"); + return; + } + + MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_SYS_CLK_CTRL, 0x00); + MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_CMN_MODE, 0x01); + MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_PLL_VCOTAIL_EN, 0x82); + MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_BIAS_EN_CLKBUFLR_EN, 0x02); +} + static int dsi_pll_enable(struct clk *c) { int i, rc; @@ -522,7 +535,7 @@ static int dsi_pll_enable(struct clk *c) } /* Disable PLL1 to avoid current leakage while toggling MDSS GDSC */ if (dsi_pll_res->pll_1_base) - __dsi_pll_disable(dsi_pll_res->pll_1_base); + pll_20nm_config_powerdown(dsi_pll_res->pll_1_base); if (rc) { mdss_pll_resource_enable(dsi_pll_res, false); @@ -533,20 +546,6 @@ static int dsi_pll_enable(struct clk *c) return rc; } - -static void pll_20nm_config_powerdown(void __iomem *pll_base) -{ - if (!pll_base) { - pr_err("Invalid pll base.\n"); - return; - } - - MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_SYS_CLK_CTRL, 0x00); - MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_CMN_MODE, 0x01); - MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_PLL_VCOTAIL_EN, 0x82); - MDSS_PLL_REG_W(pll_base, MMSS_DSI_PHY_PLL_BIAS_EN_CLKBUFLR_EN, 0x02); -} - static void dsi_pll_disable(struct clk *c) { struct dsi_pll_vco_clk *vco = to_vco_clk(c); @@ -564,7 +563,7 @@ static void dsi_pll_disable(struct clk *c) /* Disable PLL1 to avoid current leakage while toggling MDSS GDSC */ if (dsi_pll_res->pll_1_base) - __dsi_pll_disable(dsi_pll_res->pll_1_base); + pll_20nm_config_powerdown(dsi_pll_res->pll_1_base); pll_20nm_config_powerdown(dsi_pll_res->pll_base); |