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authorLinux Build Service Account <lnxbuild@localhost>2017-04-04 03:08:01 -0700
committerGerrit - the friendly Code Review server <code-review@localhost>2017-04-04 03:08:01 -0700
commit90a7e429e6aec17731203ef8f7643bc457b74b23 (patch)
treec1f2a6dfb192e065c9cc5d78c8e273fadb06621d
parent7d517eef8f04864b7ff9def0c82276c4d45391e7 (diff)
parent82f1f37ce1a4e376a66395dd094cca13dbefcf25 (diff)
Merge "clk: msm: clock-gcc-8998: Update parent src for qup_spi/uart_apps clocks"
-rw-r--r--drivers/clk/msm/clock-gcc-8998.c14
1 files changed, 9 insertions, 5 deletions
diff --git a/drivers/clk/msm/clock-gcc-8998.c b/drivers/clk/msm/clock-gcc-8998.c
index f9d713a22c76..b1c8cc43769f 100644
--- a/drivers/clk/msm/clock-gcc-8998.c
+++ b/drivers/clk/msm/clock-gcc-8998.c
@@ -42,6 +42,7 @@ static void __iomem *virt_dbgbase;
#define gpll0_out_main_source_val 1
#define gpll0_ao_source_val 1
#define gpll4_out_main_source_val 5
+#define gpll0_early_div_source_val 6
#define FIXDIV(div) (div ? (2 * (div) - 1) : (0))
@@ -164,6 +165,7 @@ static struct pll_vote_clk gpll0_ao = {
};
DEFINE_EXT_CLK(gpll0_out_main, &gpll0.c);
+DEFINE_EXT_CLK(gpll0_early_div, &gpll0.c);
static struct local_vote_clk gcc_mmss_gpll0_clk = {
.cbcr_reg = GCC_APCS_CLOCK_BRANCH_ENA_VOTE_1,
@@ -328,7 +330,7 @@ static struct clk_freq_tbl ftbl_blsp_qup_spi_apps_clk_src[] = {
F( 960000, cxo_clk_src, 10, 1, 2),
F( 4800000, cxo_clk_src, 4, 0, 0),
F( 9600000, cxo_clk_src, 2, 0, 0),
- F( 15000000, gpll0_out_main, 10, 1, 4),
+ F( 15000000, gpll0_early_div, 5, 1, 4),
F( 19200000, cxo_clk_src, 1, 0, 0),
F( 25000000, gpll0_out_main, 12, 1, 2),
F( 50000000, gpll0_out_main, 12, 0, 0),
@@ -496,10 +498,10 @@ static struct rcg_clk blsp1_qup6_spi_apps_clk_src = {
};
static struct clk_freq_tbl ftbl_blsp_uart_apps_clk_src[] = {
- F( 3686400, gpll0_out_main, 1, 96, 15625),
- F( 7372800, gpll0_out_main, 1, 192, 15625),
- F( 14745600, gpll0_out_main, 1, 384, 15625),
- F( 16000000, gpll0_out_main, 5, 2, 15),
+ F( 3686400, gpll0_early_div, 1, 192, 15625),
+ F( 7372800, gpll0_early_div, 1, 384, 15625),
+ F( 14745600, gpll0_early_div, 1, 768, 15625),
+ F( 16000000, gpll0_early_div, 1, 4, 75),
F( 19200000, cxo_clk_src, 1, 0, 0),
F( 24000000, gpll0_out_main, 5, 1, 5),
F( 32000000, gpll0_out_main, 1, 4, 75),
@@ -2732,6 +2734,8 @@ static int msm_gcc_8998_probe(struct platform_device *pdev)
if (ret)
return ret;
+ gpll0_early_div.c.rate = 300000000;
+
ret = enable_rpm_scaling();
if (ret < 0)
return ret;