diff options
| author | Rajesh Bondugula <rajeshb@codeaurora.org> | 2017-01-12 17:22:14 -0800 |
|---|---|---|
| committer | Gerrit - the friendly Code Review server <code-review@localhost> | 2017-01-30 11:25:28 -0800 |
| commit | 9064d219488e48bef62febcaf5f2cfebf74ad63d (patch) | |
| tree | 351acf18645557d456f8600d043da24c9c64634b | |
| parent | 24377df2b44eb5d8b11571be6fb18fbc9c24b600 (diff) | |
ARM: dts: msm: Update csi source clk in msm8998
Set phy/csid clk to 274290000 MAX clk in SVS mode in MSM8998.
This is needed to handle higher data rate from sensor and to
achieve dynamic clock scaling based on data rate.
Crs-Fixed: 1111089
Change-Id: If148f5a53ce4b151e4e7a2afe0352e5dba4a85ad
Signed-off-by: Rajesh Bondugula <rajeshb@codeaurora.org>
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-camera.dtsi | 20 | ||||
| -rw-r--r-- | arch/arm/boot/dts/qcom/msm8998-v2-camera.dtsi | 14 |
2 files changed, 17 insertions, 17 deletions
diff --git a/arch/arm/boot/dts/qcom/msm8998-camera.dtsi b/arch/arm/boot/dts/qcom/msm8998-camera.dtsi index f8dae210bc4e..c35ea886408d 100644 --- a/arch/arm/boot/dts/qcom/msm8998-camera.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-camera.dtsi @@ -51,8 +51,8 @@ "csi_src_clk", "csi_clk", "cphy_csid_clk", "csiphy_timer_src_clk", "csiphy_timer_clk", "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk"; - qcom,clock-rates = <0 0 0 0 0 0 256000000 0 0 200000000 0 - 0 256000000 0>; + qcom,clock-rates = <0 0 0 0 0 0 274290000 0 0 200000000 0 + 0 274290000 0>; status = "ok"; }; @@ -86,8 +86,8 @@ "csi_src_clk", "csi_clk", "cphy_csid_clk", "csiphy_timer_src_clk", "csiphy_timer_clk", "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk"; - qcom,clock-rates = <0 0 0 0 0 0 256000000 0 0 200000000 0 - 0 256000000 0>; + qcom,clock-rates = <0 0 0 0 0 0 274290000 0 0 200000000 0 + 0 274290000 0>; status = "ok"; }; @@ -121,8 +121,8 @@ "csi_src_clk", "csi_clk", "cphy_csid_clk", "csiphy_timer_src_clk", "csiphy_timer_clk", "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk"; - qcom,clock-rates = <0 0 0 0 0 0 256000000 0 0 200000000 0 - 0 256000000 0>; + qcom,clock-rates = <0 0 0 0 0 0 274290000 0 0 200000000 0 + 0 274290000 0>; status = "ok"; }; @@ -159,7 +159,7 @@ "ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src", "csi_clk", "csi_ahb_clk", "csi_rdi_clk", "csi_pix_clk", "cphy_csid_clk"; - qcom,clock-rates = <0 0 0 0 0 0 0 256000000 256000000 + qcom,clock-rates = <0 0 0 0 0 0 0 274290000 274290000 0 0 0 0 0>; status = "ok"; }; @@ -197,7 +197,7 @@ "ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src", "csi_clk", "csi_ahb_clk", "csi_rdi_clk", "csi_pix_clk", "cphy_csid_clk"; - qcom,clock-rates = <0 0 0 0 0 0 0 256000000 256000000 + qcom,clock-rates = <0 0 0 0 0 0 0 274290000 274290000 0 0 0 0 0>; status = "ok"; }; @@ -235,7 +235,7 @@ "ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src", "csi_clk", "csi_ahb_clk", "csi_rdi_clk", "csi_pix_clk", "cphy_csid_clk"; - qcom,clock-rates = <0 0 0 0 0 0 0 256000000 256000000 + qcom,clock-rates = <0 0 0 0 0 0 0 274290000 274290000 0 0 0 0 0>; status = "ok"; }; @@ -273,7 +273,7 @@ "ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src", "csi_clk", "csi_ahb_clk", "csi_rdi_clk", "csi_pix_clk", "cphy_csid_clk"; - qcom,clock-rates = <0 0 0 0 0 0 0 256000000 256000000 + qcom,clock-rates = <0 0 0 0 0 0 0 274290000 274290000 0 0 0 0 0>; status = "ok"; }; diff --git a/arch/arm/boot/dts/qcom/msm8998-v2-camera.dtsi b/arch/arm/boot/dts/qcom/msm8998-v2-camera.dtsi index fdc452a47a46..93da11e66799 100644 --- a/arch/arm/boot/dts/qcom/msm8998-v2-camera.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-v2-camera.dtsi @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -42,8 +42,8 @@ "csi_src_clk", "csi_clk", "cphy_csid_clk", "csiphy_timer_src_clk", "csiphy_timer_clk", "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk"; - qcom,clock-rates = <0 0 0 0 0 0 256000000 0 0 200000000 0 - 0 256000000 0>; + qcom,clock-rates = <0 0 0 0 0 0 274290000 0 0 200000000 0 + 0 274290000 0>; status = "ok"; }; @@ -77,8 +77,8 @@ "csi_src_clk", "csi_clk", "cphy_csid_clk", "csiphy_timer_src_clk", "csiphy_timer_clk", "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk"; - qcom,clock-rates = <0 0 0 0 0 0 256000000 0 0 200000000 0 - 0 256000000 0>; + qcom,clock-rates = <0 0 0 0 0 0 274290000 0 0 200000000 0 + 0 274290000 0>; status = "ok"; }; @@ -112,8 +112,8 @@ "csi_src_clk", "csi_clk", "cphy_csid_clk", "csiphy_timer_src_clk", "csiphy_timer_clk", "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk"; - qcom,clock-rates = <0 0 0 0 0 0 256000000 0 0 200000000 0 - 0 256000000 0>; + qcom,clock-rates = <0 0 0 0 0 0 274290000 0 0 200000000 0 + 0 274290000 0>; status = "ok"; }; |