diff options
| author | Pavankumar Kondeti <pkondeti@codeaurora.org> | 2016-12-22 11:47:49 +0530 |
|---|---|---|
| committer | Pavankumar Kondeti <pkondeti@codeaurora.org> | 2017-01-02 08:59:08 +0530 |
| commit | 8bbfeb52e0bc7fc731da4118f9eb6781f2d48b57 (patch) | |
| tree | 4bf5e63ef31710d7208fd30f12cd2f2f3858fc86 | |
| parent | 613765204325713b6419765d5d27e7b8f633ef59 (diff) | |
ARM: dts: msm: Add CPU efficiency values for sdm630
The values passed from device tree overrides the default values
defined in the topology code.
Change-Id: I323b43a228f9bc61cad079d1ac76940af209a1c5
Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
| -rw-r--r-- | arch/arm/boot/dts/qcom/sdm630.dtsi | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/qcom/sdm630.dtsi b/arch/arm/boot/dts/qcom/sdm630.dtsi index a82979d63244..dac5ed313333 100644 --- a/arch/arm/boot/dts/qcom/sdm630.dtsi +++ b/arch/arm/boot/dts/qcom/sdm630.dtsi @@ -48,7 +48,7 @@ reg = <0x0 0x100>; enable-method = "psci"; qcom,limits-info = <&mitigation_profile0>; - efficiency = <1024>; + efficiency = <1126>; next-level-cache = <&L2_1>; L2_1: l2-cache { compatible = "arm,arch-cache"; @@ -72,7 +72,7 @@ reg = <0x0 0x101>; enable-method = "psci"; qcom,limits-info = <&mitigation_profile1>; - efficiency = <1024>; + efficiency = <1126>; next-level-cache = <&L2_1>; L1_I_101: l1-icache { compatible = "arm,arch-cache"; @@ -90,7 +90,7 @@ reg = <0x0 0x102>; enable-method = "psci"; qcom,limits-info = <&mitigation_profile2>; - efficiency = <1024>; + efficiency = <1126>; next-level-cache = <&L2_1>; L1_I_102: l1-icache { compatible = "arm,arch-cache"; @@ -108,7 +108,7 @@ reg = <0x0 0x103>; enable-method = "psci"; qcom,limits-info = <&mitigation_profile3>; - efficiency = <1024>; + efficiency = <1126>; next-level-cache = <&L2_1>; L1_I_103: l1-icache { compatible = "arm,arch-cache"; |