Merge "drm/sde: only set split registers for DSI interfaces"

5 files changed, 16 insertions, 15 deletions

diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h b/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h
index d9fcec60693d..91501a2efd20 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_defs.h
@@ -198,12 +198,12 @@ enum dsi_video_traffic_mode {
  * @h_sync_width:     HSYNC width in pixels.
  * @h_front_porch:    Horizontal fron porch in pixels.
  * @h_skew:
- * @h_sync_polarity:  Polarity of HSYNC (false is active low).
+ * @h_sync_polarity:  Polarity of HSYNC (false is active high).
  * @v_active:         Active height of one frame in lines.
  * @v_back_porch:     Vertical back porch in lines.
  * @v_sync_width:     VSYNC width in lines.
  * @v_front_porch:    Vertical front porch in lines.
- * @v_sync_polarity:  Polarity of VSYNC (false is active low).
+ * @v_sync_polarity:  Polarity of VSYNC (false is active high).
  * @refresh_rate:     Refresh rate in Hz.
  */
 struct dsi_mode_info {
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_drm.c b/drivers/gpu/drm/msm/dsi-staging/dsi_drm.c
index 995cda97a2f0..c34713a13332 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_drm.c
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_drm.c
@@ -56,6 +56,10 @@ static void convert_to_dsi_mode(const struct drm_display_mode *drm_mode,
 		dsi_mode->flags |= DSI_MODE_FLAG_DFPS;
 	if (msm_needs_vblank_pre_modeset(drm_mode))
 		dsi_mode->flags |= DSI_MODE_FLAG_VBLANK_PRE_MODESET;
+	dsi_mode->timing.h_sync_polarity =
+		(drm_mode->flags & DRM_MODE_FLAG_PHSYNC) ? false : true;
+	dsi_mode->timing.v_sync_polarity =
+		(drm_mode->flags & DRM_MODE_FLAG_PVSYNC) ? false : true;
 }
 
 static void convert_to_drm_mode(const struct dsi_display_mode *dsi_mode,
@@ -87,6 +91,10 @@ static void convert_to_drm_mode(const struct dsi_display_mode *dsi_mode,
 		drm_mode->private_flags |= MSM_MODE_FLAG_SEAMLESS_DYNAMIC_FPS;
 	if (dsi_mode->flags & DSI_MODE_FLAG_VBLANK_PRE_MODESET)
 		drm_mode->private_flags |= MSM_MODE_FLAG_VBLANK_PRE_MODESET;
+	drm_mode->flags |= (dsi_mode->timing.h_sync_polarity) ?
+				DRM_MODE_FLAG_NHSYNC : DRM_MODE_FLAG_PHSYNC;
+	drm_mode->flags |= (dsi_mode->timing.v_sync_polarity) ?
+				DRM_MODE_FLAG_NVSYNC : DRM_MODE_FLAG_PVSYNC;
 
 	drm_mode_set_name(drm_mode);
 }
diff --git a/drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c b/drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c
index e61ff97d2ca4..0b6ee302e231 100644
--- a/drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c
@@ -73,12 +73,6 @@ static void drm_mode_to_intf_timing_params(
 	timing->underflow_clr = 0xff;
 	timing->hsync_skew = mode->hskew;
 
-	/* DSI controller cannot handle active-low sync signals. */
-	if (vid_enc->hw_intf->cap->type == INTF_DSI) {
-		timing->hsync_polarity = 0;
-		timing->vsync_polarity = 0;
-	}
-
 	/*
 	 * For edp only:
 	 * DISPLAY_V_START = (VBP * HCYCLE) + HBP
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_intf.c b/drivers/gpu/drm/msm/sde/sde_hw_intf.c
index 3b34719e9971..042b0ee7909a 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_intf.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_intf.c
@@ -157,13 +157,8 @@ static void sde_hw_intf_setup_timing_engine(struct sde_hw_intf *ctx,
 	display_hctl = (hsync_end_x << 16) | hsync_start_x;
 
 	den_polarity = 0;
-	if (ctx->cap->type == INTF_HDMI) {
-		hsync_polarity = p->yres >= 720 ? 0 : 1;
-		vsync_polarity = p->yres >= 720 ? 0 : 1;
-	} else {
-		hsync_polarity = 0;
-		vsync_polarity = 0;
-	}
+	hsync_polarity = p->hsync_polarity;
+	vsync_polarity = p->vsync_polarity;
 	polarity_ctl = (den_polarity << 2) | /*  DEN Polarity  */
 		(vsync_polarity << 1) | /* VSYNC Polarity */
 		(hsync_polarity << 0);  /* HSYNC Polarity */
diff --git a/drivers/gpu/drm/msm/sde/sde_hw_top.c b/drivers/gpu/drm/msm/sde/sde_hw_top.c
index 1a5d469e6e7e..d6d2e41ff5aa 100644
--- a/drivers/gpu/drm/msm/sde/sde_hw_top.c
+++ b/drivers/gpu/drm/msm/sde/sde_hw_top.c
@@ -42,6 +42,10 @@ static void sde_hw_setup_split_pipe(struct sde_hw_mdp *mdp,
 	if (!mdp || !cfg)
 		return;
 
+	/* The SPLIT registers are only for DSI interfaces */
+	if ((cfg->intf != INTF_1) && (cfg->intf != INTF_2))
+		return;
+
 	if (cfg->en) {
 		if (cfg->mode == INTF_MODE_CMD) {
 			lower_pipe = FLD_SPLIT_DISPLAY_CMD;