diff options
| author | Linux Build Service Account <lnxbuild@localhost> | 2017-03-31 21:24:23 -0700 |
|---|---|---|
| committer | Gerrit - the friendly Code Review server <code-review@localhost> | 2017-03-31 21:24:23 -0700 |
| commit | 8a493b9beea7589d8efa436152eb8ee3ea83cdfe (patch) | |
| tree | 18464b4bb6171e6f2a25073f37b0f1b92fed5638 | |
| parent | 84d6e9ea9f8cea799901c18649f512cd954d8aa3 (diff) | |
| parent | 9ef3d654f27ba9c3d17cb7465f7f79880996d929 (diff) | |
Merge "qcom: smb-lib: Disable HW trigger when forcing sink-only mode"
| -rw-r--r-- | drivers/power/supply/qcom/smb-lib.c | 16 | ||||
| -rw-r--r-- | drivers/power/supply/qcom/smb-reg.h | 2 |
2 files changed, 18 insertions, 0 deletions
diff --git a/drivers/power/supply/qcom/smb-lib.c b/drivers/power/supply/qcom/smb-lib.c index 6dceff89311d..539473df3b9b 100644 --- a/drivers/power/supply/qcom/smb-lib.c +++ b/drivers/power/supply/qcom/smb-lib.c @@ -2487,6 +2487,22 @@ int smblib_set_prop_typec_power_role(struct smb_charger *chg, return -EINVAL; } + if (power_role == UFP_EN_CMD_BIT) { + /* disable PBS workaround when forcing sink mode */ + rc = smblib_write(chg, TM_IO_DTEST4_SEL, 0x0); + if (rc < 0) { + smblib_err(chg, "Couldn't write to TM_IO_DTEST4_SEL rc=%d\n", + rc); + } + } else { + /* restore it back to 0xA5 */ + rc = smblib_write(chg, TM_IO_DTEST4_SEL, 0xA5); + if (rc < 0) { + smblib_err(chg, "Couldn't write to TM_IO_DTEST4_SEL rc=%d\n", + rc); + } + } + rc = smblib_masked_write(chg, TYPE_C_INTRPT_ENB_SOFTWARE_CTRL_REG, TYPEC_POWER_ROLE_CMD_MASK, power_role); if (rc < 0) { diff --git a/drivers/power/supply/qcom/smb-reg.h b/drivers/power/supply/qcom/smb-reg.h index f7c13390d477..b79060094cf6 100644 --- a/drivers/power/supply/qcom/smb-reg.h +++ b/drivers/power/supply/qcom/smb-reg.h @@ -1019,6 +1019,8 @@ enum { #define CFG_BUCKBOOST_FREQ_SELECT_BUCK_REG (MISC_BASE + 0xA0) #define CFG_BUCKBOOST_FREQ_SELECT_BOOST_REG (MISC_BASE + 0xA1) +#define TM_IO_DTEST4_SEL (MISC_BASE + 0xE9) + /* CHGR FREQ Peripheral registers */ #define FREQ_CLK_DIV_REG (CHGR_FREQ_BASE + 0x50) |