diff options
| author | Osvaldo Banuelos <osvaldob@codeaurora.org> | 2016-09-01 10:42:39 -0700 |
|---|---|---|
| committer | Gerrit - the friendly Code Review server <code-review@localhost> | 2016-09-02 17:59:26 -0700 |
| commit | 86d9f4aea4db4411ec7b56e2500fdb27868aeb9a (patch) | |
| tree | 4b615c868a4b0b542e91ad6a12ac0b65e3f01f55 | |
| parent | 2fbd5cd8f906fba5ddb6dac4db057815a3bb4191 (diff) | |
ARM: dts: msm: increase VDD_APC CPR LowSVS/SVS ceiling for MSMCOBALTV2
Increase VDD_APC LowSVS and SVS ceiling voltages to match the
latest hardware characterization guidelines.
CRs-Fixed: 1062365
Change-Id: I9a8439d1f38a328a08590d2c5b11a611f11b4836
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
| -rw-r--r-- | arch/arm/boot/dts/qcom/msmcobalt-v2.dtsi | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/arch/arm/boot/dts/qcom/msmcobalt-v2.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-v2.dtsi index 52c80460d26a..69d186512f89 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-v2.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-v2.dtsi @@ -244,15 +244,15 @@ qcom,cpr-voltage-ceiling = /* Speed bin 0 */ - <688000 688000 688000 688000 688000 - 688000 688000 688000 756000 756000 - 756000 828000 828000 828000 828000 + <828000 828000 828000 828000 828000 + 828000 828000 828000 828000 828000 + 828000 828000 828000 828000 828000 828000 828000 828000 952000 952000 1056000 1056000>, /* Speed bin 1 */ - <688000 688000 688000 688000 688000 - 688000 688000 688000 756000 756000 - 756000 828000 828000 828000 828000 + <828000 828000 828000 828000 828000 + 828000 828000 828000 828000 828000 + 828000 828000 828000 828000 828000 828000 828000 828000 952000 952000 1056000 1056000>; @@ -389,16 +389,16 @@ qcom,cpr-voltage-ceiling = /* Speed bin 0 */ - <688000 688000 688000 688000 688000 - 688000 688000 688000 756000 756000 - 756000 756000 828000 828000 828000 + <828000 828000 828000 828000 828000 + 828000 828000 828000 828000 828000 + 828000 828000 828000 828000 828000 828000 828000 828000 828000 828000 952000 952000 952000 1056000 1056000 1056000 1056000 1056000 1056000 1056000>, /* Speed bin 1 */ - <688000 688000 688000 688000 688000 - 688000 688000 688000 756000 756000 - 756000 756000 828000 828000 828000 + <828000 828000 828000 828000 828000 + 828000 828000 828000 828000 828000 + 828000 828000 828000 828000 828000 828000 828000 828000 828000 828000 952000 952000 952000 1056000 1056000 1056000>; |