diff options
| author | Yan He <yanhe@codeaurora.org> | 2015-05-29 15:15:43 -0700 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-22 11:16:11 -0700 |
| commit | 8133fd6791848129b656f4b963d7898f1dcf9864 (patch) | |
| tree | 8b2410e9863c76619b8eb25052f3a2e984663bc7 | |
| parent | 6a7032666d7ee5894fe7f2872f216e02935c20ad (diff) | |
msm: ep_pcie: update retry counters and intervals
Update retry counters and intervals for PCIe PHY init and PCIe link
training to accommodate various hosts.
Change-Id: I767de1f08580137559e974c0ef90273ccf5f4b76
Signed-off-by: Yan He <yanhe@codeaurora.org>
| -rw-r--r-- | drivers/platform/msm/ep_pcie/ep_pcie_com.h | 28 | ||||
| -rw-r--r-- | drivers/platform/msm/ep_pcie/ep_pcie_core.c | 4 |
2 files changed, 16 insertions, 16 deletions
diff --git a/drivers/platform/msm/ep_pcie/ep_pcie_com.h b/drivers/platform/msm/ep_pcie/ep_pcie_com.h index 131e0eaa31e1..6c20f7ec0842 100644 --- a/drivers/platform/msm/ep_pcie/ep_pcie_com.h +++ b/drivers/platform/msm/ep_pcie/ep_pcie_com.h @@ -86,20 +86,20 @@ #define PCIE20_PLR_IATU_LTAR 0x918 #define PCIE20_PLR_IATU_UTAR 0x91c -#define PERST_TIMEOUT_US_MIN 5000 -#define PERST_TIMEOUT_US_MAX 5100 -#define PERST_CHECK_MAX_COUNT 2000 -#define LINK_UP_TIMEOUT_US_MIN 5000 -#define LINK_UP_TIMEOUT_US_MAX 5100 -#define LINK_UP_CHECK_MAX_COUNT 2000 -#define BME_TIMEOUT_US_MIN 5000 -#define BME_TIMEOUT_US_MAX 5100 -#define BME_CHECK_MAX_COUNT 6000 -#define PHY_STABILIZATION_DELAY_US_MIN 995 -#define PHY_STABILIZATION_DELAY_US_MAX 1005 -#define REFCLK_STABILIZATION_DELAY_US_MIN 995 -#define REFCLK_STABILIZATION_DELAY_US_MAX 1005 -#define PHY_READY_TIMEOUT_COUNT 10000 +#define PERST_TIMEOUT_US_MIN 1000 +#define PERST_TIMEOUT_US_MAX 1000 +#define PERST_CHECK_MAX_COUNT 30000 +#define LINK_UP_TIMEOUT_US_MIN 1000 +#define LINK_UP_TIMEOUT_US_MAX 1000 +#define LINK_UP_CHECK_MAX_COUNT 30000 +#define BME_TIMEOUT_US_MIN 1000 +#define BME_TIMEOUT_US_MAX 1000 +#define BME_CHECK_MAX_COUNT 30000 +#define PHY_STABILIZATION_DELAY_US_MIN 1000 +#define PHY_STABILIZATION_DELAY_US_MAX 1000 +#define REFCLK_STABILIZATION_DELAY_US_MIN 1000 +#define REFCLK_STABILIZATION_DELAY_US_MAX 1000 +#define PHY_READY_TIMEOUT_COUNT 30000 #define XMLH_LINK_UP 0x400 #define MAX_PROP_SIZE 32 diff --git a/drivers/platform/msm/ep_pcie/ep_pcie_core.c b/drivers/platform/msm/ep_pcie/ep_pcie_core.c index df2da1139ad1..0d933ff9cb5d 100644 --- a/drivers/platform/msm/ep_pcie/ep_pcie_core.c +++ b/drivers/platform/msm/ep_pcie/ep_pcie_core.c @@ -1034,7 +1034,7 @@ int ep_pcie_core_enable_endpoint(enum ep_pcie_options opt) if (ep_pcie_phy_is_ready(dev)) break; retries++; - if (retries % 10 == 0) + if (retries % 100 == 0) EP_PCIE_DBG(dev, "PCIe V%d: current number of PHY retries:%d.\n", dev->rev, retries); @@ -1069,7 +1069,7 @@ int ep_pcie_core_enable_endpoint(enum ep_pcie_options opt) usleep_range(LINK_UP_TIMEOUT_US_MIN, LINK_UP_TIMEOUT_US_MAX); val = readl_relaxed(dev->elbi + PCIE20_ELBI_SYS_STTS); retries++; - if (retries % 5 == 0) + if (retries % 100 == 0) EP_PCIE_DBG(dev, "PCIe V%d: LTSSM_STATE:0x%x.\n", dev->rev, (val >> 0xC) & 0x3f); } while ((!(val & XMLH_LINK_UP) || |