diff options
| author | Amit Nischal <anischal@codeaurora.org> | 2017-02-22 11:42:24 +0530 |
|---|---|---|
| committer | Amit Nischal <anischal@codeaurora.org> | 2017-02-24 17:42:52 +0530 |
| commit | 7d08417887c461e20f60a6f48827804dc272fcc2 (patch) | |
| tree | 6e06061da05b04e1278821c9cfa21657d7317de0 | |
| parent | d72462d943ee499ac17a485bdacca60c0db31c04 (diff) | |
clk: msm: clock-mmss-8998: Update frequency plan for byte/pixel clock
The byte and pixel clock max frequency level has been updated to new
values, so update the same.
Change-Id: I5451c03b29a3b28e7363923896bc4836dbcd6e61
Signed-off-by: Amit Nischal <anischal@codeaurora.org>
| -rw-r--r-- | drivers/clk/msm/clock-mmss-8998.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/clk/msm/clock-mmss-8998.c b/drivers/clk/msm/clock-mmss-8998.c index 1661878fc650..6ebb3ed6ed91 100644 --- a/drivers/clk/msm/clock-mmss-8998.c +++ b/drivers/clk/msm/clock-mmss-8998.c @@ -664,8 +664,8 @@ static struct rcg_clk byte0_clk_src = { .parent = &ext_byte0_clk_src.c, .ops = &clk_ops_byte_multiparent, .flags = CLKFLAG_NO_RATE_CACHE, - VDD_DIG_FMAX_MAP3(LOWER, 150000000, LOW, 240000000, - NOMINAL, 357140000), + VDD_DIG_FMAX_MAP3(LOWER, 131250000, LOW, 210000000, + NOMINAL, 312500000), CLK_INIT(byte0_clk_src.c), }, }; @@ -681,8 +681,8 @@ static struct rcg_clk byte1_clk_src = { .parent = &ext_byte1_clk_src.c, .ops = &clk_ops_byte_multiparent, .flags = CLKFLAG_NO_RATE_CACHE, - VDD_DIG_FMAX_MAP3(LOWER, 150000000, LOW, 240000000, - NOMINAL, 357140000), + VDD_DIG_FMAX_MAP3(LOWER, 131250000, LOW, 210000000, + NOMINAL, 312500000), CLK_INIT(byte1_clk_src.c), }, }; @@ -722,8 +722,8 @@ static struct rcg_clk pclk0_clk_src = { .parent = &ext_pclk0_clk_src.c, .ops = &clk_ops_pixel_multiparent, .flags = CLKFLAG_NO_RATE_CACHE, - VDD_DIG_FMAX_MAP3(LOWER, 184000000, LOW, 295000000, - NOMINAL, 610000000), + VDD_DIG_FMAX_MAP3(LOWER, 175000000, LOW, 280000000, + NOMINAL, 416670000), CLK_INIT(pclk0_clk_src.c), }, }; @@ -739,8 +739,8 @@ static struct rcg_clk pclk1_clk_src = { .parent = &ext_pclk1_clk_src.c, .ops = &clk_ops_pixel_multiparent, .flags = CLKFLAG_NO_RATE_CACHE, - VDD_DIG_FMAX_MAP3(LOWER, 184000000, LOW, 295000000, - NOMINAL, 610000000), + VDD_DIG_FMAX_MAP3(LOWER, 175000000, LOW, 280000000, + NOMINAL, 416670000), CLK_INIT(pclk1_clk_src.c), }, }; |