diff options
| author | Yan He <yanhe@codeaurora.org> | 2015-05-29 18:13:21 -0700 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-22 11:16:14 -0700 |
| commit | 7adcccb4d1a7591ff5045f484fcb10f5e2e77483 (patch) | |
| tree | 20aadac8ff2bad4dfb3f795fa0b1e593be4c581c | |
| parent | 1e5604cf01f8626f447ca4419345e015b939bc4f (diff) | |
msm: ep_pcie: support multiple link training options
Add the support to trigger link training based on PCIe PHY version.
Change-Id: I4c765797d8e8adf5c15effae95da350a0d8ec0c3
Signed-off-by: Yan He <yanhe@codeaurora.org>
| -rw-r--r-- | drivers/platform/msm/ep_pcie/ep_pcie_com.h | 1 | ||||
| -rw-r--r-- | drivers/platform/msm/ep_pcie/ep_pcie_core.c | 5 |
2 files changed, 5 insertions, 1 deletions
diff --git a/drivers/platform/msm/ep_pcie/ep_pcie_com.h b/drivers/platform/msm/ep_pcie/ep_pcie_com.h index df9a3cd8acb1..6bb268f358aa 100644 --- a/drivers/platform/msm/ep_pcie/ep_pcie_com.h +++ b/drivers/platform/msm/ep_pcie/ep_pcie_com.h @@ -42,6 +42,7 @@ #define PCIE20_PARF_AXI_MSTR_RD_HALT_NO_WRITES 0x1A4 #define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x1A8 #define PCIE20_PARF_Q2A_FLUSH 0x1AC +#define PCIE20_PARF_LTSSM 0x1B0 #define PCIE20_PARF_DEVICE_TYPE 0x1000 #define PCIE20_ELBI_VERSION 0x00 diff --git a/drivers/platform/msm/ep_pcie/ep_pcie_core.c b/drivers/platform/msm/ep_pcie/ep_pcie_core.c index 9be5b7d7b634..021a5eba29b8 100644 --- a/drivers/platform/msm/ep_pcie/ep_pcie_core.c +++ b/drivers/platform/msm/ep_pcie/ep_pcie_core.c @@ -1061,7 +1061,10 @@ int ep_pcie_core_enable_endpoint(enum ep_pcie_options opt) ep_pcie_config_inbound_iatu(dev); /* enable link training */ - ep_pcie_write_mask(dev->elbi + PCIE20_ELBI_SYS_CTRL, 0, BIT(0)); + if (dev->phy_rev >= 3) + ep_pcie_write_mask(dev->parf + PCIE20_PARF_LTSSM, 0, BIT(8)); + else + ep_pcie_write_mask(dev->elbi + PCIE20_ELBI_SYS_CTRL, 0, BIT(0)); EP_PCIE_DBG(dev, "PCIe V%d: check if link is up\n", dev->rev); |