diff options
| author | Linux Build Service Account <lnxbuild@localhost> | 2016-12-22 17:53:42 -0700 |
|---|---|---|
| committer | Linux Build Service Account <lnxbuild@localhost> | 2016-12-22 17:53:42 -0700 |
| commit | 7aa1be414789d169eba3bce5345c4d009e989b6a (patch) | |
| tree | cf4680b7a9e1c26e102207ff4a56427236a76721 | |
| parent | 9982ad3f361c4789b78f8256d77f9506d4ead606 (diff) | |
| parent | ba4fdd9852b5a61b6a22385a9e6cab9ea78346b9 (diff) | |
Promotion of kernel.lnx.4.4-161222.
CRs Change ID Subject
--------------------------------------------------------------------------------------------------------------
1103705 Id95a65cefc25174eaf2bcd9b3d97fd8d3e632adb iio: rradc: Update charger die temperature coefficients
1103814 If51734ae27add47a856ca378faf11e54b81e4dcf ARM: dts: msm: Enable context aware and quirks for A512
1104081 I2a17d95328bef91c4a5dd4dde418296efca44431 sched: Fix out of bounds array access in sched_reset_all
1102981 I69001073af6b72875f6d023a1eb754fe0a0e00a1 ARM: dts: msm: Enable camera for msmfalcon.
1059232 I92ace85ee7fd40c3f33f1b9f7bdd32469d990d84 USB: dwc3-msm: Add support for voting for PM_QOS_LATENCY
1103251 I604a94ed28cb8df389eea8815ba0b279c7b7603c ARM: dts: msm: Update Venus PIL clock voting for MSMFALC
1088153 I3499b2ee5bb1ddb74fc94fa55d3f5a8170d72b98 ARM: dts: msm: Modify BT node for QRD interposer msm8998
1097836 I175d76cd193d649f8b91cdab5000f6e1c66de15e cfg80211: Define macro to indicate support for update co
1085388 I2f083a399b0d433ac7e8fd358f75ec0778d0396a ARM: dts: msm: Disable clock gating on msmfalcon
1094763 Ib132eaa99e0632807124f44c8dd3bc90cf6710b0 ASoC: msm: Add routing controls for hfp, port mixer
1099759 Ib8fc3ed96e4704e71d9224a067fd8d9e88373cf0 drivers: mfd: clean up bootup info logs
1096945 I8fc3f646a0127ec705239be6a7de858a4f805acc wil6210: Block write ioctl to the card by default
1059232 I40a86a062910253401dc4a59f7ae84c518eebb5e ARM: dts: msm: Allow only wfi based on USB irq load for
1102504 Ia995e60b8d8d335239be0a35876d1becfd9a0f3c soc: qcom: glink_pkt: Remove BUG_ON in glink_pkt_write
1088153 Ibc1d54ca18c57a83c08e8a1eafc63e6aeb95f7c4 ARM: dts: msm: Enable blsp1_uart3_hs for QRD interposer
1086571 I70c5ec050f88e23c1d09fe0d19ac34a4a56977a1 ARM: dts: msm: Add battery profile for FG in qrd8998 int
1068294 I510c2fe7f763c8d44c67794c889c687df60398d7 regulator: gfx-ldo: support voltage based regulator oper
1100789 I84a936f834101ba2ad9e354c4d8df6d3c051a2f7 soc: qcom: glink_ssr: Add rx done for received packets
1094973 I98e443e894d81bcd815418f2a79723db14d87ce4 msm: ADSPRPC: Add channel for compute/modem DSP
1097863 Ib55302c8fc9dbf2a4114a793e17f9b2dc9ade37c nl80211: Use different attrs for BSSID and random MAC ad
1096083 I22bc2803d1cfa57777dda41c6d635b60f2740fad ARM: dts: msm: configure wled for mdss on falcon interpo
1097836 I184b8e13bc5f7e2ed21e5337673c6ba82cd2f4fe cfg80211: Add support to update connection parameters
Change-Id: I9b9d04bbef27f5576bd29dde1fe8f9bbcd9c419f
CRs-Fixed: 1094763, 1100789, 1103814, 1103705, 1097863, 1096083, 1094973, 1097836, 1085388, 1099759, 1059232, 1096945, 1103251, 1102504, 1068294, 1088153, 1104081, 1086571, 1102981
32 files changed, 2859 insertions, 141 deletions
diff --git a/Documentation/devicetree/bindings/regulator/msm_gfx_ldo.txt b/Documentation/devicetree/bindings/regulator/msm_gfx_ldo.txt index 890255749704..42c735e26d66 100644 --- a/Documentation/devicetree/bindings/regulator/msm_gfx_ldo.txt +++ b/Documentation/devicetree/bindings/regulator/msm_gfx_ldo.txt @@ -8,7 +8,8 @@ This document describes the bindings that apply for the GFX LDO regulator. - compatible Usage: required Value type: <string> - Definition: should be "qcom,msm8953-gfx-ldo" for MSM8953. + Definition: should be "qcom,msm8953-gfx-ldo" for MSM8953 and + "qcom,msmfalcon-gfx-ldo" for MSMFALCON - reg Usage: required diff --git a/Documentation/devicetree/bindings/usb/msm-ssusb.txt b/Documentation/devicetree/bindings/usb/msm-ssusb.txt index 1c870acbd034..fa6ee8969946 100644 --- a/Documentation/devicetree/bindings/usb/msm-ssusb.txt +++ b/Documentation/devicetree/bindings/usb/msm-ssusb.txt @@ -60,6 +60,8 @@ Optional properties : should point to external connector device, which provide "USB-HOST" cable events. A single phandle may be specified if a single connector device provides both "USB" and "USB-HOST" events. +- qcom,pm-qos-latency: This represents max tolerable CPU latency in microsecs, + which is used as a vote by driver to get max performance in perf mode. Sub nodes: - Sub node for "DWC3- USB3 controller". @@ -84,6 +86,7 @@ Example MSM USB3.0 controller device node : qcom,dwc-usb3-msm-tx-fifo-size = <29696>; qcom,usb-dbm = <&dbm_1p4>; qcom,lpm-to-suspend-delay-ms = <2>; + qcom,pm-qos-latency = <2>; qcom,msm_bus,name = "usb3"; qcom,msm_bus,num_cases = <2>; diff --git a/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-qrd.dts b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-qrd.dts index 6866415c6f35..44c4b74dd696 100644 --- a/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-qrd.dts +++ b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-qrd.dts @@ -146,3 +146,19 @@ }; }; }; + +/ { + qrd_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + + #include "fg-gen3-batterydata-qrd-skuk-4v4-3000mah.dtsi" + }; +}; + +&pmfalcon_fg { + qcom,battery-data = <&qrd_batterydata>; +}; + +&pm2falcon_wled { + qcom,led-strings-list = [00 01]; +}; diff --git a/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-qrd.dtsi b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-qrd.dtsi index 83368136a8b3..dcfb851cd116 100644 --- a/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-qrd.dtsi +++ b/arch/arm/boot/dts/qcom/msm8998-v2.1-interposer-msmfalcon-qrd.dtsi @@ -16,32 +16,29 @@ / { bluetooth: bt_wcn3990 { - status = "disabled"; compatible = "qca,wcn3990"; - qca,bt-vdd-io-supply = <&pmfalcon_l13>; - qca,bt-vdd-xtal-supply = <&pmfalcon_l9>; - qca,bt-vdd-core-supply = <&pmfalcon_l9>; - qca,bt-vdd-pa-supply = <&pmfalcon_l6>; - qca,bt-vdd-ldo-supply = <&pmfalcon_l19>; + qca,bt-vdd-core-supply = <&pmfalcon_l9_pin_ctrl>; + qca,bt-vdd-pa-supply = <&pmfalcon_l6_pin_ctrl>; + qca,bt-vdd-ldo-supply = <&pmfalcon_l19_pin_ctrl>; qca,bt-chip-pwd-supply = <&pm2falcon_bob_pin1>; - clocks = <&clock_gcc clk_rf_clk2>; - clock-names = "rf_clk2"; - - qca,bt-vdd-io-voltage-level = <1800000 1800000>; - qca,bt-vdd-xtal-voltage-level = <1800000 1800000>; - qca,bt-vdd-core-voltage-level = <1800000 1800000>; - qca,bt-vdd-pa-voltage-level = <1304000 1304000>; - qca,bt-vdd-ldo-voltage-level = <3312000 3312000>; + clocks = <&clock_gcc clk_rf_clk1>; + clock-names = "rf_clk1"; + + qca,bt-vdd-core-voltage-level = <1800000 1900000>; + qca,bt-vdd-pa-voltage-level = <1304000 1370000>; + qca,bt-vdd-ldo-voltage-level = <3312000 3400000>; qca,bt-chip-pwd-voltage-level = <3600000 3600000>; - qca,bt-vdd-io-current-level = <1>; /* LPM/PFM */ - qca,bt-vdd-xtal-current-level = <1>; /* LPM/PFM */ qca,bt-vdd-core-current-level = <1>; /* LPM/PFM */ qca,bt-vdd-pa-current-level = <1>; /* LPM/PFM */ qca,bt-vdd-ldo-current-level = <1>; /* LPM/PFM */ }; }; +&blsp1_uart3_hs { + status = "ok"; +}; + &uartblsp2dm1 { status = "ok"; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-camera-sensor-cdp.dtsi b/arch/arm/boot/dts/qcom/msmfalcon-camera-sensor-cdp.dtsi new file mode 100644 index 000000000000..63528e23160a --- /dev/null +++ b/arch/arm/boot/dts/qcom/msmfalcon-camera-sensor-cdp.dtsi @@ -0,0 +1,384 @@ +/* + * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + led_flash0: qcom,camera-flash@0 { + cell-index = <0>; + compatible = "qcom,camera-flash"; + qcom,flash-source = <&pm2falcon_flash0 &pm2falcon_flash1>; + qcom,torch-source = <&pm2falcon_torch0 &pm2falcon_torch1>; + qcom,switch-source = <&pm2falcon_switch0>; + status = "ok"; + }; + + led_flash1: qcom,camera-flash@1 { + cell-index = <1>; + compatible = "qcom,camera-flash"; + qcom,flash-source = <&pm2falcon_flash2>; + qcom,torch-source = <&pm2falcon_torch2>; + qcom,switch-source = <&pm2falcon_switch1>; + status = "ok"; + }; +}; + +&cci { + actuator0: qcom,actuator@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,actuator"; + qcom,cci-master = <0>; + gpios = <&tlmm 50 0>; + qcom,gpio-vaf = <0>; + qcom,gpio-req-tbl-num = <0>; + qcom,gpio-req-tbl-flags = <0>; + qcom,gpio-req-tbl-label = "CAM_VAF"; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_actuator_vaf_active>; + pinctrl-1 = <&cam_actuator_vaf_suspend>; + }; + + actuator1: qcom,actuator@1 { + cell-index = <1>; + reg = <0x1>; + compatible = "qcom,actuator"; + qcom,cci-master = <1>; + gpios = <&tlmm 50 0>; + qcom,gpio-vaf = <0>; + qcom,gpio-req-tbl-num = <0>; + qcom,gpio-req-tbl-flags = <0>; + qcom,gpio-req-tbl-label = "CAM_VAF"; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_actuator_vaf_active>; + pinctrl-1 = <&cam_actuator_vaf_suspend>; + }; + + actuator2: qcom,actuator@2 { + cell-index = <2>; + reg = <0x2>; + compatible = "qcom,actuator"; + qcom,cci-master = <1>; + gpios = <&tlmm 50 0>; + qcom,gpio-vaf = <0>; + qcom,gpio-req-tbl-num = <0>; + qcom,gpio-req-tbl-flags = <0>; + qcom,gpio-req-tbl-label = "CAM_VAF"; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_actuator_vaf_active>; + pinctrl-1 = <&cam_actuator_vaf_suspend>; + }; + + ois0: qcom,ois@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,ois"; + qcom,cci-master = <0>; + gpios = <&tlmm 50 0>; + qcom,gpio-vaf = <0>; + qcom,gpio-req-tbl-num = <0>; + qcom,gpio-req-tbl-flags = <0>; + qcom,gpio-req-tbl-label = "CAM_VAF"; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_actuator_vaf_active>; + pinctrl-1 = <&cam_actuator_vaf_suspend>; + status = "disabled"; + }; + + eeprom0: qcom,eeprom@0 { + cell-index = <0>; + reg = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pmfalcon_l11>; + cam_vana-supply = <&pm2falcon_bob>; + cam_vdig-supply = <&pmfalcon_s5>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; + qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; + qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; + qcom,cam-vreg-op-mode = <105000 80000 105000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear_active + &cam_actuator_vaf_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear_suspend + &cam_actuator_vaf_suspend>; + gpios = <&tlmm 32 0>, + <&tlmm 46 0>, + <&pm2falcon_gpios 4 0>, + <&tlmm 51 0>, + <&tlmm 50 0>; + qcom,gpio-reset = <1>; + qcom,gpio-vdig = <2>; + qcom,gpio-vana = <3>; + qcom,gpio-vaf = <4>; + qcom,gpio-req-tbl-num = <0 1 2 3 4>; + qcom,gpio-req-tbl-flags = <1 0 0 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0", + "CAM_VDIG", + "CAM_VANA", + "CAM_VAF"; + qcom,sensor-position = <0>; + qcom,sensor-mode = <0>; + qcom,cci-master = <0>; + status = "ok"; + clocks = <&clock_mmss MCLK0_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_MCLK0_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + + eeprom1: qcom,eeprom@1 { + cell-index = <1>; + reg = <0x1>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pmfalcon_l11>; + cam_vana-supply = <&pm2falcon_bob>; + cam_vdig-supply = <&pmfalcon_s5>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; + qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; + qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; + qcom,cam-vreg-op-mode = <105000 80000 105000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_rear2_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_rear2_suspend>; + gpios = <&tlmm 34 0>, + <&tlmm 48 0>, + <&pm2falcon_gpios 3 0>, + <&tlmm 51 0>; + qcom,gpio-reset = <1>; + qcom,gpio-vdig = <2>; + qcom,gpio-vana = <3>; + qcom,gpio-req-tbl-num = <0 1 2 3>; + qcom,gpio-req-tbl-flags = <1 0 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET", + "CAM_VDIG", + "CAM_VANA"; + qcom,sensor-position = <0>; + qcom,sensor-mode = <0>; + qcom,cci-master = <1>; + status = "ok"; + clocks = <&clock_mmss MCLK2_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_MCLK2_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + + eeprom2: qcom,eeprom@2 { + cell-index = <2>; + reg = <0x2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pmfalcon_l11>; + cam_vana-supply = <&pm2falcon_bob>; + cam_vdig-supply = <&pmfalcon_s5>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; + qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; + qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; + qcom,cam-vreg-op-mode = <105000 80000 105000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_front_active + &cam_actuator_vaf_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_front_suspend + &cam_actuator_vaf_suspend>; + gpios = <&tlmm 33 0>, + <&tlmm 47 0>, + <&pmfalcon_gpios 3 0>, + <&tlmm 44 0>, + <&tlmm 50 0>; + qcom,gpio-reset = <1>; + qcom,gpio-vdig = <2>; + qcom,gpio-vana = <3>; + qcom,gpio-vaf = <4>; + qcom,gpio-req-tbl-num = <0 1 2 3 4>; + qcom,gpio-req-tbl-flags = <1 0 0 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VDIG", + "CAM_VANA", + "CAM_VAF"; + qcom,sensor-position = <1>; + qcom,sensor-mode = <0>; + qcom,cci-master = <1>; + status = "ok"; + clocks = <&clock_mmss MCLK1_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_MCLK1_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + + qcom,camera@0 { + cell-index = <0>; + compatible = "qcom,camera"; + reg = <0x0>; + qcom,csiphy-sd-index = <0>; + qcom,csid-sd-index = <0>; + qcom,mount-angle = <270>; + qcom,led-flash-src = <&led_flash0>; + qcom,actuator-src = <&actuator0>; + qcom,ois-src = <&ois0>; + qcom,eeprom-src = <&eeprom0>; + cam_vio-supply = <&pmfalcon_l11>; + cam_vana-supply = <&pm2falcon_bob>; + cam_vdig-supply = <&pmfalcon_s5>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; + qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; + qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; + qcom,cam-vreg-op-mode = <105000 80000 105000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear_suspend>; + gpios = <&tlmm 32 0>, + <&tlmm 46 0>, + <&pm2falcon_gpios 4 0>, + <&tlmm 51 0>; + qcom,gpio-reset = <1>; + qcom,gpio-vdig = <2>; + qcom,gpio-vana = <3>; + qcom,gpio-req-tbl-num = <0 1 2 3>; + qcom,gpio-req-tbl-flags = <1 0 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0", + "CAM_VDIG", + "CAM_VANA"; + qcom,sensor-position = <0>; + qcom,sensor-mode = <0>; + qcom,cci-master = <0>; + status = "ok"; + clocks = <&clock_mmss MCLK0_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_MCLK0_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + + qcom,camera@1 { + cell-index = <1>; + compatible = "qcom,camera"; + reg = <0x1>; + qcom,csiphy-sd-index = <1>; + qcom,csid-sd-index = <2>; + qcom,mount-angle = <90>; + qcom,actuator-src = <&actuator1>; + qcom,eeprom-src = <&eeprom1>; + cam_vio-supply = <&pmfalcon_l11>; + cam_vana-supply = <&pm2falcon_bob>; + cam_vdig-supply = <&pmfalcon_s5>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; + qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; + qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; + qcom,cam-vreg-op-mode = <105000 80000 105000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_rear2_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_rear2_suspend>; + gpios = <&tlmm 34 0>, + <&tlmm 48 0>, + <&pm2falcon_gpios 3 0>, + <&tlmm 51 0>; + qcom,gpio-reset = <1>; + qcom,gpio-vdig = <2>; + qcom,gpio-vana = <3>; + qcom,gpio-req-tbl-num = <0 1 2 3>; + qcom,gpio-req-tbl-flags = <1 0 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET", + "CAM_VDIG", + "CAM_VANA"; + qcom,sensor-position = <0>; + qcom,sensor-mode = <0>; + qcom,cci-master = <1>; + status = "ok"; + clocks = <&clock_mmss MCLK2_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_MCLK2_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + + qcom,camera@2 { + cell-index = <2>; + compatible = "qcom,camera"; + reg = <0x02>; + qcom,csiphy-sd-index = <2>; + qcom,csid-sd-index = <2>; + qcom,mount-angle = <90>; + qcom,actuator-src = <&actuator2>; + qcom,eeprom-src = <&eeprom2>; + cam_vio-supply = <&pmfalcon_l11>; + cam_vana-supply = <&pm2falcon_bob>; + cam_vdig-supply = <&pmfalcon_s5>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; + qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; + qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; + qcom,cam-vreg-op-mode = <105000 80000 105000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_front_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_front_suspend>; + gpios = <&tlmm 33 0>, + <&tlmm 47 0>, + <&pm2falcon_gpios 3 0>, + <&tlmm 51 0>; + qcom,gpio-reset = <1>; + qcom,gpio-vdig = <2>; + qcom,gpio-vana = <3>; + qcom,gpio-req-tbl-num = <0 1 2 3>; + qcom,gpio-req-tbl-flags = <1 0 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VDIG", + "CAM_VANA"; + qcom,sensor-position = <1>; + qcom,sensor-mode = <0>; + qcom,cci-master = <1>; + status = "ok"; + clocks = <&clock_mmss MCLK1_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_MCLK1_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; +}; + +&pm2falcon_gpios { + gpio@c300 { /* GPIO4 -CAMERA SENSOR 0 VDIG*/ + qcom,mode = <1>; /* Output */ + qcom,pull = <5>; /* No Pull */ + qcom,vin-sel = <0>; /* VIN1 GPIO_LV */ + qcom,src-sel = <0>; /* GPIO */ + qcom,invert = <0>; /* Invert */ + qcom,master-en = <1>; /* Enable GPIO */ + status = "ok"; + }; + + gpio@c200 { /* GPIO3 -CAMERA SENSOR 2 VDIG*/ + qcom,mode = <1>; /* Output */ + qcom,pull = <5>; /* No Pull */ + qcom,vin-sel = <0>; /* VIN1 GPIO_LV */ + qcom,src-sel = <0>; /* GPIO */ + qcom,invert = <0>; /* Invert */ + qcom,master-en = <1>; /* Enable GPIO */ + status = "ok"; + }; +}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-camera-sensor-mtp.dtsi b/arch/arm/boot/dts/qcom/msmfalcon-camera-sensor-mtp.dtsi new file mode 100644 index 000000000000..384807c4ef60 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msmfalcon-camera-sensor-mtp.dtsi @@ -0,0 +1,384 @@ +/* + * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + led_flash0: qcom,camera-flash@0 { + cell-index = <0>; + compatible = "qcom,camera-flash"; + qcom,flash-source = <&pm2falcon_flash0 &pm2falcon_flash1>; + qcom,torch-source = <&pm2falcon_torch0 &pm2falcon_torch1>; + qcom,switch-source = <&pm2falcon_switch0>; + status = "ok"; + }; + + led_flash1: qcom,camera-flash@1 { + cell-index = <1>; + compatible = "qcom,camera-flash"; + qcom,flash-source = <&pm2falcon_flash2>; + qcom,torch-source = <&pm2falcon_torch2>; + qcom,switch-source = <&pm2falcon_switch1>; + status = "ok"; + }; +}; + +&cci { + actuator0: qcom,actuator@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,actuator"; + qcom,cci-master = <0>; + gpios = <&tlmm 50 0>; + qcom,gpio-vaf = <0>; + qcom,gpio-req-tbl-num = <0>; + qcom,gpio-req-tbl-flags = <0>; + qcom,gpio-req-tbl-label = "CAM_VAF"; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_actuator_vaf_active>; + pinctrl-1 = <&cam_actuator_vaf_suspend>; + }; + + actuator1: qcom,actuator@1 { + cell-index = <1>; + reg = <0x1>; + compatible = "qcom,actuator"; + qcom,cci-master = <1>; + gpios = <&tlmm 50 0>; + qcom,gpio-vaf = <0>; + qcom,gpio-req-tbl-num = <0>; + qcom,gpio-req-tbl-flags = <0>; + qcom,gpio-req-tbl-label = "CAM_VAF"; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_actuator_vaf_active>; + pinctrl-1 = <&cam_actuator_vaf_suspend>; + }; + + actuator2: qcom,actuator@2 { + cell-index = <2>; + reg = <0x2>; + compatible = "qcom,actuator"; + qcom,cci-master = <1>; + gpios = <&tlmm 50 0>; + qcom,gpio-vaf = <0>; + qcom,gpio-req-tbl-num = <0>; + qcom,gpio-req-tbl-flags = <0>; + qcom,gpio-req-tbl-label = "CAM_VAF"; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_actuator_vaf_active>; + pinctrl-1 = <&cam_actuator_vaf_suspend>; + }; + + ois0: qcom,ois@0 { + cell-index = <0>; + reg = <0x0>; + compatible = "qcom,ois"; + qcom,cci-master = <0>; + gpios = <&tlmm 50 0>; + qcom,gpio-vaf = <0>; + qcom,gpio-req-tbl-num = <0>; + qcom,gpio-req-tbl-flags = <0>; + qcom,gpio-req-tbl-label = "CAM_VAF"; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_actuator_vaf_active>; + pinctrl-1 = <&cam_actuator_vaf_suspend>; + status = "disabled"; + }; + + eeprom0: qcom,eeprom@0 { + cell-index = <0>; + reg = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pmfalcon_l11>; + cam_vana-supply = <&pm2falcon_bob>; + cam_vdig-supply = <&pmfalcon_s5>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; + qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; + qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; + qcom,cam-vreg-op-mode = <105000 80000 105000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear_active + &cam_actuator_vaf_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear_suspend + &cam_actuator_vaf_suspend>; + gpios = <&tlmm 32 0>, + <&tlmm 46 0>, + <&pm2falcon_gpios 4 0>, + <&tlmm 51 0>, + <&tlmm 50 0>; + qcom,gpio-reset = <1>; + qcom,gpio-vdig = <2>; + qcom,gpio-vana = <3>; + qcom,gpio-vaf = <4>; + qcom,gpio-req-tbl-num = <0 1 2 3 4>; + qcom,gpio-req-tbl-flags = <1 0 0 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0", + "CAM_VDIG", + "CAM_VANA", + "CAM_VAF"; + qcom,sensor-position = <0>; + qcom,sensor-mode = <0>; + qcom,cci-master = <0>; + status = "ok"; + clocks = <&clock_mmss MCLK0_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_MCLK0_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + + eeprom1: qcom,eeprom@1 { + cell-index = <1>; + reg = <0x1>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pmfalcon_l11>; + cam_vana-supply = <&pm2falcon_bob>; + cam_vdig-supply = <&pmfalcon_s5>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; + qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; + qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; + qcom,cam-vreg-op-mode = <105000 80000 105000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_rear2_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_rear2_suspend>; + gpios = <&tlmm 34 0>, + <&tlmm 48 0>, + <&pm2falcon_gpios 3 0>, + <&tlmm 51 0>; + qcom,gpio-reset = <1>; + qcom,gpio-vdig = <2>; + qcom,gpio-vana = <3>; + qcom,gpio-req-tbl-num = <0 1 2 3>; + qcom,gpio-req-tbl-flags = <1 0 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET", + "CAM_VDIG", + "CAM_VANA"; + qcom,sensor-position = <0>; + qcom,sensor-mode = <0>; + qcom,cci-master = <1>; + status = "ok"; + clocks = <&clock_mmss MCLK2_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_MCLK2_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + + eeprom2: qcom,eeprom@2 { + cell-index = <2>; + reg = <0x2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pmfalcon_l11>; + cam_vana-supply = <&pm2falcon_bob>; + cam_vdig-supply = <&pmfalcon_s5>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; + qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; + qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; + qcom,cam-vreg-op-mode = <105000 80000 105000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_front_active + &cam_actuator_vaf_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_front_suspend + &cam_actuator_vaf_suspend>; + gpios = <&tlmm 33 0>, + <&tlmm 47 0>, + <&pmfalcon_gpios 3 0>, + <&tlmm 44 0>, + <&tlmm 50 0>; + qcom,gpio-reset = <1>; + qcom,gpio-vdig = <2>; + qcom,gpio-vana = <3>; + qcom,gpio-vaf = <4>; + qcom,gpio-req-tbl-num = <0 1 2 3 4>; + qcom,gpio-req-tbl-flags = <1 0 0 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VDIG", + "CAM_VANA", + "CAM_VAF"; + qcom,sensor-position = <1>; + qcom,sensor-mode = <0>; + qcom,cci-master = <1>; + status = "ok"; + clocks = <&clock_mmss MCLK1_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_MCLK1_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + + qcom,camera@0 { + cell-index = <0>; + compatible = "qcom,camera"; + reg = <0x0>; + qcom,csiphy-sd-index = <0>; + qcom,csid-sd-index = <0>; + qcom,mount-angle = <270>; + qcom,led-flash-src = <&led_flash0>; + qcom,actuator-src = <&actuator0>; + qcom,ois-src = <&ois0>; + qcom,eeprom-src = <&eeprom0>; + cam_vio-supply = <&pmfalcon_l11>; + cam_vana-supply = <&pm2falcon_bob>; + cam_vdig-supply = <&pmfalcon_s5>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; + qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; + qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; + qcom,cam-vreg-op-mode = <105000 80000 105000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_rear_active>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_rear_suspend>; + gpios = <&tlmm 32 0>, + <&tlmm 46 0>, + <&pm2falcon_gpios 4 0>, + <&tlmm 51 0>; + qcom,gpio-reset = <1>; + qcom,gpio-vdig = <2>; + qcom,gpio-vana = <3>; + qcom,gpio-req-tbl-num = <0 1 2 3>; + qcom,gpio-req-tbl-flags = <1 0 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0", + "CAM_VDIG", + "CAM_VANA"; + qcom,sensor-position = <0>; + qcom,sensor-mode = <0>; + qcom,cci-master = <0>; + status = "ok"; + clocks = <&clock_mmss MCLK0_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_MCLK0_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + + qcom,camera@1 { + cell-index = <1>; + compatible = "qcom,camera"; + reg = <0x1>; + qcom,csiphy-sd-index = <1>; + qcom,csid-sd-index = <2>; + qcom,mount-angle = <90>; + qcom,actuator-src = <&actuator1>; + qcom,eeprom-src = <&eeprom1>; + cam_vio-supply = <&pmfalcon_l11>; + cam_vana-supply = <&pm2falcon_bob>; + cam_vdig-supply = <&pmfalcon_s5>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; + qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; + qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; + qcom,cam-vreg-op-mode = <105000 80000 105000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_rear2_active>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_rear2_suspend>; + gpios = <&tlmm 34 0>, + <&tlmm 48 0>, + <&pm2falcon_gpios 3 0>, + <&tlmm 51 0>; + qcom,gpio-reset = <1>; + qcom,gpio-vdig = <2>; + qcom,gpio-vana = <3>; + qcom,gpio-req-tbl-num = <0 1 2 3>; + qcom,gpio-req-tbl-flags = <1 0 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK", + "CAM_RESET", + "CAM_VDIG", + "CAM_VANA"; + qcom,sensor-position = <0>; + qcom,sensor-mode = <0>; + qcom,cci-master = <1>; + status = "ok"; + clocks = <&clock_mmss MCLK2_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_MCLK2_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; + + qcom,camera@2 { + cell-index = <2>; + compatible = "qcom,camera"; + reg = <0x02>; + qcom,csiphy-sd-index = <2>; + qcom,csid-sd-index = <2>; + qcom,mount-angle = <90>; + qcom,actuator-src = <&actuator2>; + qcom,eeprom-src = <&eeprom2>; + cam_vio-supply = <&pmfalcon_l11>; + cam_vana-supply = <&pm2falcon_bob>; + cam_vdig-supply = <&pmfalcon_s5>; + qcom,cam-vreg-name = "cam_vio", "cam_vana", "cam_vdig"; + qcom,cam-vreg-min-voltage = <1780000 3300000 1350000>; + qcom,cam-vreg-max-voltage = <1950000 3600000 1350000>; + qcom,cam-vreg-op-mode = <105000 80000 105000>; + qcom,gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_front_active>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_front_suspend>; + gpios = <&tlmm 33 0>, + <&tlmm 47 0>, + <&pm2falcon_gpios 3 0>, + <&tlmm 51 0>; + qcom,gpio-reset = <1>; + qcom,gpio-vdig = <2>; + qcom,gpio-vana = <3>; + qcom,gpio-req-tbl-num = <0 1 2 3>; + qcom,gpio-req-tbl-flags = <1 0 0 0>; + qcom,gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2", + "CAM_VDIG", + "CAM_VANA"; + qcom,sensor-position = <1>; + qcom,sensor-mode = <0>; + qcom,cci-master = <1>; + status = "ok"; + clocks = <&clock_mmss MCLK1_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_MCLK1_CLK>; + clock-names = "cam_src_clk", "cam_clk"; + qcom,clock-rates = <24000000 0>; + }; +}; + +&pm2falcon_gpios { + gpio@c300 { /* GPIO4 -CAMERA SENSOR 0 VDIG*/ + qcom,mode = <1>; /* Output */ + qcom,pull = <5>; /* No Pull */ + qcom,vin-sel = <0>; /* VIN1 GPIO_LV */ + qcom,src-sel = <0>; /* GPIO */ + qcom,invert = <0>; /* Invert */ + qcom,master-en = <1>; /* Enable GPIO */ + status = "ok"; + }; + + gpio@c200 { /* GPIO3 -CAMERA SENSOR 2 VDIG*/ + qcom,mode = <1>; /* Output */ + qcom,pull = <5>; /* No Pull */ + qcom,vin-sel = <0>; /* VIN1 GPIO_LV */ + qcom,src-sel = <0>; /* GPIO */ + qcom,invert = <0>; /* Invert */ + qcom,master-en = <1>; /* Enable GPIO */ + status = "ok"; + }; +}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-camera.dtsi b/arch/arm/boot/dts/qcom/msmfalcon-camera.dtsi new file mode 100644 index 000000000000..c16794550d88 --- /dev/null +++ b/arch/arm/boot/dts/qcom/msmfalcon-camera.dtsi @@ -0,0 +1,850 @@ +/* + * Copyright (c) 2016, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + qcom,msm-cam@8c0000 { + compatible = "qcom,msm-cam"; + reg = <0x8c0000 0x40000>; + reg-names = "msm-cam"; + status = "ok"; + bus-vectors = "suspend", "svs", "nominal", "turbo"; + qcom,bus-votes = <0 300000000 640000000 640000000>; + }; + + qcom,csiphy@c824000 { + cell-index = <0>; + compatible = "qcom,csiphy-v3.5", "qcom,csiphy"; + reg = <0xc824000 0x1000>; + reg-names = "csiphy"; + interrupts = <0 78 0>; + interrupt-names = "csiphy"; + gdscr-supply = <&gdsc_camss_top>; + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "gdscr", "bimc_smmu"; + clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>, + <&clock_mmss MMSS_MNOC_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>, + <&clock_mmss MMSS_CAMSS_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>, + <&clock_mmss CSI0_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_CSI0_CLK>, + <&clock_mmss MMSS_CAMSS_CPHY_CSID0_CLK>, + <&clock_mmss CSI0PHYTIMER_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_CSI0PHYTIMER_CLK>, + <&clock_mmss MMSS_CAMSS_ISPIF_AHB_CLK>, + <&clock_mmss CSIPHY_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_CSIPHY0_CLK>; + clock-names = "mmssnoc_axi", "mnoc_ahb", + "bmic_smmu_ahb", "bmic_smmu_axi", + "camss_ahb_clk", "camss_top_ahb_clk", + "csi_src_clk", "csi_clk", "cphy_csid_clk", + "csiphy_timer_src_clk", "csiphy_timer_clk", + "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk"; + qcom,clock-rates = <0 0 0 0 0 0 384000000 0 0 269333333 0 + 0 384000000 0>; + status = "ok"; + }; + + qcom,csiphy@c825000 { + cell-index = <1>; + compatible = "qcom,csiphy-v3.5", "qcom,csiphy"; + reg = <0xc825000 0x1000>; + reg-names = "csiphy"; + interrupts = <0 79 0>; + interrupt-names = "csiphy"; + gdscr-supply = <&gdsc_camss_top>; + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "gdscr", "bimc_smmu"; + clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>, + <&clock_mmss MMSS_MNOC_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>, + <&clock_mmss MMSS_CAMSS_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>, + <&clock_mmss CSI1_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_CSI1_CLK>, + <&clock_mmss MMSS_CAMSS_CPHY_CSID1_CLK>, + <&clock_mmss CSI1PHYTIMER_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_CSI1PHYTIMER_CLK>, + <&clock_mmss MMSS_CAMSS_ISPIF_AHB_CLK>, + <&clock_mmss CSIPHY_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_CSIPHY1_CLK>; + clock-names = "mmssnoc_axi", "mnoc_ahb", + "bmic_smmu_ahb", "bmic_smmu_axi", + "camss_ahb_clk", "camss_top_ahb_clk", + "csi_src_clk", "csi_clk", "cphy_csid_clk", + "csiphy_timer_src_clk", "csiphy_timer_clk", + "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk"; + qcom,clock-rates = <0 0 0 0 0 0 384000000 0 0 269333333 0 + 0 384000000 0>; + status = "ok"; + }; + + qcom,csiphy@c826000 { + cell-index = <2>; + compatible = "qcom,csiphy-v3.5", "qcom,csiphy"; + reg = <0xc826000 0x1000>; + reg-names = "csiphy"; + interrupts = <0 80 0>; + interrupt-names = "csiphy"; + gdscr-supply = <&gdsc_camss_top>; + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "gdscr", "bimc_smmu"; + clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>, + <&clock_mmss MMSS_MNOC_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>, + <&clock_mmss MMSS_CAMSS_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>, + <&clock_mmss CSI0_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_CSI2_CLK>, + <&clock_mmss MMSS_CAMSS_CPHY_CSID2_CLK>, + <&clock_mmss CSI2PHYTIMER_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_CSI2PHYTIMER_CLK>, + <&clock_mmss MMSS_CAMSS_ISPIF_AHB_CLK>, + <&clock_mmss CSIPHY_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_CSIPHY2_CLK>; + clock-names = "mmssnoc_axi", "mnoc_ahb", + "bmic_smmu_ahb", "bmic_smmu_axi", + "camss_ahb_clk", "camss_top_ahb_clk", + "csi_src_clk", "csi_clk", "cphy_csid_clk", + "csiphy_timer_src_clk", "csiphy_timer_clk", + "camss_ispif_ahb_clk", "csiphy_clk_src", "csiphy_clk"; + qcom,clock-rates = <0 0 0 0 0 0 384000000 0 0 269333333 0 + 0 384000000 0>; + status = "ok"; + }; + + qcom,csid@ca30000 { + cell-index = <0>; + compatible = "qcom,csid-v5.0", "qcom,csid"; + reg = <0xca30000 0x400>; + reg-names = "csid"; + interrupts = <0 296 0>; + interrupt-names = "csid"; + qcom,csi-vdd-voltage = <1200000>; + qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>; + gdscr-supply = <&gdsc_camss_top>; + vdd_sec-supply = <&pm2falcon_l1>; + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; + qcom,cam-vreg-min-voltage = <925000 0 0>; + qcom,cam-vreg-max-voltage = <925000 0 0>; + qcom,cam-vreg-op-mode = <0 0 0>; + clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>, + <&clock_mmss MMSS_MNOC_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>, + <&clock_mmss MMSS_CAMSS_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_ISPIF_AHB_CLK>, + <&clock_mmss CSI0_CLK_SRC>, + <&clock_mmss CSIPHY_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_CSI0_CLK>, + <&clock_mmss MMSS_CAMSS_CSI0_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_CSI0RDI_CLK>, + <&clock_mmss MMSS_CAMSS_CSI0PIX_CLK>, + <&clock_mmss MMSS_CAMSS_CPHY_CSID0_CLK>; + clock-names = "mmssnoc_axi", "mnoc_ahb", + "bmic_smmu_ahb", "bmic_smmu_axi", + "camss_ahb_clk", "camss_top_ahb_clk", + "ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src", + "csi_clk", "csi_ahb_clk", "csi_rdi_clk", + "csi_pix_clk", "cphy_csid_clk"; + qcom,clock-rates = <0 0 0 0 0 0 0 384000000 384000000 + 0 0 0 0 0>; + status = "ok"; + }; + + qcom,csid@ca30400 { + cell-index = <1>; + compatible = "qcom,csid-v5.0", "qcom,csid"; + reg = <0xca30400 0x400>; + reg-names = "csid"; + interrupts = <0 297 0>; + interrupt-names = "csid"; + qcom,csi-vdd-voltage = <1200000>; + qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>; + gdscr-supply = <&gdsc_camss_top>; + vdd_sec-supply = <&pm2falcon_l1>; + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; + qcom,cam-vreg-min-voltage = <925000 0 0>; + qcom,cam-vreg-max-voltage = <925000 0 0>; + qcom,cam-vreg-op-mode = <0 0 0>; + clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>, + <&clock_mmss MMSS_MNOC_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>, + <&clock_mmss MMSS_CAMSS_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_ISPIF_AHB_CLK>, + <&clock_mmss CSI1_CLK_SRC>, + <&clock_mmss CSIPHY_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_CSI1_CLK>, + <&clock_mmss MMSS_CAMSS_CSI1_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_CSI1RDI_CLK>, + <&clock_mmss MMSS_CAMSS_CSI1PIX_CLK>, + <&clock_mmss MMSS_CAMSS_CPHY_CSID1_CLK>; + clock-names = "mmssnoc_axi", "mnoc_ahb", + "bmic_smmu_ahb", "bmic_smmu_axi", + "camss_ahb_clk", "camss_top_ahb_clk", + "ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src", + "csi_clk", "csi_ahb_clk", "csi_rdi_clk", + "csi_pix_clk", "cphy_csid_clk"; + qcom,clock-rates = <0 0 0 0 0 0 0 256000000 256000000 + 0 0 0 0 0>; + status = "ok"; + }; + + qcom,csid@ca30800 { + cell-index = <2>; + compatible = "qcom,csid-v5.0", "qcom,csid"; + reg = <0xca30800 0x400>; + reg-names = "csid"; + interrupts = <0 298 0>; + interrupt-names = "csid"; + qcom,csi-vdd-voltage = <1200000>; + qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>; + gdscr-supply = <&gdsc_camss_top>; + vdd_sec-supply = <&pm2falcon_l1>; + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; + qcom,cam-vreg-min-voltage = <925000 0 0>; + qcom,cam-vreg-max-voltage = <925000 0 0>; + qcom,cam-vreg-op-mode = <0 0 0>; + clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>, + <&clock_mmss MMSS_MNOC_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>, + <&clock_mmss MMSS_CAMSS_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_ISPIF_AHB_CLK>, + <&clock_mmss CSI2_CLK_SRC>, + <&clock_mmss CSIPHY_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_CSI2_CLK>, + <&clock_mmss MMSS_CAMSS_CSI2_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_CSI2RDI_CLK>, + <&clock_mmss MMSS_CAMSS_CSI2PIX_CLK>, + <&clock_mmss MMSS_CAMSS_CPHY_CSID2_CLK>; + clock-names = "mmssnoc_axi", "mnoc_ahb", + "bmic_smmu_ahb", "bmic_smmu_axi", + "camss_ahb_clk", "camss_top_ahb_clk", + "ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src", + "csi_clk", "csi_ahb_clk", "csi_rdi_clk", + "csi_pix_clk", "cphy_csid_clk"; + qcom,clock-rates = <0 0 0 0 0 0 0 256000000 256000000 + 0 0 0 0 0>; + status = "ok"; + }; + + qcom,csid@ca30c00 { + cell-index = <3>; + compatible = "qcom,csid-v5.0", "qcom,csid"; + reg = <0xca30c00 0x400>; + reg-names = "csid"; + interrupts = <0 299 0>; + interrupt-names = "csid"; + qcom,csi-vdd-voltage = <1200000>; + qcom,mipi-csi-vdd-supply = <&pmfalcon_l1>; + gdscr-supply = <&gdsc_camss_top>; + vdd_sec-supply = <&pm2falcon_l1>; + bimc_smmu-supply = <&gdsc_bimc_smmu>; + qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu"; + qcom,cam-vreg-min-voltage = <925000 0 0>; + qcom,cam-vreg-max-voltage = <925000 0 0>; + qcom,cam-vreg-op-mode = <0 0 0>; + clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>, + <&clock_mmss MMSS_MNOC_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>, + <&clock_mmss MMSS_CAMSS_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_ISPIF_AHB_CLK>, + <&clock_mmss CSI3_CLK_SRC>, + <&clock_mmss CSIPHY_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_CSI3_CLK>, + <&clock_mmss MMSS_CAMSS_CSI3_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_CSI3RDI_CLK>, + <&clock_mmss MMSS_CAMSS_CSI3PIX_CLK>, + <&clock_mmss MMSS_CAMSS_CPHY_CSID3_CLK>; + clock-names = "mmssnoc_axi", "mnoc_ahb", + "bmic_smmu_ahb", "bmic_smmu_axi", + "camss_ahb_clk", "camss_top_ahb_clk", + "ispif_ahb_clk", "csi_src_clk", "csiphy_clk_src", + "csi_clk", "csi_ahb_clk", "csi_rdi_clk", + "csi_pix_clk", "cphy_csid_clk"; + qcom,clock-rates = <0 0 0 0 0 0 0 256000000 256000000 + 0 0 0 0 0>; + status = "ok"; + }; + + qcom,cam_smmu { + compatible = "qcom,msm-cam-smmu"; + status = "ok"; + + msm_cam_smmu_cb1 { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&mmss_bimc_smmu 0xc00>, + <&mmss_bimc_smmu 0xc01>, + <&mmss_bimc_smmu 0xc02>, + <&mmss_bimc_smmu 0xc03>; + label = "vfe"; + qcom,scratch-buf-support; + }; + + msm_cam_smmu_cb2 { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&mmss_bimc_smmu 0xa00>; + label = "cpp"; + }; + + msm_cam_smmu_cb3 { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&mmss_bimc_smmu 0xa01>; + label = "camera_fd"; + }; + + msm_cam_smmu_cb4 { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&mmss_bimc_smmu 0x800>; + label = "jpeg_enc0"; + }; + + msm_cam_smmu_cb5 { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&mmss_bimc_smmu 0x801>; + label = "jpeg_dma"; + }; + }; + + qcom,cpp@ca04000 { + cell-index = <0>; + compatible = "qcom,cpp"; + reg = <0xca04000 0x100>, + <0xca80000 0x3000>, + <0xca18000 0x3000>, + <0xc8c36D4 0x4>; + reg-names = "cpp", "cpp_vbif", "cpp_hw", "camss_cpp"; + interrupts = <0 294 0>; + interrupt-names = "cpp"; + smmu-vdd-supply = <&gdsc_bimc_smmu>; + camss-vdd-supply = <&gdsc_camss_top>; + vdd-supply = <&gdsc_cpp>; + qcom,vdd-names = "smmu-vdd", "camss-vdd", "vdd"; + clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>, + <&clock_mmss MMSS_MNOC_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>, + <&clock_mmss CPP_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_CPP_CLK>, + <&clock_mmss MMSS_CAMSS_CPP_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_CPP_AXI_CLK>, + <&clock_mmss MMSS_CAMSS_MICRO_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>, + <&clock_mmss MMSS_CAMSS_CPP_VBIF_AHB_CLK>; + clock-names = "mmssnoc_axi_clk", + "mnoc_ahb_clk", + "camss_ahb_clk", "camss_top_ahb_clk", + "cpp_src_clk", + "cpp_core_clk", "camss_cpp_ahb_clk", + "camss_cpp_axi_clk", "micro_iface_clk", + "mmss_smmu_axi_clk", "cpp_vbif_ahb_clk"; + qcom,clock-rates = <0 0 0 0 200000000 200000000 0 0 0 0 0>; + qcom,min-clock-rate = <200000000>; + qcom,bus-master = <1>; + qcom,vbif-qos-setting = <0x20 0x10000000>, + <0x24 0x10000000>, + <0x28 0x10000000>, + <0x2C 0x10000000>; + status = "ok"; + qcom,msm-bus,name = "msm_camera_cpp"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <106 512 0 0>, + <106 512 0 0>; + qcom,msm-bus-vector-dyn-vote; + resets = <&clock_mmss CAMSS_MICRO_BCR>; + reset-names = "micro_iface_reset"; + qcom,src-clock-rates = <100000000 200000000 576000000 + 600000000>; + qcom,cpp-fw-payload-info { + qcom,stripe-base = <790>; + qcom,plane-base = <715>; + qcom,stripe-size = <63>; + qcom,plane-size = <25>; + qcom,fe-ptr-off = <11>; + qcom,we-ptr-off = <23>; + qcom,ref-fe-ptr-off = <17>; + qcom,ref-we-ptr-off = <36>; + qcom,we-meta-ptr-off = <42>; + qcom,fe-mmu-pf-ptr-off = <7>; + qcom,ref-fe-mmu-pf-ptr-off = <10>; + qcom,we-mmu-pf-ptr-off = <13>; + qcom,dup-we-mmu-pf-ptr-off = <18>; + qcom,ref-we-mmu-pf-ptr-off = <23>; + qcom,set-group-buffer-len = <135>; + qcom,dup-frame-indicator-off = <70>; + }; + }; + + qcom,ispif@ca31000 { + cell-index = <0>; + compatible = "qcom,ispif-v3.0", "qcom,ispif"; + reg = <0xca31000 0xc00>, + <0xca00020 0x4>; + reg-names = "ispif", "csi_clk_mux"; + interrupts = <0 309 0>; + interrupt-names = "ispif"; + qcom,num-isps = <0x2>; + camss-vdd-supply = <&gdsc_camss_top>; + vfe0-vdd-supply = <&gdsc_vfe0>; + vfe1-vdd-supply = <&gdsc_vfe1>; + qcom,vdd-names = "camss-vdd", "vfe0-vdd", + "vfe1-vdd"; + qcom,clock-cntl-support; + clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>, + <&clock_mmss MMSS_MNOC_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_ISPIF_AHB_CLK>, + <&clock_mmss CSI0_CLK_SRC>, + <&clock_mmss CSI1_CLK_SRC>, + <&clock_mmss CSI2_CLK_SRC>, + <&clock_mmss CSI3_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_CSI0RDI_CLK>, + <&clock_mmss MMSS_CAMSS_CSI1RDI_CLK>, + <&clock_mmss MMSS_CAMSS_CSI2RDI_CLK>, + <&clock_mmss MMSS_CAMSS_CSI3RDI_CLK>, + <&clock_mmss MMSS_CAMSS_CSI0PIX_CLK>, + <&clock_mmss MMSS_CAMSS_CSI1PIX_CLK>, + <&clock_mmss MMSS_CAMSS_CSI2PIX_CLK>, + <&clock_mmss MMSS_CAMSS_CSI3PIX_CLK>, + <&clock_mmss MMSS_CAMSS_CSI0_CLK>, + <&clock_mmss MMSS_CAMSS_CSI1_CLK>, + <&clock_mmss MMSS_CAMSS_CSI2_CLK>, + <&clock_mmss MMSS_CAMSS_CSI3_CLK>, + <&clock_mmss MMSS_CAMSS_VFE0_CLK>, + <&clock_mmss VFE0_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_CSI_VFE0_CLK>, + <&clock_mmss MMSS_CAMSS_VFE1_CLK>, + <&clock_mmss VFE1_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_CSI_VFE1_CLK>; + clock-names = "mmssnoc_axi", "mnoc_ahb_clk", + "camss_ahb_clk", + "camss_top_ahb_clk", "ispif_ahb_clk", + "csi0_src_clk", "csi1_src_clk", + "csi2_src_clk", "csi3_src_clk", + "csi0_rdi_clk", "csi1_rdi_clk", + "csi2_rdi_clk", "csi3_rdi_clk", + "csi0_pix_clk", "csi1_pix_clk", + "csi2_pix_clk", "csi3_pix_clk", + "camss_csi0_clk", "camss_csi1_clk", + "camss_csi2_clk", "camss_csi3_clk", + "camss_vfe_vfe0_clk", + "vfe0_clk_src", "camss_csi_vfe0_clk", + "camss_vfe_vfe1_clk", + "vfe1_clk_src", "camss_csi_vfe1_clk"; + qcom,clock-rates = <0 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 0 + 0 0 0 + 0 0 0>; + qcom,clock-control = "INIT_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", + "INIT_RATE", "INIT_RATE", + "INIT_RATE", "INIT_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", "NO_SET_RATE", + "NO_SET_RATE", + "INIT_RATE", "NO_SET_RATE", + "NO_SET_RATE", + "INIT_RATE", "NO_SET_RATE"; + status = "ok"; + }; + + vfe0: qcom,vfe0@ca10000 { + cell-index = <0>; + compatible = "qcom,vfe48"; + reg = <0xca10000 0x4000>, + <0xca40000 0x3000>; + reg-names = "vfe", "vfe_vbif"; + interrupts = <0 314 0>; + interrupt-names = "vfe"; + vdd-supply = <&gdsc_vfe0>; + camss-vdd-supply = <&gdsc_camss_top>; + smmu-vdd-supply = <&gdsc_bimc_smmu>; + qcom,vdd-names = "vdd", "camss-vdd", "smmu-vdd"; + clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>, + <&clock_mmss MMSS_MNOC_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>, + <&clock_mmss MMSS_CAMSS_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_VFE0_CLK>, + <&clock_mmss MMSS_CAMSS_VFE0_STREAM_CLK>, + <&clock_mmss MMSS_CAMSS_VFE0_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_VFE_VBIF_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_VFE_VBIF_AXI_CLK>, + <&clock_mmss VFE0_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_CSI_VFE0_CLK>; + clock-names = "mmssnoc_axi", "mnoc_ahb_clk", + "bimc_smmu_ahb_clk", "bimc_smmu_axi_clk", + "camss_ahb_clk", "camss_top_ahb_clk", + "camss_vfe_clk", "camss_vfe_stream_clk", + "camss_vfe_ahb_clk", "camss_vfe_vbif_ahb_clk", + "camss_vfe_vbif_axi_clk", "vfe_clk_src", + "camss_csi_vfe_clk"; + qcom,clock-rates = <0 0 0 0 0 0 0 0 0 0 0 384000000 0 + 0 0 0 0 0 0 0 0 0 0 0 576000000 0 + 0 0 0 0 0 0 0 0 0 0 0 600000000 0>; + status = "ok"; + qos-entries = <8>; + qos-regs = <0x404 0x408 0x40c 0x410 0x414 0x418 + 0x41c 0x420>; + qos-settings = <0xaaa5aaa5 + 0xaaa5aaa5 + 0xaaa5aaa5 + 0xaa55aaa5 + 0xaa55aa55 + 0xaa55aa55 + 0xaa55aa55 + 0x0005aa55>; + vbif-entries = <3>; + vbif-regs = <0x124 0xac 0xd0>; + vbif-settings = <0x3 0x40 0x1010>; + ds-entries = <17>; + ds-regs = <0x424 0x428 0x42c 0x430 0x434 + 0x438 0x43c 0x440 0x444 0x448 0x44c + 0x450 0x454 0x458 0x45c 0x460 0x464>; + ds-settings = <0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0x110>; + qcom,msm-bus,name = "msm_camera_vfe"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <29 512 0 0>, + <29 512 100000000 100000000>; + qcom,msm-bus-vector-dyn-vote; + }; + + vfe1: qcom,vfe1@ca14000 { + cell-index = <1>; + compatible = "qcom,vfe48"; + reg = <0xca14000 0x4000>, + <0xca40000 0x3000>; + reg-names = "vfe", "vfe_vbif"; + interrupts = <0 315 0>; + interrupt-names = "vfe"; + vdd-supply = <&gdsc_vfe1>; + camss-vdd-supply = <&gdsc_camss_top>; + smmu-vdd-supply = <&gdsc_bimc_smmu>; + qcom,vdd-names = "vdd", "camss-vdd", "smmu-vdd"; + clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>, + <&clock_mmss MMSS_MNOC_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>, + <&clock_mmss MMSS_CAMSS_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_VFE1_CLK>, + <&clock_mmss MMSS_CAMSS_VFE1_STREAM_CLK>, + <&clock_mmss MMSS_CAMSS_VFE1_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_VFE_VBIF_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_VFE_VBIF_AXI_CLK>, + <&clock_mmss VFE1_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_CSI_VFE1_CLK>; + clock-names = "mmssnoc_axi", "mnoc_ahb_clk", + "bimc_smmu_ahb_clk", "bimc_smmu_axi_clk", + "camss_ahb_clk", "camss_top_ahb_clk", + "camss_vfe_clk", "camss_vfe_stream_clk", + "camss_vfe_ahb_clk", "camss_vfe_vbif_ahb_clk", + "camss_vfe_vbif_axi_clk", "vfe_clk_src", + "camss_csi_vfe_clk"; + qcom,clock-rates = <0 0 0 0 0 0 0 0 0 0 0 384000000 0 + 0 0 0 0 0 0 0 0 0 0 0 576000000 0 + 0 0 0 0 0 0 0 0 0 0 0 600000000 0>; + status = "ok"; + qos-entries = <8>; + qos-regs = <0x404 0x408 0x40c 0x410 0x414 0x418 + 0x41c 0x420>; + qos-settings = <0xaaa5aaa5 + 0xaaa5aaa5 + 0xaaa5aaa5 + 0xaa55aaa5 + 0xaa55aa55 + 0xaa55aa55 + 0xaa55aa55 + 0x0005aa55>; + vbif-entries = <3>; + vbif-regs = <0x124 0xac 0xd0>; + vbif-settings = <0x3 0x40 0x1010>; + ds-entries = <17>; + ds-regs = <0x424 0x428 0x42c 0x430 0x434 + 0x438 0x43c 0x440 0x444 0x448 0x44c + 0x450 0x454 0x458 0x45c 0x460 0x464>; + ds-settings = <0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0xcccc1111 + 0x110>; + qcom,msm-bus,name = "msm_camera_vfe"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = + <29 512 0 0>, + <29 512 100000000 100000000>; + qcom,msm-bus-vector-dyn-vote; + }; + + qcom,vfe { + compatible = "qcom,vfe"; + num_child = <2>; + }; + + cci: qcom,cci@ca0c000 { + cell-index = <0>; + compatible = "qcom,cci"; + reg = <0xca0c000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "cci"; + interrupts = <0 295 0>; + interrupt-names = "cci"; + status = "ok"; + mmagic-supply = <&gdsc_bimc_smmu>; + gdscr-supply = <&gdsc_camss_top>; + qcom,cam-vreg-name = "mmagic", "gdscr"; + clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>, + <&clock_mmss MMSS_MNOC_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>, + <&clock_mmss MMSS_CAMSS_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>, + <&clock_mmss CCI_CLK_SRC>, + <&clock_mmss MMSS_CAMSS_CCI_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_CCI_CLK>; + clock-names = "mmssnoc_axi", "mnoc_ahb", "smmu_ahb", "smmu_axi", + "camss_ahb_clk", "camss_top_ahb_clk", + "cci_src_clk", "cci_ahb_clk", "camss_cci_clk"; + qcom,clock-rates = <0 0 0 0 0 0 19200000 0 0>, + <0 0 0 0 0 0 37500000 0 0>; + pinctrl-names = "cci_default", "cci_suspend"; + pinctrl-0 = <&cci0_active &cci1_active>; + pinctrl-1 = <&cci0_suspend &cci1_suspend>; + gpios = <&tlmm 36 0>, + <&tlmm 37 0>, + <&tlmm 38 0>, + <&tlmm 39 0>; + qcom,gpio-tbl-num = <0 1 2 3>; + qcom,gpio-tbl-flags = <1 1 1 1>; + qcom,gpio-tbl-label = "CCI_I2C_DATA0", + "CCI_I2C_CLK0", + "CCI_I2C_DATA1", + "CCI_I2C_CLK1"; + i2c_freq_100Khz: qcom,i2c_standard_mode { + status = "disabled"; + }; + i2c_freq_400Khz: qcom,i2c_fast_mode { + status = "disabled"; + }; + i2c_freq_custom: qcom,i2c_custom_mode { + status = "disabled"; + }; + i2c_freq_1Mhz: qcom,i2c_fast_plus_mode { + status = "disabled"; + }; + }; + + qcom,jpeg@ca1c000 { + cell-index = <0>; + compatible = "qcom,jpeg"; + reg = <0xca1c000 0x4000>, + <0xca60000 0x3000>; + reg-names = "jpeg_hw", "jpeg_vbif"; + interrupts = <0 316 0>; + interrupt-names = "jpeg"; + smmu-vdd-supply = <&gdsc_bimc_smmu>; + camss-vdd-supply = <&gdsc_camss_top>; + qcom,vdd-names = "smmu-vdd", "camss-vdd"; + clock-names = "mmssnoc_axi", + "mmss_mnoc_ahb_clk", + "mmss_bimc_smmu_ahb_clk", + "mmss_bimc_smmu_axi_clk", + "mmss_camss_ahb_clk", + "mmss_camss_top_ahb_clk", + "core_clk", + "mmss_camss_jpeg_ahb_clk", + "mmss_camss_jpeg_axi_clk"; + clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>, + <&clock_mmss MMSS_MNOC_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>, + <&clock_mmss MMSS_CAMSS_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_JPEG0_CLK>, + <&clock_mmss MMSS_CAMSS_JPEG_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_JPEG_AXI_CLK >; + qcom,clock-rates = <0 0 0 0 0 0 480000000 0 0>; + qcom,vbif-reg-settings = <0x4 0x1>; + qcom,prefetch-reg-settings = <0x30c 0x1111>, + <0x318 0x31>, + <0x324 0x31>, + <0x330 0x31>, + <0x33c 0x0>; + qcom,msm-bus,name = "msm_camera_jpeg0"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <62 512 0 0>, + <62 512 1920000 2880000>; + status = "ok"; + }; + + qcom,jpeg@caa0000 { + cell-index = <3>; + compatible = "qcom,jpegdma"; + reg = <0xcaa0000 0x4000>, + <0xca60000 0x3000>; + reg-names = "jpeg_hw", "jpeg_vbif"; + interrupts = <0 304 0>; + interrupt-names = "jpeg"; + smmu-vdd-supply = <&gdsc_bimc_smmu>; + camss-vdd-supply = <&gdsc_camss_top>; + qcom,vdd-names = "smmu-vdd", "camss-vdd"; + clock-names = "mmssnoc_axi", + "mmss_mnoc_ahb_clk", + "mmss_bimc_smmu_ahb_clk", + "mmss_bimc_smmu_axi_clk", + "mmss_camss_ahb_clk", + "mmss_camss_top_ahb_clk", + "core_clk", + "mmss_camss_jpeg_ahb_clk", + "mmss_camss_jpeg_axi_clk"; + clocks = <&clock_rpmcc MMSSNOC_AXI_CLK>, + <&clock_mmss MMSS_MNOC_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AHB_CLK>, + <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>, + <&clock_mmss MMSS_CAMSS_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_TOP_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_JPEG0_CLK>, + <&clock_mmss MMSS_CAMSS_JPEG_AHB_CLK>, + <&clock_mmss MMSS_CAMSS_JPEG_AXI_CLK>; + qcom,clock-rates = <0 0 0 0 0 0 480000000 0 0>; + qcom,vbif-reg-settings = <0x4 0x1>; + qcom,prefetch-reg-settings = <0x18c 0x11>, + <0x1a0 0x31>, + <0x1b0 0x31>; + qcom,msm-bus,name = "msm_camera_jpeg_dma"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,num-paths = <1>; + qcom,msm-bus,vectors-KBps = <62 512 0 0>, + <62 512 1920000 2880000>; + qcom,max-ds-factor = <128>; + status = "ok"; + }; +}; + +&i2c_freq_100Khz { + qcom,hw-thigh = <201>; + qcom,hw-tlow = <174>; + qcom,hw-tsu-sto = <204>; + qcom,hw-tsu-sta = <231>; + qcom,hw-thd-dat = <22>; + qcom,hw-thd-sta = <162>; + qcom,hw-tbuf = <227>; + qcom,hw-scl-stretch-en = <0>; + qcom,hw-trdhld = <6>; + qcom,hw-tsp = <3>; + qcom,cci-clk-src = <37500000>; + status = "ok"; +}; + +&i2c_freq_400Khz { + qcom,hw-thigh = <38>; + qcom,hw-tlow = <56>; + qcom,hw-tsu-sto = <40>; + qcom,hw-tsu-sta = <40>; + qcom,hw-thd-dat = <22>; + qcom,hw-thd-sta = <35>; + qcom,hw-tbuf = <62>; + qcom,hw-scl-stretch-en = <0>; + qcom,hw-trdhld = <6>; + qcom,hw-tsp = <3>; + qcom,cci-clk-src = <37500000>; + status = "ok"; +}; + +&i2c_freq_custom { + qcom,hw-thigh = <38>; + qcom,hw-tlow = <56>; + qcom,hw-tsu-sto = <40>; + qcom,hw-tsu-sta = <40>; + qcom,hw-thd-dat = <22>; + qcom,hw-thd-sta = <35>; + qcom,hw-tbuf = <62>; + qcom,hw-scl-stretch-en = <1>; + qcom,hw-trdhld = <6>; + qcom,hw-tsp = <3>; + qcom,cci-clk-src = <37500000>; + status = "ok"; +}; + +&i2c_freq_1Mhz { + qcom,hw-thigh = <16>; + qcom,hw-tlow = <22>; + qcom,hw-tsu-sto = <17>; + qcom,hw-tsu-sta = <18>; + qcom,hw-thd-dat = <16>; + qcom,hw-thd-sta = <15>; + qcom,hw-tbuf = <24>; + qcom,hw-scl-stretch-en = <0>; + qcom,hw-trdhld = <3>; + qcom,hw-tsp = <3>; + qcom,cci-clk-src = <37500000>; + status = "ok"; +}; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-cdp.dtsi b/arch/arm/boot/dts/qcom/msmfalcon-cdp.dtsi index 9cf8a200a327..9f057b9444c1 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-cdp.dtsi +++ b/arch/arm/boot/dts/qcom/msmfalcon-cdp.dtsi @@ -11,6 +11,7 @@ */ #include "msmfalcon-pinctrl.dtsi" +#include "msmfalcon-camera-sensor-cdp.dtsi" / { }; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-common.dtsi b/arch/arm/boot/dts/qcom/msmfalcon-common.dtsi index 50513ceabbeb..1a7ec9fea452 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-common.dtsi +++ b/arch/arm/boot/dts/qcom/msmfalcon-common.dtsi @@ -36,6 +36,7 @@ qcom,dwc-usb3-msm-tx-fifo-size = <21288>; extcon = <&pmfalcon_pdphy>; + qcom,pm-qos-latency = <41>; /* CPU-CLUSTER-WFI-LVL latency +1 */ clocks = <&clock_gcc GCC_USB30_MASTER_CLK>, <&clock_gcc GCC_CFG_NOC_USB3_AXI_CLK>, @@ -63,6 +64,7 @@ usb-phy = <&qusb_phy0>, <&ssphy>; tx-fifo-resize; snps,nominal-elastic-buffer; + snps,disable-clk-gating; snps,is-utmi-l1-suspend; snps,hird-threshold = /bits/ 8 <0x0>; }; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-gpu.dtsi b/arch/arm/boot/dts/qcom/msmfalcon-gpu.dtsi index 111eca7aef22..5c11131b9ddf 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-gpu.dtsi +++ b/arch/arm/boot/dts/qcom/msmfalcon-gpu.dtsi @@ -111,6 +111,24 @@ vddcx-supply = <&gdsc_gpu_cx>; vdd-supply = <&gdsc_gpu_gx>; + /* CPU latency parameter */ + qcom,pm-qos-active-latency = <349>; + qcom,pm-qos-wakeup-latency = <349>; + + /* Quirks */ + qcom,gpu-quirk-two-pass-use-wfi; + qcom,gpu-quirk-dp2clockgating-disable; + qcom,gpu-quirk-lmloadkill-disable; + + /* Enable context aware freq. scaling */ + qcom,enable-ca-jump; + + /* Context aware jump busy penalty in us */ + qcom,ca-busy-penalty = <12000>; + + /* Context aware jump target power level */ + qcom,ca-target-pwrlevel = <4>; + /* GPU Mempools */ qcom,gpu-mempools { #address-cells= <1>; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-mtp.dtsi b/arch/arm/boot/dts/qcom/msmfalcon-mtp.dtsi index 9cf8a200a327..bde93bf4c314 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-mtp.dtsi +++ b/arch/arm/boot/dts/qcom/msmfalcon-mtp.dtsi @@ -11,6 +11,7 @@ */ #include "msmfalcon-pinctrl.dtsi" +#include "msmfalcon-camera-sensor-mtp.dtsi" / { }; diff --git a/arch/arm/boot/dts/qcom/msmfalcon-pinctrl.dtsi b/arch/arm/boot/dts/qcom/msmfalcon-pinctrl.dtsi index 8315f1db6544..d89293c63840 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon-pinctrl.dtsi +++ b/arch/arm/boot/dts/qcom/msmfalcon-pinctrl.dtsi @@ -805,6 +805,264 @@ }; }; + cci0_active: cci0_active { + mux { + /* CLK, DATA */ + pins = "gpio36","gpio37"; // Only 2 + function = "cci_i2c"; + }; + + config { + pins = "gpio36","gpio37"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci0_suspend: cci0_suspend { + mux { + /* CLK, DATA */ + pins = "gpio36","gpio37"; + function = "cci_i2c"; + }; + + config { + pins = "gpio36","gpio37"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_active: cci1_active { + mux { + /* CLK, DATA */ + pins = "gpio38","gpio39"; + function = "cci_i2c"; + }; + + config { + pins = "gpio38","gpio39"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_suspend: cci1_suspend { + mux { + /* CLK, DATA */ + pins = "gpio38","gpio39"; + function = "cci_i2c"; + }; + + + config { + pins = "gpio38","gpio39"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_actuator_vaf_active: cam_actuator_vaf_active { + /* ACTUATOR POWER */ + mux { + pins = "gpio50"; + function = "gpio"; + }; + + config { + pins = "gpio50"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_actuator_vaf_suspend: cam_actuator_vaf_suspend { + /* ACTUATOR POWER */ + mux { + pins = "gpio50"; + function = "gpio"; + }; + + config { + pins = "gpio50"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_active: cam_sensor_mclk0_active { + /* MCLK0 */ + mux { + /* CLK, DATA */ + pins = "gpio32"; + function = "cam_mclk"; + }; + + config { + pins = "gpio32"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend { + /* MCLK0 */ + mux { + /* CLK, DATA */ + pins = "gpio32"; + function = "cam_mclk"; + }; + + config { + pins = "gpio32"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_active: cam_sensor_rear_active { + /* RESET, STANDBY */ + mux { + pins = "gpio46","gpio44"; + function = "gpio"; + }; + + config { + pins = "gpio46","gpio44"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear_suspend: cam_sensor_rear_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio46","gpio44"; + function = "gpio"; + }; + + config { + pins = "gpio46","gpio44"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_active: cam_sensor_mclk1_active { + /* MCLK1 */ + mux { + /* CLK, DATA */ + pins = "gpio33"; + function = "cam_mclk"; + }; + + config { + pins = "gpio33"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend { + /* MCLK1 */ + mux { + /* CLK, DATA */ + pins = "gpio33"; + function = "cam_mclk"; + }; + + config { + pins = "gpio33"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear2_active: cam_sensor_rear2_active { + /* RESET, STANDBY */ + mux { + pins = "gpio48","gpio51"; + function = "gpio"; + }; + + config { + pins = "gpio48","gpio51"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear2_suspend: cam_sensor_rear2_suspend { + /* RESET, STANDBY */ + mux { + pins = "gpio48","gpio51"; + function = "gpio"; + }; + config { + pins = "gpio48","gpio51"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_active: cam_sensor_mclk2_active { + /* MCLK1 */ + mux { + /* CLK, DATA */ + pins = "gpio34"; + function = "cam_mclk"; + }; + + config { + pins = "gpio34"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend { + /* MCLK1 */ + mux { + /* CLK, DATA */ + pins = "gpio34"; + function = "cam_mclk"; + }; + + config { + pins = "gpio34"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_active: cam_sensor_front_active { + /* RESET VANA*/ + mux { + pins = "gpio47", "gpio44"; + function = "gpio"; + }; + + config { + pins = "gpio47", "gpio44"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front_suspend: cam_sensor_front_suspend { + /* RESET */ + mux { + pins = "gpio47"; + function = "gpio"; + }; + + config { + pins = "gpio47"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + /* HS UART CONFIGURATION */ blsp1_uart1_active: blsp1_uart1_active { mux { diff --git a/arch/arm/boot/dts/qcom/msmfalcon.dtsi b/arch/arm/boot/dts/qcom/msmfalcon.dtsi index 4da94e2f78f5..edea1eea6752 100644 --- a/arch/arm/boot/dts/qcom/msmfalcon.dtsi +++ b/arch/arm/boot/dts/qcom/msmfalcon.dtsi @@ -1361,12 +1361,14 @@ qcom,proxy-reg-names = "vdd"; clocks = <&clock_mmss MMSS_VIDEO_CORE_CLK>, + <&clock_mmss MMSS_MNOC_AHB_CLK>, <&clock_mmss MMSS_VIDEO_AHB_CLK>, + <&clock_rpmcc MMSSNOC_AXI_CLK>, <&clock_mmss MMSS_VIDEO_AXI_CLK>; - clock-names = "core_clk","iface_clk", - "bus_clk"; - qcom,proxy-clock-names = "core_clk", - "iface_clk","bus_clk"; + clock-names = "core_clk", "mnoc_ahb_clk", "iface_clk", + "noc_axi_clk", "bus_clk"; + qcom,proxy-clock-names = "core_clk", "mnoc_ahb_clk", + "iface_clk", "noc_axi_clk", "bus_clk"; qcom,msm-bus,name = "pil-venus"; qcom,msm-bus,num-cases = <2>; @@ -1995,6 +1997,7 @@ #include "msm-arm-smmu-impl-defs-falcon.dtsi" #include "msmfalcon-common.dtsi" #include "msmfalcon-blsp.dtsi" +#include "msmfalcon-camera.dtsi" #include "msmfalcon-vidc.dtsi" &pm2falcon_gpios { diff --git a/arch/arm/boot/dts/qcom/msmtriton.dtsi b/arch/arm/boot/dts/qcom/msmtriton.dtsi index 50a172ba2eb1..ed58d5d3c683 100644 --- a/arch/arm/boot/dts/qcom/msmtriton.dtsi +++ b/arch/arm/boot/dts/qcom/msmtriton.dtsi @@ -874,12 +874,14 @@ qcom,proxy-reg-names = "vdd"; clocks = <&clock_mmss MMSS_VIDEO_CORE_CLK>, + <&clock_mmss MMSS_MNOC_AHB_CLK>, <&clock_mmss MMSS_VIDEO_AHB_CLK>, + <&clock_rpmcc MMSSNOC_AXI_CLK>, <&clock_mmss MMSS_VIDEO_AXI_CLK>; - clock-names = "core_clk","iface_clk", - "bus_clk"; - qcom,proxy-clock-names = "core_clk", - "iface_clk","bus_clk"; + clock-names = "core_clk", "mnoc_ahb_clk", "iface_clk", + "noc_axi_clk", "bus_clk"; + qcom,proxy-clock-names = "core_clk", "mnoc_ahb_clk", + "iface_clk", "noc_axi_clk", "bus_clk"; qcom,msm-bus,name = "pil-venus"; qcom,msm-bus,num-cases = <2>; diff --git a/drivers/char/adsprpc.c b/drivers/char/adsprpc.c index 7767086df849..c056ad9625b1 100644 --- a/drivers/char/adsprpc.c +++ b/drivers/char/adsprpc.c @@ -58,7 +58,7 @@ #define RPC_TIMEOUT (5 * HZ) #define BALIGN 128 -#define NUM_CHANNELS 3 /*1 adsp, 1 mdsp*/ +#define NUM_CHANNELS 4 /* adsp,sdsp,mdsp,cdsp */ #define NUM_SESSIONS 9 /*8 compute, 1 cpz*/ #define IS_CACHE_ALIGNED(x) (((x) & ((L1_CACHE_BYTES)-1)) == 0) @@ -264,6 +264,13 @@ static struct fastrpc_channel_ctx gcinfo[NUM_CHANNELS] = { .link.link_info.transport = "smem", }, { + .name = "mdsprpc-smd", + .subsys = "modem", + .channel = SMD_APPS_MODEM, + .link.link_info.edge = "mpss", + .link.link_info.transport = "smem", + }, + { .name = "sdsprpc-smd", .subsys = "dsps", .channel = SMD_APPS_DSPS, @@ -271,6 +278,12 @@ static struct fastrpc_channel_ctx gcinfo[NUM_CHANNELS] = { .link.link_info.transport = "smem", .vmid = VMID_SSC_Q6, }, + { + .name = "cdsprpc-smd", + .subsys = "cdsp", + .link.link_info.edge = "cdsp", + .link.link_info.transport = "smem", + }, }; static void fastrpc_buf_free(struct fastrpc_buf *buf, int cache) diff --git a/drivers/iio/adc/qcom-rradc.c b/drivers/iio/adc/qcom-rradc.c index ec774917f4a4..b7504fdd380f 100644 --- a/drivers/iio/adc/qcom-rradc.c +++ b/drivers/iio/adc/qcom-rradc.c @@ -165,10 +165,10 @@ #define FAB_ID_GF 0x30 #define FAB_ID_SMIC 0x11 -#define FG_ADC_RR_CHG_TEMP_GF_OFFSET_UV 1296794 -#define FG_ADC_RR_CHG_TEMP_GF_SLOPE_UV_PER_C 3858 -#define FG_ADC_RR_CHG_TEMP_SMIC_OFFSET_UV 1339518 -#define FG_ADC_RR_CHG_TEMP_SMIC_SLOPE_UV_PER_C 3598 +#define FG_ADC_RR_CHG_TEMP_GF_OFFSET_UV 1303168 +#define FG_ADC_RR_CHG_TEMP_GF_SLOPE_UV_PER_C 3784 +#define FG_ADC_RR_CHG_TEMP_SMIC_OFFSET_UV 1338433 +#define FG_ADC_RR_CHG_TEMP_SMIC_SLOPE_UV_PER_C 3655 #define FG_ADC_RR_CHG_TEMP_OFFSET_MILLI_DEGC 25000 #define FG_ADC_RR_CHG_THRESHOLD_SCALE 4 diff --git a/drivers/mfd/wcd9xxx-utils.c b/drivers/mfd/wcd9xxx-utils.c index 2b0a5f8ce7f2..909e2f77a43e 100644 --- a/drivers/mfd/wcd9xxx-utils.c +++ b/drivers/mfd/wcd9xxx-utils.c @@ -287,7 +287,7 @@ static u32 wcd9xxx_validate_dmic_sample_rate(struct device *dev, return dmic_sample_rate; undefined_rate: - dev_info(dev, "%s: Invalid %s = %d, for mclk %d\n", + dev_dbg(dev, "%s: Invalid %s = %d, for mclk %d\n", __func__, dmic_rate_type, dmic_sample_rate, mclk_rate); dmic_sample_rate = WCD9XXX_DMIC_SAMPLE_RATE_UNDEFINED; diff --git a/drivers/net/wireless/ath/wil6210/Kconfig b/drivers/net/wireless/ath/wil6210/Kconfig index 9e3961c400ac..8f0bde5825d5 100644 --- a/drivers/net/wireless/ath/wil6210/Kconfig +++ b/drivers/net/wireless/ath/wil6210/Kconfig @@ -41,6 +41,17 @@ config WIL6210_TRACING If unsure, say Y to make it easier to debug problems. +config WIL6210_WRITE_IOCTL + bool "wil6210 write ioctl to the device" + depends on WIL6210 + default n + ---help--- + Say Y here to allow write-access from user-space to + the device memory through ioctl. This is useful for + debugging purposes only. + + If unsure, say N. + config WIL6210_PLATFORM_MSM bool "wil6210 MSM platform specific support" depends on WIL6210 diff --git a/drivers/net/wireless/ath/wil6210/ioctl.c b/drivers/net/wireless/ath/wil6210/ioctl.c index 47058ccccb5b..bbdd232df3b7 100644 --- a/drivers/net/wireless/ath/wil6210/ioctl.c +++ b/drivers/net/wireless/ath/wil6210/ioctl.c @@ -87,10 +87,12 @@ static int wil_ioc_memio_dword(struct wil6210_priv *wil, void __user *data) io.val = readl(a); need_copy = true; break; +#if defined(CONFIG_WIL6210_WRITE_IOCTL) case wil_mmio_write: writel(io.val, a); wmb(); /* make sure write propagated to HW */ break; +#endif default: wil_err(wil, "Unsupported operation, op = 0x%08x\n", io.op); return -EINVAL; @@ -147,6 +149,7 @@ static int wil_ioc_memio_block(struct wil6210_priv *wil, void __user *data) goto out_free; } break; +#if defined(CONFIG_WIL6210_WRITE_IOCTL) case wil_mmio_write: if (copy_from_user(block, io.block, io.size)) { rc = -EFAULT; @@ -156,6 +159,7 @@ static int wil_ioc_memio_block(struct wil6210_priv *wil, void __user *data) wmb(); /* make sure write propagated to HW */ wil_hex_dump_ioctl("Write ", block, io.size); break; +#endif default: wil_err(wil, "Unsupported operation, op = 0x%08x\n", io.op); rc = -EINVAL; diff --git a/drivers/regulator/msm_gfx_ldo.c b/drivers/regulator/msm_gfx_ldo.c index 3c0cc9a74cd7..d2f743b8089a 100644 --- a/drivers/regulator/msm_gfx_ldo.c +++ b/drivers/regulator/msm_gfx_ldo.c @@ -27,11 +27,13 @@ #include <linux/regulator/of_regulator.h> #include <linux/slab.h> #include <linux/uaccess.h> +#include <linux/regulator/msm-ldo-regulator.h> #define LDO_ATEST_REG 0x0 #define LDO_CFG0_REG 0x4 #define LDO_CFG1_REG 0x8 #define LDO_CFG2_REG 0xC +#define LDO_LD_DATA_REG 0x10 #define LDO_VREF_TEST_CFG 0x14 #define ENABLE_LDO_STATUS_BIT (BIT(8) | BIT(12)) @@ -46,6 +48,7 @@ #define LDO_CLAMP_IO_BIT BIT(31) #define CPR_BYPASS_IN_LDO_MODE_BIT BIT(30) #define EN_LDOAP_CTRL_CPR_BIT BIT(29) +#define CX_CPR_BYPASS_IN_LDO_MODE_BIT BIT(10) #define PWR_SRC_SEL_BIT BIT(9) #define ACK_SW_OVR_BIT BIT(8) #define LDO_PREON_SW_OVR_BIT BIT(7) @@ -63,6 +66,10 @@ #define LDO_READY_BIT BIT(2) #define BHS_EN_REST_ACK_BIT BIT(1) +#define REF_CURRENT_X1_REG 0x2C +#define REF_CURRENT_X2_REG 0x30 +#define ADC_CTL_REG 0x34 + #define MIN_LDO_VOLTAGE 375000 #define MAX_LDO_VOLTAGE 980000 #define LDO_STEP_VOLATGE 5000 @@ -76,17 +83,17 @@ #define GFX_LDO_FUSE_STEP_VOLT 10000 #define GFX_LDO_FUSE_SIZE 5 -enum regulator_mode { - LDO, - BHS, -}; - enum direction { NO_CHANGE, UP, DOWN, }; +enum voltage_handling { + VOLTAGE, + CORNER, +}; + struct fuse_param { unsigned row; unsigned bit_start; @@ -127,10 +134,11 @@ struct msm_gfx_ldo { phys_addr_t ldo_addr; bool vreg_enabled; - enum regulator_mode mode; + enum msm_ldo_supply_mode mode; u32 corner; int ldo_voltage_uv; struct mutex ldo_mutex; + enum voltage_handling ops_type; }; #define MSM8953_LDO_FUSE_CORNERS 3 @@ -144,6 +152,19 @@ static struct ldo_config msm8953_ldo_config[] = { {LDO_MAX_OFFSET, LDO_MAX_OFFSET}, }; +static struct ldo_config msmfalcon_ldo_config[] = { + {LDO_ATEST_REG, 0x00000080}, + {LDO_CFG0_REG, 0x0100A600}, + {LDO_CFG1_REG, 0x000000A0}, + {LDO_CFG2_REG, 0x0000C3FE}, + {LDO_LD_DATA_REG, 0x00000000}, + {LDO_VREF_TEST_CFG, 0x00401100}, + {REF_CURRENT_X1_REG, 0x00000230}, + {REF_CURRENT_X2_REG, 0x00000048}, + {ADC_CTL_REG, 0x00000000}, + {LDO_MAX_OFFSET, LDO_MAX_OFFSET}, +}; + static struct fuse_param msm8953_ldo_enable_param[] = { {65, 11, 11}, {}, @@ -162,6 +183,11 @@ static const int msm8953_fuse_ref_volt[MSM8953_LDO_FUSE_CORNERS] = { 720000, }; +enum { + MSM8953_SOC_ID, + MSMFALCON_SOC_ID, +}; + static int convert_open_loop_voltage_fuse(int ref_volt, int step_volt, u32 fuse, int fuse_len) { @@ -209,14 +235,14 @@ static int read_fuse_param(void __iomem *fuse_base_addr, return 0; } -static enum regulator_mode get_operating_mode(struct msm_gfx_ldo *ldo_vreg, +static enum msm_ldo_supply_mode get_operating_mode(struct msm_gfx_ldo *ldo_vreg, int corner) { if (!ldo_vreg->ldo_mode_disable && ldo_vreg->ldo_fuse_enable && ldo_vreg->ldo_corner_en_map[corner]) - return LDO; + return LDO_MODE; - return BHS; + return BHS_MODE; } static char *register_str[] = { @@ -247,14 +273,12 @@ static void dump_registers(struct msm_gfx_ldo *ldo_vreg, char *func) #define GET_VREF(a) DIV_ROUND_UP(a - MIN_LDO_VOLTAGE, LDO_STEP_VOLATGE) -static void configure_ldo_voltage(struct msm_gfx_ldo *ldo_vreg, int new_corner) +static void configure_ldo_voltage(struct msm_gfx_ldo *ldo_vreg, int new_uv) { - int new_uv = 0, val = 0; + int val = 0; u32 reg = 0; - new_uv = ldo_vreg->open_loop_volt[new_corner]; val = GET_VREF(new_uv); - reg = readl_relaxed(ldo_vreg->ldo_base + LDO_VREF_SET_REG); /* set the new voltage */ @@ -266,6 +290,9 @@ static void configure_ldo_voltage(struct msm_gfx_ldo *ldo_vreg, int new_corner) reg |= UPDATE_VREF_BIT; writel_relaxed(reg, ldo_vreg->ldo_base + LDO_VREF_SET_REG); + /* complete the writes */ + mb(); + reg &= ~UPDATE_VREF_BIT; writel_relaxed(reg, ldo_vreg->ldo_base + LDO_VREF_SET_REG); @@ -275,12 +302,12 @@ static void configure_ldo_voltage(struct msm_gfx_ldo *ldo_vreg, int new_corner) mb(); } -static int ldo_update_voltage(struct msm_gfx_ldo *ldo_vreg, int new_corner) +static int ldo_update_voltage(struct msm_gfx_ldo *ldo_vreg, int new_uv) { int timeout = 50; u32 reg = 0; - configure_ldo_voltage(ldo_vreg, new_corner); + configure_ldo_voltage(ldo_vreg, new_uv); while (--timeout) { reg = readl_relaxed(ldo_vreg->ldo_base + @@ -303,16 +330,12 @@ static int ldo_update_voltage(struct msm_gfx_ldo *ldo_vreg, int new_corner) return 0; } -static int enable_ldo_mode(struct msm_gfx_ldo *ldo_vreg) +static int enable_ldo_mode(struct msm_gfx_ldo *ldo_vreg, int new_uv) { u32 ctl = 0; /* set the ldo-vref */ - configure_ldo_voltage(ldo_vreg, ldo_vreg->corner); - - pr_debug("LDO voltage configured =%d uV corner=%d\n", - ldo_vreg->ldo_voltage_uv, - ldo_vreg->corner + MIN_CORNER_OFFSET); + configure_ldo_voltage(ldo_vreg, new_uv); /* configure the LDO for power-up */ ctl = readl_relaxed(ldo_vreg->ldo_base + PWRSWITCH_CTRL_REG); @@ -342,8 +365,10 @@ static int enable_ldo_mode(struct msm_gfx_ldo *ldo_vreg) writel_relaxed(ctl, ldo_vreg->ldo_base + PWRSWITCH_CTRL_REG); /* put CPR in bypass mode */ - ctl |= CPR_BYPASS_IN_LDO_MODE_BIT; - writel_relaxed(ctl, ldo_vreg->ldo_base + PWRSWITCH_CTRL_REG); + if (ldo_vreg->ops_type == CORNER) { + ctl |= CPR_BYPASS_IN_LDO_MODE_BIT; + writel_relaxed(ctl, ldo_vreg->ldo_base + PWRSWITCH_CTRL_REG); + } /* complete all writes */ mb(); @@ -367,9 +392,11 @@ static int enable_bhs_mode(struct msm_gfx_ldo *ldo_vreg) ctl &= ~PWR_SRC_SEL_BIT; writel_relaxed(ctl, ldo_vreg->ldo_base + PWRSWITCH_CTRL_REG); - /* clear CPR in by-pass mode */ - ctl &= ~CPR_BYPASS_IN_LDO_MODE_BIT; - writel_relaxed(ctl, ldo_vreg->ldo_base + PWRSWITCH_CTRL_REG); + if (ldo_vreg->ops_type == CORNER) { + /* clear GFX CPR in by-pass mode */ + ctl &= ~CPR_BYPASS_IN_LDO_MODE_BIT; + writel_relaxed(ctl, ldo_vreg->ldo_base + PWRSWITCH_CTRL_REG); + } /* Enable the BHS control signals to gdsc */ ctl &= ~BHS_EN_FEW_BIT; @@ -386,11 +413,11 @@ static int enable_bhs_mode(struct msm_gfx_ldo *ldo_vreg) return 0; } -static int msm_gfx_ldo_enable(struct regulator_dev *rdev) +static int msm_gfx_ldo_corner_enable(struct regulator_dev *rdev) { struct msm_gfx_ldo *ldo_vreg = rdev_get_drvdata(rdev); - int rc = 0; - enum regulator_mode enable_mode; + int rc = 0, new_uv; + enum msm_ldo_supply_mode enable_mode; mutex_lock(&ldo_vreg->ldo_mutex); @@ -415,19 +442,24 @@ static int msm_gfx_ldo_enable(struct regulator_dev *rdev) } enable_mode = get_operating_mode(ldo_vreg, ldo_vreg->corner); - if (enable_mode == LDO) - rc = enable_ldo_mode(ldo_vreg); - else + if (enable_mode == LDO_MODE) { + new_uv = ldo_vreg->open_loop_volt[ldo_vreg->corner]; + rc = enable_ldo_mode(ldo_vreg, new_uv); + pr_debug("LDO voltage configured =%d uV corner=%d\n", + ldo_vreg->ldo_voltage_uv, + ldo_vreg->corner + MIN_CORNER_OFFSET); + } else { rc = enable_bhs_mode(ldo_vreg); + } if (rc) { pr_err("Failed to enable regulator in %s mode rc=%d\n", - (enable_mode == LDO) ? "LDO" : "BHS", rc); + (enable_mode == LDO_MODE) ? "LDO" : "BHS", rc); goto disable_cx; } pr_debug("regulator_enable complete. mode=%s, corner=%d\n", - (enable_mode == LDO) ? "LDO" : "BHS", + (enable_mode == LDO_MODE) ? "LDO" : "BHS", ldo_vreg->corner + MIN_CORNER_OFFSET); ldo_vreg->mode = enable_mode; @@ -471,15 +503,17 @@ done: return rc; } -static int switch_mode_to_ldo(struct msm_gfx_ldo *ldo_vreg, int new_corner) +static int switch_mode_to_ldo(struct msm_gfx_ldo *ldo_vreg, int new_uv) { u32 ctl = 0, status = 0, timeout = 50; ctl = readl_relaxed(ldo_vreg->ldo_base + PWRSWITCH_CTRL_REG); - /* enable CPR bypass mode for LDO */ - ctl |= CPR_BYPASS_IN_LDO_MODE_BIT; - writel_relaxed(ctl, ldo_vreg->ldo_base + PWRSWITCH_CTRL_REG); + if (ldo_vreg->ops_type == CORNER) { + /* enable CPR bypass mode for LDO */ + ctl |= CPR_BYPASS_IN_LDO_MODE_BIT; + writel_relaxed(ctl, ldo_vreg->ldo_base + PWRSWITCH_CTRL_REG); + } /* fake ack to GDSC */ ctl |= ACK_SW_OVR_BIT; @@ -512,7 +546,7 @@ static int switch_mode_to_ldo(struct msm_gfx_ldo *ldo_vreg, int new_corner) writel_relaxed(ctl, ldo_vreg->ldo_base + PWRSWITCH_CTRL_REG); /* set the new LDO voltage */ - ldo_update_voltage(ldo_vreg, new_corner); + ldo_update_voltage(ldo_vreg, new_uv); pr_debug("LDO voltage =%d uV\n", ldo_vreg->ldo_voltage_uv); @@ -616,9 +650,11 @@ static int switch_mode_to_bhs(struct msm_gfx_ldo *ldo_vreg) ctl &= ~BHS_UNDER_SW_CTL; writel_relaxed(ctl, ldo_vreg->ldo_base + PWRSWITCH_CTRL_REG); - /* Enable CPR in BHS mode */ - ctl &= ~CPR_BYPASS_IN_LDO_MODE_BIT; - writel_relaxed(ctl, ldo_vreg->ldo_base + PWRSWITCH_CTRL_REG); + if (ldo_vreg->ops_type == CORNER) { + /* Enable CPR in BHS mode */ + ctl &= ~CPR_BYPASS_IN_LDO_MODE_BIT; + writel_relaxed(ctl, ldo_vreg->ldo_base + PWRSWITCH_CTRL_REG); + } /* make sure that all configuration is complete */ mb(); @@ -628,12 +664,12 @@ static int switch_mode_to_bhs(struct msm_gfx_ldo *ldo_vreg) return 0; } -static int msm_gfx_ldo_set_voltage(struct regulator_dev *rdev, +static int msm_gfx_ldo_set_corner(struct regulator_dev *rdev, int corner, int corner_max, unsigned *selector) { struct msm_gfx_ldo *ldo_vreg = rdev_get_drvdata(rdev); - int rc = 0, mem_acc_corner; - enum regulator_mode new_mode; + int rc = 0, mem_acc_corner, new_uv; + enum msm_ldo_supply_mode new_mode; enum direction dir = NO_CHANGE; corner -= MIN_CORNER_OFFSET; @@ -645,7 +681,7 @@ static int msm_gfx_ldo_set_voltage(struct regulator_dev *rdev, goto done; pr_debug("set-voltage requested: old_mode=%s old_corner=%d new_corner=%d vreg_enabled=%d\n", - ldo_vreg->mode == BHS ? "BHS" : "LDO", + ldo_vreg->mode == BHS_MODE ? "BHS" : "LDO", ldo_vreg->corner + MIN_CORNER_OFFSET, corner + MIN_CORNER_OFFSET, ldo_vreg->vreg_enabled); @@ -679,21 +715,23 @@ static int msm_gfx_ldo_set_voltage(struct regulator_dev *rdev, new_mode = get_operating_mode(ldo_vreg, corner); - if (new_mode == BHS) { - if (ldo_vreg->mode == LDO) { + if (new_mode == BHS_MODE) { + if (ldo_vreg->mode == LDO_MODE) { rc = switch_mode_to_bhs(ldo_vreg); if (rc) pr_err("Switch to BHS corner=%d failed rc=%d\n", corner + MIN_CORNER_OFFSET, rc); } } else { /* new mode - LDO */ - if (ldo_vreg->mode == BHS) { - rc = switch_mode_to_ldo(ldo_vreg, corner); + new_uv = ldo_vreg->open_loop_volt[ldo_vreg->corner]; + + if (ldo_vreg->mode == BHS_MODE) { + rc = switch_mode_to_ldo(ldo_vreg, new_uv); if (rc) pr_err("Switch to LDO failed corner=%d rc=%d\n", corner + MIN_CORNER_OFFSET, rc); } else { - rc = ldo_update_voltage(ldo_vreg, corner); + rc = ldo_update_voltage(ldo_vreg, new_uv); if (rc) pr_err("Update voltage failed corner=%d rc=%d\n", corner + MIN_CORNER_OFFSET, rc); @@ -702,8 +740,8 @@ static int msm_gfx_ldo_set_voltage(struct regulator_dev *rdev, if (!rc) { pr_debug("set-voltage complete. old_mode=%s new_mode=%s old_corner=%d new_corner=%d\n", - ldo_vreg->mode == BHS ? "BHS" : "LDO", - new_mode == BHS ? "BHS" : "LDO", + ldo_vreg->mode == BHS_MODE ? "BHS" : "LDO", + new_mode == BHS_MODE ? "BHS" : "LDO", ldo_vreg->corner + MIN_CORNER_OFFSET, corner + MIN_CORNER_OFFSET); @@ -721,7 +759,7 @@ done: return rc; } -static int msm_gfx_ldo_get_voltage(struct regulator_dev *rdev) +static int msm_gfx_ldo_get_corner(struct regulator_dev *rdev) { struct msm_gfx_ldo *ldo_vreg = rdev_get_drvdata(rdev); @@ -736,11 +774,132 @@ static int msm_gfx_ldo_is_enabled(struct regulator_dev *rdev) } static struct regulator_ops msm_gfx_ldo_corner_ops = { - .enable = msm_gfx_ldo_enable, + .enable = msm_gfx_ldo_corner_enable, + .disable = msm_gfx_ldo_disable, + .is_enabled = msm_gfx_ldo_is_enabled, + .set_voltage = msm_gfx_ldo_set_corner, + .get_voltage = msm_gfx_ldo_get_corner, +}; + +static int msm_gfx_ldo_get_bypass(struct regulator_dev *rdev, + bool *enable) +{ + struct msm_gfx_ldo *ldo_vreg = rdev_get_drvdata(rdev); + + *enable = ldo_vreg->mode; + + return 0; +} + +static int msm_gfx_ldo_set_bypass(struct regulator_dev *rdev, + bool mode) +{ + struct msm_gfx_ldo *ldo_vreg = rdev_get_drvdata(rdev); + int rc = 0; + + mutex_lock(&ldo_vreg->ldo_mutex); + + if (ldo_vreg->mode == mode || !ldo_vreg->vreg_enabled) + goto done; + + if (mode == LDO_MODE) + rc = switch_mode_to_ldo(ldo_vreg, ldo_vreg->ldo_voltage_uv); + else + rc = switch_mode_to_bhs(ldo_vreg); + + if (rc) { + pr_err("Failed to configure regulator in %s mode rc=%d\n", + (mode == LDO_MODE) ? "LDO" : "BHS", rc); + goto done; + } + + pr_debug("regulator_set_bypass complete. mode=%s, voltage = %d uV\n", + (mode == LDO_MODE) ? "LDO" : "BHS", + (mode == LDO_MODE) ? ldo_vreg->ldo_voltage_uv : 0); + + ldo_vreg->mode = mode; + +done: + mutex_unlock(&ldo_vreg->ldo_mutex); + return rc; +} + +static int msm_gfx_ldo_voltage_enable(struct regulator_dev *rdev) +{ + struct msm_gfx_ldo *ldo_vreg = rdev_get_drvdata(rdev); + int rc = 0; + enum msm_ldo_supply_mode enable_mode; + + mutex_lock(&ldo_vreg->ldo_mutex); + + pr_debug("regulator_enable requested. voltage=%d\n", + ldo_vreg->ldo_voltage_uv); + + enable_mode = ldo_vreg->mode; + + if (enable_mode == LDO_MODE) + rc = enable_ldo_mode(ldo_vreg, ldo_vreg->ldo_voltage_uv); + else + rc = enable_bhs_mode(ldo_vreg); + + if (rc) { + pr_err("Failed to enable regulator in %s mode rc=%d\n", + (enable_mode == LDO_MODE) ? "LDO" : "BHS", rc); + goto fail; + } + + pr_debug("regulator_enable complete. mode=%s, voltage = %d uV\n", + (enable_mode == LDO_MODE) ? "LDO" : "BHS", + (enable_mode == LDO_MODE) ? ldo_vreg->ldo_voltage_uv : 0); + + ldo_vreg->vreg_enabled = true; + +fail: + mutex_unlock(&ldo_vreg->ldo_mutex); + return rc; +} + +static int msm_gfx_ldo_set_voltage(struct regulator_dev *rdev, + int new_uv, int max_uv, unsigned *selector) +{ + struct msm_gfx_ldo *ldo_vreg = rdev_get_drvdata(rdev); + int rc = 0; + + mutex_lock(&ldo_vreg->ldo_mutex); + + if (new_uv == ldo_vreg->ldo_voltage_uv) + goto done; + + if (!ldo_vreg->vreg_enabled || ldo_vreg->mode != LDO_MODE) { + ldo_vreg->ldo_voltage_uv = new_uv; + goto done; + } + + /* update LDO voltage */ + rc = ldo_update_voltage(ldo_vreg, new_uv); + if (rc) + pr_err("Update voltage failed for [%d, %d], rc=%d\n", + new_uv, max_uv, rc); +done: + mutex_unlock(&ldo_vreg->ldo_mutex); + return rc; +} + +static int msm_gfx_ldo_get_voltage(struct regulator_dev *rdev) +{ + struct msm_gfx_ldo *ldo_vreg = rdev_get_drvdata(rdev); + + return ldo_vreg->ldo_voltage_uv; +} + +static struct regulator_ops msm_gfx_ldo_voltage_ops = { + .enable = msm_gfx_ldo_voltage_enable, .disable = msm_gfx_ldo_disable, .is_enabled = msm_gfx_ldo_is_enabled, .set_voltage = msm_gfx_ldo_set_voltage, .get_voltage = msm_gfx_ldo_get_voltage, + .set_bypass = msm_gfx_ldo_set_bypass, + .get_bypass = msm_gfx_ldo_get_bypass, }; static int msm_gfx_ldo_adjust_init_voltage(struct msm_gfx_ldo *ldo_vreg) @@ -764,6 +923,9 @@ static int msm_gfx_ldo_adjust_init_voltage(struct msm_gfx_ldo *ldo_vreg) volt_adjust = devm_kcalloc(ldo_vreg->dev, size, sizeof(*volt_adjust), GFP_KERNEL); + if (!volt_adjust) + return -ENOMEM; + rc = of_property_read_u32_array(of_node, prop_name, volt_adjust, size); if (rc) { pr_err("failed to read %s property rc=%d\n", prop_name, rc); @@ -950,7 +1112,7 @@ static int msm_gfx_ldo_init(struct platform_device *pdev, { struct resource *res; u32 len, ctl; - int rc, i = 0; + int i = 0; res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ldo_addr"); if (!res || !res->start) { @@ -969,12 +1131,6 @@ static int msm_gfx_ldo_init(struct platform_device *pdev, return -EINVAL; } - rc = msm_gfx_ldo_mem_acc_init(ldo_vreg); - if (rc) { - pr_err("Unable to initialize mem_acc rc=%d\n", rc); - return rc; - } - /* HW initialization */ /* clear clamp_io, enable CPR in auto-bypass*/ @@ -1117,7 +1273,6 @@ static int msm_gfx_ldo_target_init(struct msm_gfx_ldo *ldo_vreg) ldo_vreg->init_volt_param[i] = msm8953_init_voltage_param[i]; - ldo_vreg->ldo_init_config = msm8953_ldo_config; ldo_vreg->ref_volt = msm8953_fuse_ref_volt; ldo_vreg->ldo_enable_param = msm8953_ldo_enable_param; @@ -1156,7 +1311,7 @@ static int debugfs_ldo_set_voltage(void *data, u64 val) mutex_lock(&ldo_vreg->ldo_mutex); - if (ldo_vreg->mode == BHS || !ldo_vreg->vreg_enabled || + if (ldo_vreg->mode == BHS_MODE || !ldo_vreg->vreg_enabled || val > MAX_LDO_VOLTAGE || val < MIN_LDO_VOLTAGE) { rc = -EINVAL; goto done; @@ -1174,6 +1329,9 @@ static int debugfs_ldo_set_voltage(void *data, u64 val) reg |= UPDATE_VREF_BIT; writel_relaxed(reg, ldo_vreg->ldo_base + LDO_VREF_SET_REG); + /* complete the writes */ + mb(); + reg &= ~UPDATE_VREF_BIT; writel_relaxed(reg, ldo_vreg->ldo_base + LDO_VREF_SET_REG); @@ -1210,7 +1368,7 @@ static int debugfs_ldo_get_voltage(void *data, u64 *val) mutex_lock(&ldo_vreg->ldo_mutex); - if (ldo_vreg->mode == BHS || !ldo_vreg->vreg_enabled) { + if (ldo_vreg->mode == BHS_MODE || !ldo_vreg->vreg_enabled) { rc = -EINVAL; goto done; } @@ -1250,7 +1408,7 @@ static ssize_t msm_gfx_ldo_debug_info_read(struct file *file, char __user *buff, len = snprintf(debugfs_buf + ret, PAGE_SIZE - ret, "Regulator_enable = %d Regulator mode = %s Corner = %d LDO-voltage = %d uV\n", ldo_vreg->vreg_enabled, - ldo_vreg->mode == BHS ? "BHS" : "LDO", + ldo_vreg->mode == BHS_MODE ? "BHS" : "LDO", ldo_vreg->corner + MIN_CORNER_OFFSET, ldo_vreg->ldo_voltage_uv); ret += len; @@ -1313,6 +1471,57 @@ static void msm_gfx_ldo_debugfs_remove(struct msm_gfx_ldo *ldo_vreg) debugfs_remove_recursive(ldo_vreg->debugfs); } +static int msm_gfx_ldo_corner_config_init(struct msm_gfx_ldo *ldo_vreg, + struct platform_device *pdev) +{ + int rc; + + rc = msm_gfx_ldo_target_init(ldo_vreg); + if (rc) { + pr_err("Unable to initialize target specific data rc=%d", rc); + return rc; + } + + rc = msm_gfx_ldo_parse_dt(ldo_vreg); + if (rc) { + pr_err("Unable to pasrse dt rc=%d\n", rc); + return rc; + } + + rc = msm_gfx_ldo_efuse_init(pdev, ldo_vreg); + if (rc) { + pr_err("efuse_init failed rc=%d\n", rc); + return rc; + } + + rc = msm_gfx_ldo_voltage_init(ldo_vreg); + if (rc) { + pr_err("ldo_voltage_init failed rc=%d\n", rc); + return rc; + } + + rc = msm_gfx_ldo_mem_acc_init(ldo_vreg); + if (rc) { + pr_err("Unable to initialize mem_acc rc=%d\n", rc); + return rc; + } + + return rc; +}; + +/* Data corresponds to the SoC revision */ +static const struct of_device_id msm_gfx_ldo_match_table[] = { + { + .compatible = "qcom,msm8953-gfx-ldo", + .data = (void *)(uintptr_t)MSM8953_SOC_ID, + }, + { + .compatible = "qcom,msmfalcon-gfx-ldo", + .data = (void *)(uintptr_t)MSMFALCON_SOC_ID, + }, + {} +}; + static int msm_gfx_ldo_probe(struct platform_device *pdev) { struct msm_gfx_ldo *ldo_vreg; @@ -1320,13 +1529,18 @@ static int msm_gfx_ldo_probe(struct platform_device *pdev) struct regulator_desc *rdesc; struct regulator_init_data *init_data = pdev->dev.platform_data; struct device *dev = &pdev->dev; - int rc; + const struct of_device_id *match; + int soc_id, rc; + + match = of_match_device(msm_gfx_ldo_match_table, dev); + if (!match) + return -ENODEV; ldo_vreg = devm_kzalloc(dev, sizeof(*ldo_vreg), GFP_KERNEL); if (!ldo_vreg) return -ENOMEM; - init_data = of_get_regulator_init_data(dev, dev->of_node); + init_data = of_get_regulator_init_data(dev, dev->of_node, NULL); if (!init_data) { pr_err("regulator init data is missing\n"); return -EINVAL; @@ -1342,34 +1556,34 @@ static int msm_gfx_ldo_probe(struct platform_device *pdev) return -EINVAL; } + soc_id = (uintptr_t)match->data; ldo_vreg->dev = &pdev->dev; mutex_init(&ldo_vreg->ldo_mutex); platform_set_drvdata(pdev, ldo_vreg); - rc = msm_gfx_ldo_target_init(ldo_vreg); - if (rc) { - pr_err("Unable to initialize target specific data rc=%d", rc); - return rc; - } - - rc = msm_gfx_ldo_parse_dt(ldo_vreg); - if (rc) { - pr_err("Unable to pasrse dt rc=%d\n", rc); - return rc; - } - - rc = msm_gfx_ldo_efuse_init(pdev, ldo_vreg); - if (rc) { - pr_err("efuse_init failed rc=%d\n", rc); - return rc; - } - - rc = msm_gfx_ldo_voltage_init(ldo_vreg); - if (rc) { - pr_err("ldo_voltage_init failed rc=%d\n", rc); - return rc; + switch (soc_id) { + case MSM8953_SOC_ID: + ldo_vreg->ldo_init_config = msm8953_ldo_config; + ldo_vreg->ops_type = CORNER; + rc = msm_gfx_ldo_corner_config_init(ldo_vreg, pdev); + if (rc) { + pr_err("ldo corner handling initialization failed, rc=%d\n", + rc); + return rc; + } + break; + case MSMFALCON_SOC_ID: + ldo_vreg->ldo_init_config = msmfalcon_ldo_config; + ldo_vreg->ops_type = VOLTAGE; + init_data->constraints.valid_ops_mask + |= REGULATOR_CHANGE_BYPASS; + break; + default: + pr_err("invalid SOC ID = %d\n", soc_id); + return -EINVAL; } + /* HW initialization */ rc = msm_gfx_ldo_init(pdev, ldo_vreg); if (rc) { pr_err("ldo_init failed rc=%d\n", rc); @@ -1379,7 +1593,11 @@ static int msm_gfx_ldo_probe(struct platform_device *pdev) rdesc = &ldo_vreg->rdesc; rdesc->owner = THIS_MODULE; rdesc->type = REGULATOR_VOLTAGE; - rdesc->ops = &msm_gfx_ldo_corner_ops; + + if (ldo_vreg->ops_type == CORNER) + rdesc->ops = &msm_gfx_ldo_corner_ops; + else + rdesc->ops = &msm_gfx_ldo_voltage_ops; reg_config.dev = &pdev->dev; reg_config.init_data = init_data; @@ -1408,11 +1626,6 @@ static int msm_gfx_ldo_remove(struct platform_device *pdev) return 0; } -static struct of_device_id msm_gfx_ldo_match_table[] = { - { .compatible = "qcom,msm8953-gfx-ldo", }, - {} -}; - static struct platform_driver msm_gfx_ldo_driver = { .driver = { .name = "qcom,msm-gfx-ldo", diff --git a/drivers/soc/qcom/glink_ssr.c b/drivers/soc/qcom/glink_ssr.c index a14d912b7536..4d94e6446505 100644 --- a/drivers/soc/qcom/glink_ssr.c +++ b/drivers/soc/qcom/glink_ssr.c @@ -80,6 +80,19 @@ struct configure_and_open_ch_work { }; /** + * struct rx_done_ch_work - Work structure used for sending rx_done on + * glink_ssr channels + * handle: G-Link channel handle to be used for sending rx_done + * ptr: Intent pointer data provided in notify rx function + * work: Work structure + */ +struct rx_done_ch_work { + void *handle; + const void *ptr; + struct work_struct work; +}; + +/** * struct close_ch_work - Work structure for used for closing glink_ssr channels * edge: The G-Link edge name for the channel being closed * handle: G-Link channel handle to be closed @@ -102,6 +115,15 @@ static LIST_HEAD(subsystem_list); static atomic_t responses_remaining = ATOMIC_INIT(0); static wait_queue_head_t waitqueue; +static void rx_done_cb_worker(struct work_struct *work) +{ + struct rx_done_ch_work *rx_done_work = + container_of(work, struct rx_done_ch_work, work); + + glink_rx_done(rx_done_work->handle, rx_done_work->ptr, false); + kfree(rx_done_work); +} + static void link_state_cb_worker(struct work_struct *work) { unsigned long flags; @@ -196,7 +218,14 @@ void glink_ssr_notify_rx(void *handle, const void *priv, const void *pkt_priv, { struct ssr_notify_data *cb_data = (struct ssr_notify_data *)priv; struct cleanup_done_msg *resp = (struct cleanup_done_msg *)ptr; + struct rx_done_ch_work *rx_done_work; + rx_done_work = kmalloc(sizeof(*rx_done_work), GFP_ATOMIC); + if (!rx_done_work) { + GLINK_SSR_ERR("<SSR> %s: Could not allocate rx_done_work\n", + __func__); + return; + } if (unlikely(!cb_data)) goto missing_cb_data; if (unlikely(!cb_data->do_cleanup_data)) @@ -221,6 +250,10 @@ void glink_ssr_notify_rx(void *handle, const void *priv, const void *pkt_priv, kfree(cb_data->do_cleanup_data); cb_data->do_cleanup_data = NULL; + rx_done_work->ptr = ptr; + rx_done_work->handle = handle; + INIT_WORK(&rx_done_work->work, rx_done_cb_worker); + queue_work(glink_ssr_wq, &rx_done_work->work); wake_up(&waitqueue); return; diff --git a/drivers/soc/qcom/msm_glink_pkt.c b/drivers/soc/qcom/msm_glink_pkt.c index 490faf89ab76..9ebc6a3c23c9 100644 --- a/drivers/soc/qcom/msm_glink_pkt.c +++ b/drivers/soc/qcom/msm_glink_pkt.c @@ -664,7 +664,16 @@ ssize_t glink_pkt_read(struct file *file, spin_unlock_irqrestore(&devp->pkt_list_lock, flags); ret = copy_to_user(buf, pkt->data, pkt->size); - BUG_ON(ret != 0); + if (ret) { + GLINK_PKT_ERR( + "%s copy_to_user failed ret[%d] on dev id:%d size %zu\n", + __func__, ret, devp->i, pkt->size); + spin_lock_irqsave(&devp->pkt_list_lock, flags); + list_add_tail(&pkt->list, &devp->pkt_list); + spin_unlock_irqrestore(&devp->pkt_list_lock, flags); + return -EFAULT; + } + ret = pkt->size; glink_rx_done(devp->handle, pkt->data, false); @@ -738,7 +747,13 @@ ssize_t glink_pkt_write(struct file *file, } ret = copy_from_user(data, buf, count); - BUG_ON(ret != 0); + if (ret) { + GLINK_PKT_ERR( + "%s copy_from_user failed ret[%d] on dev id:%d size %zu\n", + __func__, ret, devp->i, count); + kfree(data); + return -EFAULT; + } ret = glink_tx(devp->handle, data, data, count, GLINK_TX_REQ_INTENT); if (ret) { diff --git a/drivers/usb/dwc3/dwc3-msm.c b/drivers/usb/dwc3/dwc3-msm.c index 76bf29e78dad..db74e4f4f4d9 100644 --- a/drivers/usb/dwc3/dwc3-msm.c +++ b/drivers/usb/dwc3/dwc3-msm.c @@ -143,6 +143,9 @@ enum plug_orientation { #define B_SESS_VLD 1 #define B_SUSPEND 2 +#define PM_QOS_SAMPLE_SEC 2 +#define PM_QOS_THRESHOLD 400 + struct dwc3_msm { struct device *dev; void __iomem *base; @@ -219,6 +222,9 @@ struct dwc3_msm { unsigned int lpm_to_suspend_delay; bool init; enum plug_orientation typec_orientation; + int pm_qos_latency; + struct pm_qos_request pm_qos_req_dma; + struct delayed_work perf_vote_work; }; #define USB_HSPHY_3P3_VOL_MIN 3050000 /* uV */ @@ -1952,6 +1958,8 @@ static void dwc3_set_phy_speed_flags(struct dwc3_msm *mdwc) } } +static void msm_dwc3_perf_vote_update(struct dwc3_msm *mdwc, + bool perf_mode); static int dwc3_msm_suspend(struct dwc3_msm *mdwc) { @@ -1966,6 +1974,9 @@ static int dwc3_msm_suspend(struct dwc3_msm *mdwc) return 0; } + cancel_delayed_work_sync(&mdwc->perf_vote_work); + msm_dwc3_perf_vote_update(mdwc, false); + if (!mdwc->in_host_mode) { /* pending device events unprocessed */ for (i = 0; i < dwc->num_event_buffers; i++) { @@ -2244,6 +2255,10 @@ static int dwc3_msm_resume(struct dwc3_msm *mdwc) */ dwc3_pwr_event_handler(mdwc); + if (pm_qos_request_active(&mdwc->pm_qos_req_dma)) + schedule_delayed_work(&mdwc->perf_vote_work, + msecs_to_jiffies(1000 * PM_QOS_SAMPLE_SEC)); + dbg_event(0xFF, "Ctl Res", atomic_read(&dwc->in_lpm)); return 0; @@ -2702,6 +2717,7 @@ static ssize_t mode_store(struct device *dev, struct device_attribute *attr, } static DEVICE_ATTR_RW(mode); +static void msm_dwc3_perf_vote_work(struct work_struct *w); static int dwc3_msm_probe(struct platform_device *pdev) { @@ -2737,6 +2753,7 @@ static int dwc3_msm_probe(struct platform_device *pdev) INIT_WORK(&mdwc->bus_vote_w, dwc3_msm_bus_vote_w); INIT_WORK(&mdwc->vbus_draw_work, dwc3_msm_vbus_draw_work); INIT_DELAYED_WORK(&mdwc->sm_work, dwc3_otg_sm_work); + INIT_DELAYED_WORK(&mdwc->perf_vote_work, msm_dwc3_perf_vote_work); mdwc->dwc3_wq = alloc_ordered_workqueue("dwc3_wq", 0); if (!mdwc->dwc3_wq) { @@ -3012,6 +3029,13 @@ static int dwc3_msm_probe(struct platform_device *pdev) if (ret) goto put_dwc3; + ret = of_property_read_u32(node, "qcom,pm-qos-latency", + &mdwc->pm_qos_latency); + if (ret) { + dev_dbg(&pdev->dev, "setting pm-qos-latency to zero.\n"); + mdwc->pm_qos_latency = 0; + } + /* Update initial VBUS/ID state from extcon */ if (mdwc->extcon_vbus && extcon_get_cable_state_(mdwc->extcon_vbus, EXTCON_USB)) @@ -3077,6 +3101,7 @@ static int dwc3_msm_remove(struct platform_device *pdev) clk_prepare_enable(mdwc->xo_clk); } + cancel_delayed_work_sync(&mdwc->perf_vote_work); cancel_delayed_work_sync(&mdwc->sm_work); if (mdwc->hs_phy) @@ -3162,6 +3187,45 @@ static int dwc3_msm_host_notifier(struct notifier_block *nb, return NOTIFY_DONE; } +static void msm_dwc3_perf_vote_update(struct dwc3_msm *mdwc, bool perf_mode) +{ + static bool curr_perf_mode; + int latency = mdwc->pm_qos_latency; + + if ((curr_perf_mode == perf_mode) || !latency) + return; + + if (perf_mode) + pm_qos_update_request(&mdwc->pm_qos_req_dma, latency); + else + pm_qos_update_request(&mdwc->pm_qos_req_dma, + PM_QOS_DEFAULT_VALUE); + + curr_perf_mode = perf_mode; + pr_debug("%s: latency updated to: %d\n", __func__, + perf_mode ? latency : PM_QOS_DEFAULT_VALUE); +} + +static void msm_dwc3_perf_vote_work(struct work_struct *w) +{ + struct dwc3_msm *mdwc = container_of(w, struct dwc3_msm, + perf_vote_work.work); + struct dwc3 *dwc = platform_get_drvdata(mdwc->dwc3); + static unsigned long last_irq_cnt; + bool in_perf_mode = false; + + if (dwc->irq_cnt - last_irq_cnt >= PM_QOS_THRESHOLD) + in_perf_mode = true; + + pr_debug("%s: in_perf_mode:%u, interrupts in last sample:%lu\n", + __func__, in_perf_mode, (dwc->irq_cnt - last_irq_cnt)); + + last_irq_cnt = dwc->irq_cnt; + msm_dwc3_perf_vote_update(mdwc, in_perf_mode); + schedule_delayed_work(&mdwc->perf_vote_work, + msecs_to_jiffies(1000 * PM_QOS_SAMPLE_SEC)); +} + #define VBUS_REG_CHECK_DELAY (msecs_to_jiffies(1000)) /** @@ -3267,6 +3331,16 @@ static int dwc3_otg_start_host(struct dwc3_msm *mdwc, int on) atomic_read(&mdwc->dev->power.usage_count)); pm_runtime_mark_last_busy(mdwc->dev); pm_runtime_put_sync_autosuspend(mdwc->dev); +#ifdef CONFIG_SMP + mdwc->pm_qos_req_dma.type = PM_QOS_REQ_AFFINE_IRQ; + mdwc->pm_qos_req_dma.irq = dwc->irq; +#endif + pm_qos_add_request(&mdwc->pm_qos_req_dma, + PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); + /* start in perf mode for better performance initially */ + msm_dwc3_perf_vote_update(mdwc, true); + schedule_delayed_work(&mdwc->perf_vote_work, + msecs_to_jiffies(1000 * PM_QOS_SAMPLE_SEC)); } else { dev_dbg(mdwc->dev, "%s: turn off host\n", __func__); @@ -3278,6 +3352,10 @@ static int dwc3_otg_start_host(struct dwc3_msm *mdwc, int on) return ret; } + cancel_delayed_work_sync(&mdwc->perf_vote_work); + msm_dwc3_perf_vote_update(mdwc, false); + pm_qos_remove_request(&mdwc->pm_qos_req_dma); + pm_runtime_get_sync(mdwc->dev); dbg_event(0xFF, "StopHost gsync", atomic_read(&mdwc->dev->power.usage_count)); @@ -3359,9 +3437,23 @@ static int dwc3_otg_start_peripheral(struct dwc3_msm *mdwc, int on) dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE); usb_gadget_vbus_connect(&dwc->gadget); +#ifdef CONFIG_SMP + mdwc->pm_qos_req_dma.type = PM_QOS_REQ_AFFINE_IRQ; + mdwc->pm_qos_req_dma.irq = dwc->irq; +#endif + pm_qos_add_request(&mdwc->pm_qos_req_dma, + PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE); + /* start in perf mode for better performance initially */ + msm_dwc3_perf_vote_update(mdwc, true); + schedule_delayed_work(&mdwc->perf_vote_work, + msecs_to_jiffies(1000 * PM_QOS_SAMPLE_SEC)); } else { dev_dbg(mdwc->dev, "%s: turn off gadget %s\n", __func__, dwc->gadget.name); + cancel_delayed_work_sync(&mdwc->perf_vote_work); + msm_dwc3_perf_vote_update(mdwc, false); + pm_qos_remove_request(&mdwc->pm_qos_req_dma); + usb_gadget_vbus_disconnect(&dwc->gadget); usb_phy_notify_disconnect(mdwc->hs_phy, USB_SPEED_HIGH); usb_phy_notify_disconnect(mdwc->ss_phy, USB_SPEED_SUPER); diff --git a/include/net/cfg80211.h b/include/net/cfg80211.h index 195b625a4a76..733a479f3f17 100644 --- a/include/net/cfg80211.h +++ b/include/net/cfg80211.h @@ -67,6 +67,7 @@ struct wiphy; #define CFG80211_CONNECT_PREV_BSSID 1 #define CFG80211_CONNECT_BSS 1 #define CFG80211_ABORT_SCAN 1 +#define CFG80211_UPDATE_CONNECT_PARAMS 1 /* * wireless hardware capability structures @@ -1968,6 +1969,18 @@ struct cfg80211_connect_params { }; /** + * enum cfg80211_connect_params_changed - Connection parameters being updated + * + * This enum provides information of all connect parameters that + * have to be updated as part of update_connect_params() call. + * + * @UPDATE_ASSOC_IES: Indicates whether association request IEs are updated + */ +enum cfg80211_connect_params_changed { + UPDATE_ASSOC_IES = BIT(0), +}; + +/** * enum wiphy_params_flags - set_wiphy_params bitfield values * @WIPHY_PARAM_RETRY_SHORT: wiphy->retry_short has changed * @WIPHY_PARAM_RETRY_LONG: wiphy->retry_long has changed @@ -2382,6 +2395,14 @@ struct cfg80211_qos_map { * If the connection fails for some reason, call cfg80211_connect_result() * with the status from the AP. * (invoked with the wireless_dev mutex held) + * @update_connect_params: Update the connect parameters while connected to a + * BSS. The updated parameters can be used by driver/firmware for + * subsequent BSS selection (roaming) decisions and to form the + * Authentication/(Re)Association Request frames. This call does not + * request an immediate disassociation or reassociation with the current + * BSS, i.e., this impacts only subsequent (re)associations. The bits in + * changed are defined in &enum cfg80211_connect_params_changed. + * (invoked with the wireless_dev mutex held) * @disconnect: Disconnect from the BSS/ESS. * (invoked with the wireless_dev mutex held) * @@ -2652,6 +2673,10 @@ struct cfg80211_ops { int (*connect)(struct wiphy *wiphy, struct net_device *dev, struct cfg80211_connect_params *sme); + int (*update_connect_params)(struct wiphy *wiphy, + struct net_device *dev, + struct cfg80211_connect_params *sme, + u32 changed); int (*disconnect)(struct wiphy *wiphy, struct net_device *dev, u16 reason_code); diff --git a/include/uapi/linux/nl80211.h b/include/uapi/linux/nl80211.h index 441a6b423ad8..cc8ece36e0e3 100644 --- a/include/uapi/linux/nl80211.h +++ b/include/uapi/linux/nl80211.h @@ -322,7 +322,7 @@ * @NL80211_CMD_GET_SCAN: get scan results * @NL80211_CMD_TRIGGER_SCAN: trigger a new scan with the given parameters * %NL80211_ATTR_TX_NO_CCK_RATE is used to decide whether to send the - * probe requests at CCK rate or not. %NL80211_ATTR_MAC can be used to + * probe requests at CCK rate or not. %NL80211_ATTR_BSSID can be used to * specify a BSSID to scan for; if not included, the wildcard BSSID will * be used. * @NL80211_CMD_NEW_SCAN_RESULTS: scan notification (as a reply to @@ -826,6 +826,47 @@ * not running. The driver indicates the status of the scan through * cfg80211_scan_done(). * + * @NL80211_CMD_START_NAN: Start NAN operation, identified by its + * %NL80211_ATTR_WDEV interface. This interface must have been previously + * created with %NL80211_CMD_NEW_INTERFACE. After it has been started, the + * NAN interface will create or join a cluster. This command must have a + * valid %NL80211_ATTR_NAN_MASTER_PREF attribute and optional + * %NL80211_ATTR_NAN_DUAL attributes. + * After this command NAN functions can be added. + * @NL80211_CMD_STOP_NAN: Stop the NAN operation, identified by + * its %NL80211_ATTR_WDEV interface. + * @NL80211_CMD_ADD_NAN_FUNCTION: Add a NAN function. The function is defined + * with %NL80211_ATTR_NAN_FUNC nested attribute. When called, this + * operation returns the strictly positive and unique instance id + * (%NL80211_ATTR_NAN_FUNC_INST_ID) and a cookie (%NL80211_ATTR_COOKIE) + * of the function upon success. + * Since instance ID's can be re-used, this cookie is the right + * way to identify the function. This will avoid races when a termination + * event is handled by the user space after it has already added a new + * function that got the same instance id from the kernel as the one + * which just terminated. + * This cookie may be used in NAN events even before the command + * returns, so userspace shouldn't process NAN events until it processes + * the response to this command. + * Look at %NL80211_ATTR_SOCKET_OWNER as well. + * @NL80211_CMD_DEL_NAN_FUNCTION: Delete a NAN function by cookie. + * This command is also used as a notification sent when a NAN function is + * terminated. This will contain a %NL80211_ATTR_NAN_FUNC_INST_ID + * and %NL80211_ATTR_COOKIE attributes. + * @NL80211_CMD_CHANGE_NAN_CONFIG: Change current NAN configuration. NAN + * must be operational (%NL80211_CMD_START_NAN was executed). + * It must contain at least one of the following attributes: + * %NL80211_ATTR_NAN_MASTER_PREF, %NL80211_ATTR_NAN_DUAL. + * @NL80211_CMD_NAN_FUNC_MATCH: Notification sent when a match is reported. + * This will contain a %NL80211_ATTR_NAN_MATCH nested attribute and + * %NL80211_ATTR_COOKIE. + * + * @NL80211_CMD_UPDATE_CONNECT_PARAMS: Update one or more connect parameters + * for subsequent roaming cases if the driver or firmware uses internal + * BSS selection. This command can be issued only while connected and it + * does not result in a change for the current association. Currently, + * only the %NL80211_ATTR_IE data is used and updated with this command. + * * @NL80211_CMD_MAX: highest used command number * @__NL80211_CMD_AFTER_LAST: internal use */ @@ -1014,6 +1055,17 @@ enum nl80211_commands { NL80211_CMD_ABORT_SCAN, + NL80211_CMD_START_NAN, + NL80211_CMD_STOP_NAN, + NL80211_CMD_ADD_NAN_FUNCTION, + NL80211_CMD_DEL_NAN_FUNCTION, + NL80211_CMD_CHANGE_NAN_CONFIG, + NL80211_CMD_NAN_MATCH, + + NL80211_CMD_SET_MULTICAST_TO_UNICAST, + + NL80211_CMD_UPDATE_CONNECT_PARAMS, + /* add new commands above here */ /* used to define NL80211_CMD_MAX below */ @@ -1818,6 +1870,70 @@ enum nl80211_commands { * %NL80211_ATTR_EXT_CAPA_MASK, to specify the extended capabilities per * interface type. * + * @NL80211_ATTR_MU_MIMO_GROUP_DATA: array of 24 bytes that defines a MU-MIMO + * groupID for monitor mode. + * The first 8 bytes are a mask that defines the membership in each + * group (there are 64 groups, group 0 and 63 are reserved), + * each bit represents a group and set to 1 for being a member in + * that group and 0 for not being a member. + * The remaining 16 bytes define the position in each group: 2 bits for + * each group. + * (smaller group numbers represented on most significant bits and bigger + * group numbers on least significant bits.) + * This attribute is used only if all interfaces are in monitor mode. + * Set this attribute in order to monitor packets using the given MU-MIMO + * groupID data. + * to turn off that feature set all the bits of the groupID to zero. + * @NL80211_ATTR_MU_MIMO_FOLLOW_MAC_ADDR: mac address for the sniffer to follow + * when using MU-MIMO air sniffer. + * to turn that feature off set an invalid mac address + * (e.g. FF:FF:FF:FF:FF:FF) + * + * @NL80211_ATTR_SCAN_START_TIME_TSF: The time at which the scan was actually + * started (u64). The time is the TSF of the BSS the interface that + * requested the scan is connected to (if available, otherwise this + * attribute must not be included). + * @NL80211_ATTR_SCAN_START_TIME_TSF_BSSID: The BSS according to which + * %NL80211_ATTR_SCAN_START_TIME_TSF is set. + * @NL80211_ATTR_MEASUREMENT_DURATION: measurement duration in TUs (u16). If + * %NL80211_ATTR_MEASUREMENT_DURATION_MANDATORY is not set, this is the + * maximum measurement duration allowed. This attribute is used with + * measurement requests. It can also be used with %NL80211_CMD_TRIGGER_SCAN + * if the scan is used for beacon report radio measurement. + * @NL80211_ATTR_MEASUREMENT_DURATION_MANDATORY: flag attribute that indicates + * that the duration specified with %NL80211_ATTR_MEASUREMENT_DURATION is + * mandatory. If this flag is not set, the duration is the maximum duration + * and the actual measurement duration may be shorter. + * + * @NL80211_ATTR_MESH_PEER_AID: Association ID for the mesh peer (u16). This is + * used to pull the stored data for mesh peer in power save state. + * + * @NL80211_ATTR_NAN_MASTER_PREF: the master preference to be used by + * %NL80211_CMD_START_NAN and optionally with + * %NL80211_CMD_CHANGE_NAN_CONFIG. Its type is u8 and it can't be 0. + * Also, values 1 and 255 are reserved for certification purposes and + * should not be used during a normal device operation. + * @NL80211_ATTR_NAN_DUAL: NAN dual band operation config (see + * &enum nl80211_nan_dual_band_conf). This attribute is used with + * %NL80211_CMD_START_NAN and optionally with + * %NL80211_CMD_CHANGE_NAN_CONFIG. + * @NL80211_ATTR_NAN_FUNC: a function that can be added to NAN. See + * &enum nl80211_nan_func_attributes for description of this nested + * attribute. + * @NL80211_ATTR_NAN_MATCH: used to report a match. This is a nested attribute. + * See &enum nl80211_nan_match_attributes. + * @NL80211_ATTR_FILS_KEK: KEK for FILS (Re)Association Request/Response frame + * protection. + * @NL80211_ATTR_FILS_NONCES: Nonces (part of AAD) for FILS (Re)Association + * Request/Response frame protection. This attribute contains the 16 octet + * STA Nonce followed by 16 octets of AP Nonce. + * + * @NL80211_ATTR_MULTICAST_TO_UNICAST_ENABLED: Indicates whether or not multicast + * packets should be send out as unicast to all stations (flag attribute). + * + * @NL80211_ATTR_BSSID: The BSSID of the AP. Note that %NL80211_ATTR_MAC is also + * used in various commands/events for specifying the BSSID. + * * @NUM_NL80211_ATTR: total number of nl80211_attrs available * @NL80211_ATTR_MAX: highest attribute number currently defined * @__NL80211_ATTR_AFTER_LAST: internal use @@ -2202,6 +2318,28 @@ enum nl80211_attrs { NL80211_ATTR_IFTYPE_EXT_CAPA, + NL80211_ATTR_MU_MIMO_GROUP_DATA, + NL80211_ATTR_MU_MIMO_FOLLOW_MAC_ADDR, + + NL80211_ATTR_SCAN_START_TIME_TSF, + NL80211_ATTR_SCAN_START_TIME_TSF_BSSID, + NL80211_ATTR_MEASUREMENT_DURATION, + NL80211_ATTR_MEASUREMENT_DURATION_MANDATORY, + + NL80211_ATTR_MESH_PEER_AID, + + NL80211_ATTR_NAN_MASTER_PREF, + NL80211_ATTR_NAN_DUAL, + NL80211_ATTR_NAN_FUNC, + NL80211_ATTR_NAN_MATCH, + + NL80211_ATTR_FILS_KEK, + NL80211_ATTR_FILS_NONCES, + + NL80211_ATTR_MULTICAST_TO_UNICAST_ENABLED, + + NL80211_ATTR_BSSID, + /* add attributes here, update the policy in nl80211.c */ __NL80211_ATTR_AFTER_LAST, diff --git a/kernel/sched/hmp.c b/kernel/sched/hmp.c index 652e19ea7bb0..a8bf39c6d7d7 100644 --- a/kernel/sched/hmp.c +++ b/kernel/sched/hmp.c @@ -3070,6 +3070,7 @@ const char *sched_window_reset_reasons[] = { "WINDOW_CHANGE", "POLICY_CHANGE", "HIST_SIZE_CHANGE", + "FREQ_AGGREGATE_CHANGE", }; /* Called with IRQs enabled */ diff --git a/net/wireless/nl80211.c b/net/wireless/nl80211.c index e5a1df6fc282..2d71cafde513 100644 --- a/net/wireless/nl80211.c +++ b/net/wireless/nl80211.c @@ -402,6 +402,7 @@ static const struct nla_policy nl80211_policy[NUM_NL80211_ATTR] = { [NL80211_ATTR_SCHED_SCAN_DELAY] = { .type = NLA_U32 }, [NL80211_ATTR_REG_INDOOR] = { .type = NLA_FLAG }, [NL80211_ATTR_PBSS] = { .type = NLA_FLAG }, + [NL80211_ATTR_BSSID] = { .len = ETH_ALEN }, }; /* policy for the key attributes */ @@ -1551,6 +1552,7 @@ static int nl80211_send_wiphy(struct cfg80211_registered_device *rdev, if (rdev->wiphy.features & NL80211_FEATURE_SUPPORTS_WMM_ADMISSION) CMD(add_tx_ts, ADD_TX_TS); + CMD(update_connect_params, UPDATE_CONNECT_PARAMS); } /* add into the if now */ #undef CMD @@ -6323,7 +6325,20 @@ static int nl80211_trigger_scan(struct sk_buff *skb, struct genl_info *info) request->no_cck = nla_get_flag(info->attrs[NL80211_ATTR_TX_NO_CCK_RATE]); - if (info->attrs[NL80211_ATTR_MAC]) + /* Initial implementation used NL80211_ATTR_MAC to set the specific + * BSSID to scan for. This was problematic because that same attribute + * was already used for another purpose (local random MAC address). The + * NL80211_ATTR_BSSID attribute was added to fix this. For backwards + * compatibility with older userspace components, also use the + * NL80211_ATTR_MAC value here if it can be determined to be used for + * the specific BSSID use case instead of the random MAC address + * (NL80211_ATTR_SCAN_FLAGS is used to enable random MAC address use). + */ + if (info->attrs[NL80211_ATTR_BSSID]) + memcpy(request->bssid, + nla_data(info->attrs[NL80211_ATTR_BSSID]), ETH_ALEN); + else if (!(request->flags & NL80211_SCAN_FLAG_RANDOM_ADDR) && + info->attrs[NL80211_ATTR_MAC]) memcpy(request->bssid, nla_data(info->attrs[NL80211_ATTR_MAC]), ETH_ALEN); else @@ -8342,6 +8357,37 @@ static int nl80211_connect(struct sk_buff *skb, struct genl_info *info) return err; } +static int nl80211_update_connect_params(struct sk_buff *skb, + struct genl_info *info) +{ + struct cfg80211_connect_params connect = {}; + struct cfg80211_registered_device *rdev = info->user_ptr[0]; + struct net_device *dev = info->user_ptr[1]; + struct wireless_dev *wdev = dev->ieee80211_ptr; + u32 changed = 0; + int ret; + + if (!rdev->ops->update_connect_params) + return -EOPNOTSUPP; + + if (info->attrs[NL80211_ATTR_IE]) { + if (!is_valid_ie_attr(info->attrs[NL80211_ATTR_IE])) + return -EINVAL; + connect.ie = nla_data(info->attrs[NL80211_ATTR_IE]); + connect.ie_len = nla_len(info->attrs[NL80211_ATTR_IE]); + changed |= UPDATE_ASSOC_IES; + } + + wdev_lock(dev->ieee80211_ptr); + if (!wdev->current_bss) + ret = -ENOLINK; + else + ret = rdev_update_connect_params(rdev, dev, &connect, changed); + wdev_unlock(dev->ieee80211_ptr); + + return ret; +} + static int nl80211_disconnect(struct sk_buff *skb, struct genl_info *info) { struct cfg80211_registered_device *rdev = info->user_ptr[0]; @@ -11230,6 +11276,14 @@ static const struct genl_ops nl80211_ops[] = { NL80211_FLAG_NEED_RTNL, }, { + .cmd = NL80211_CMD_UPDATE_CONNECT_PARAMS, + .doit = nl80211_update_connect_params, + .policy = nl80211_policy, + .flags = GENL_ADMIN_PERM, + .internal_flags = NL80211_FLAG_NEED_NETDEV_UP | + NL80211_FLAG_NEED_RTNL, + }, + { .cmd = NL80211_CMD_DISCONNECT, .doit = nl80211_disconnect, .policy = nl80211_policy, diff --git a/net/wireless/rdev-ops.h b/net/wireless/rdev-ops.h index 966d15247030..b3675ce67a8b 100644 --- a/net/wireless/rdev-ops.h +++ b/net/wireless/rdev-ops.h @@ -489,6 +489,18 @@ static inline int rdev_connect(struct cfg80211_registered_device *rdev, return ret; } +static inline int +rdev_update_connect_params(struct cfg80211_registered_device *rdev, + struct net_device *dev, + struct cfg80211_connect_params *sme, u32 changed) +{ + int ret; + trace_rdev_update_connect_params(&rdev->wiphy, dev, sme, changed); + ret = rdev->ops->update_connect_params(&rdev->wiphy, dev, sme, changed); + trace_rdev_return_int(&rdev->wiphy, ret); + return ret; +} + static inline int rdev_disconnect(struct cfg80211_registered_device *rdev, struct net_device *dev, u16 reason_code) { diff --git a/net/wireless/trace.h b/net/wireless/trace.h index ca24294fe463..500d72ac719a 100644 --- a/net/wireless/trace.h +++ b/net/wireless/trace.h @@ -1243,6 +1243,24 @@ TRACE_EVENT(rdev_connect, __entry->wpa_versions, __entry->flags, MAC_PR_ARG(prev_bssid)) ); +TRACE_EVENT(rdev_update_connect_params, + TP_PROTO(struct wiphy *wiphy, struct net_device *netdev, + struct cfg80211_connect_params *sme, u32 changed), + TP_ARGS(wiphy, netdev, sme, changed), + TP_STRUCT__entry( + WIPHY_ENTRY + NETDEV_ENTRY + __field(u32, changed) + ), + TP_fast_assign( + WIPHY_ASSIGN; + NETDEV_ASSIGN; + __entry->changed = changed; + ), + TP_printk(WIPHY_PR_FMT ", " NETDEV_PR_FMT ", parameters changed: %u", + WIPHY_PR_ARG, NETDEV_PR_ARG, __entry->changed) +); + TRACE_EVENT(rdev_set_cqm_rssi_config, TP_PROTO(struct wiphy *wiphy, struct net_device *netdev, s32 rssi_thold, diff --git a/sound/soc/msm/msm-dai-fe.c b/sound/soc/msm/msm-dai-fe.c index 9c720acf8ef8..bab4da4758ac 100644 --- a/sound/soc/msm/msm-dai-fe.c +++ b/sound/soc/msm/msm-dai-fe.c @@ -506,6 +506,33 @@ static struct snd_soc_dai_driver msm_fe_dais[] = { }, { .playback = { + .stream_name = "SLIMBUS7_HOSTLESS Playback", + .aif_name = "SLIM7_DL_HL", + .rates = SNDRV_PCM_RATE_8000_384000, + .formats = (SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S24_LE), + .channels_min = 1, + .channels_max = 8, + .rate_min = 8000, + .rate_max = 384000, + }, + .capture = { + .stream_name = "SLIMBUS7_HOSTLESS Capture", + .aif_name = "SLIM7_UL_HL", + .rates = SNDRV_PCM_RATE_8000_384000, + .formats = (SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S24_LE), + .channels_min = 1, + .channels_max = 8, + .rate_min = 8000, + .rate_max = 384000, + }, + .ops = &msm_fe_dai_ops, + .name = "SLIMBUS7_HOSTLESS", + .probe = fe_dai_probe, + }, + { + .playback = { .stream_name = "SLIMBUS8_HOSTLESS Playback", .aif_name = "SLIM8_DL_HL", .rates = SNDRV_PCM_RATE_8000_384000, @@ -902,6 +929,22 @@ static struct snd_soc_dai_driver msm_fe_dais[] = { .name = "INT4_MI2S_RX_HOSTLESS", .probe = fe_dai_probe, }, + { + .capture = { + .stream_name = "INT3 MI2S_TX Hostless Capture", + .aif_name = "INT3_MI2S_UL_HL", + .rates = SNDRV_PCM_RATE_8000_48000, + .formats = (SNDRV_PCM_FMTBIT_S16_LE | + SNDRV_PCM_FMTBIT_S24_LE), + .channels_min = 1, + .channels_max = 2, + .rate_min = 8000, + .rate_max = 48000, + }, + .ops = &msm_fe_dai_ops, + .name = "INT3_MI2S_TX_HOSTLESS", + .probe = fe_dai_probe, + }, /* TDM Hostless */ { .capture = { diff --git a/sound/soc/msm/msmfalcon-internal.c b/sound/soc/msm/msmfalcon-internal.c index a40740d02582..5226e791fcff 100644 --- a/sound/soc/msm/msmfalcon-internal.c +++ b/sound/soc/msm/msmfalcon-internal.c @@ -1842,25 +1842,24 @@ static struct snd_soc_dai_link msm_int_dai[] = { .codec_name = "snd-soc-dummy", }, {/* hw:x,11 */ - .name = "SLIMBUS_3 Hostless", - .stream_name = "SLIMBUS_3 Hostless", - .cpu_dai_name = "SLIMBUS3_HOSTLESS", + .name = "INT3 MI2S_TX Hostless", + .stream_name = "INT3 MI2S_TX Hostless", + .cpu_dai_name = "INT3_MI2S_TX_HOSTLESS", .platform_name = "msm-pcm-hostless", .dynamic = 1, .dpcm_capture = 1, - .dpcm_playback = 1, .trigger = {SND_SOC_DPCM_TRIGGER_POST, SND_SOC_DPCM_TRIGGER_POST}, .no_host_mode = SND_SOC_DAI_LINK_NO_HOST, .ignore_suspend = 1, - .ignore_pmdown_time = 1, /* dai link has playback support */ + .ignore_pmdown_time = 1, .codec_dai_name = "snd-soc-dummy-dai", .codec_name = "snd-soc-dummy", }, {/* hw:x,12 */ - .name = "SLIMBUS_4 Hostless", - .stream_name = "SLIMBUS_4 Hostless", - .cpu_dai_name = "SLIMBUS4_HOSTLESS", + .name = "SLIMBUS_7 Hostless", + .stream_name = "SLIMBUS_7 Hostless", + .cpu_dai_name = "SLIMBUS7_HOSTLESS", .platform_name = "msm-pcm-hostless", .dynamic = 1, .dpcm_capture = 1, diff --git a/sound/soc/msm/qdsp6v2/msm-pcm-routing-v2.c b/sound/soc/msm/qdsp6v2/msm-pcm-routing-v2.c index f35958e0e4dd..2639bfd5b8fd 100644 --- a/sound/soc/msm/qdsp6v2/msm-pcm-routing-v2.c +++ b/sound/soc/msm/qdsp6v2/msm-pcm-routing-v2.c @@ -2261,6 +2261,18 @@ static int msm_routing_ec_ref_rx_put(struct snd_kcontrol *kcontrol, msm_route_ec_ref_rx = 19; ec_ref_port_id = AFE_PORT_ID_USB_RX; break; + case 20: + msm_route_ec_ref_rx = 20; + ec_ref_port_id = AFE_PORT_ID_INT0_MI2S_RX; + break; + case 21: + msm_route_ec_ref_rx = 21; + ec_ref_port_id = AFE_PORT_ID_INT4_MI2S_RX; + break; + case 22: + msm_route_ec_ref_rx = 22; + ec_ref_port_id = AFE_PORT_ID_INT3_MI2S_TX; + break; default: msm_route_ec_ref_rx = 0; /* NONE */ pr_err("%s EC ref rx %ld not valid\n", @@ -2281,7 +2293,8 @@ static const char *const ec_ref_rx[] = { "None", "SLIM_RX", "I2S_RX", "TERT_MI2S_TX", "QUAT_MI2S_TX", "SEC_I2S_RX", "PROXY_RX", "SLIM_5_RX", "SLIM_1_TX", "QUAT_TDM_TX_1", "QUAT_TDM_RX_0", "QUAT_TDM_RX_1", "QUAT_TDM_RX_2", "SLIM_6_RX", - "TERT_MI2S_RX", "QUAT_MI2S_RX", "TERT_TDM_TX_0", "USB_AUDIO_RX"}; + "TERT_MI2S_RX", "QUAT_MI2S_RX", "TERT_TDM_TX_0", "USB_AUDIO_RX", + "INT0_MI2S_RX", "INT4_MI2S_RX", "INT3_MI2S_TX"}; static const struct soc_enum msm_route_ec_ref_rx_enum[] = { SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(ec_ref_rx), ec_ref_rx), @@ -6614,6 +6627,66 @@ static const struct snd_kcontrol_new tx_qchat_mixer_controls[] = { msm_routing_put_voice_mixer), }; +static const struct snd_kcontrol_new int0_mi2s_rx_port_mixer_controls[] = { + SOC_SINGLE_EXT("PRI_MI2S_TX", MSM_BACKEND_DAI_INT0_MI2S_RX, + MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_SINGLE_EXT("SEC_MI2S_TX", MSM_BACKEND_DAI_INT0_MI2S_RX, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_SINGLE_EXT("TERT_MI2S_TX", MSM_BACKEND_DAI_INT0_MI2S_RX, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_SINGLE_EXT("QUAT_MI2S_TX", MSM_BACKEND_DAI_INT0_MI2S_RX, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_SINGLE_EXT("INT3_MI2S_TX", MSM_BACKEND_DAI_INT0_MI2S_RX, + MSM_BACKEND_DAI_INT3_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_SINGLE_EXT("INTERNAL_FM_TX", MSM_BACKEND_DAI_INT0_MI2S_RX, + MSM_BACKEND_DAI_INT_FM_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_SINGLE_EXT("INTERNAL_BT_SCO_TX", MSM_BACKEND_DAI_INT0_MI2S_RX, + MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_SINGLE_EXT("SLIM_7_TX", MSM_BACKEND_DAI_INT0_MI2S_RX, + MSM_BACKEND_DAI_SLIMBUS_7_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_SINGLE_EXT("SLIM_8_TX", MSM_BACKEND_DAI_INT0_MI2S_RX, + MSM_BACKEND_DAI_SLIMBUS_8_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +}; + +static const struct snd_kcontrol_new int4_mi2s_rx_port_mixer_controls[] = { + SOC_SINGLE_EXT("PRI_MI2S_TX", MSM_BACKEND_DAI_INT4_MI2S_RX, + MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_SINGLE_EXT("SEC_MI2S_TX", MSM_BACKEND_DAI_INT4_MI2S_RX, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_SINGLE_EXT("TERT_MI2S_TX", MSM_BACKEND_DAI_INT4_MI2S_RX, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_SINGLE_EXT("QUAT_MI2S_TX", MSM_BACKEND_DAI_INT4_MI2S_RX, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_SINGLE_EXT("INT3_MI2S_TX", MSM_BACKEND_DAI_INT4_MI2S_RX, + MSM_BACKEND_DAI_INT3_MI2S_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_SINGLE_EXT("INTERNAL_FM_TX", MSM_BACKEND_DAI_INT4_MI2S_RX, + MSM_BACKEND_DAI_INT_FM_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_SINGLE_EXT("INTERNAL_BT_SCO_TX", MSM_BACKEND_DAI_INT4_MI2S_RX, + MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_SINGLE_EXT("SLIM_7_TX", MSM_BACKEND_DAI_INT4_MI2S_RX, + MSM_BACKEND_DAI_SLIMBUS_7_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), + SOC_SINGLE_EXT("SLIM_8_TX", MSM_BACKEND_DAI_INT4_MI2S_RX, + MSM_BACKEND_DAI_SLIMBUS_8_TX, 1, 0, msm_routing_get_port_mixer, + msm_routing_put_port_mixer), +}; + static const struct snd_kcontrol_new sbus_0_rx_port_mixer_controls[] = { SOC_SINGLE_EXT("INTERNAL_FM_TX", MSM_BACKEND_DAI_SLIMBUS_0_RX, MSM_BACKEND_DAI_INT_FM_TX, 1, 0, msm_routing_get_port_mixer, @@ -7540,6 +7613,11 @@ static const struct snd_kcontrol_new hfp_int_switch_mixer_controls = 0, 1, 0, msm_routing_get_hfp_switch_mixer, msm_routing_put_hfp_switch_mixer); +static const struct snd_kcontrol_new hfp_slim7_switch_mixer_controls = + SOC_SINGLE_EXT("Switch", SND_SOC_NOPM, + 0, 1, 0, msm_routing_get_hfp_switch_mixer, + msm_routing_put_hfp_switch_mixer); + static const struct soc_enum lsm_mux_enum = SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(mad_audio_mux_text), mad_audio_mux_text); @@ -8422,6 +8500,10 @@ static const struct snd_soc_dapm_widget msm_qdsp6_widgets[] = { 0, 0, 0, 0), SND_SOC_DAPM_AIF_OUT("SLIM6_UL_HL", "SLIMBUS6_HOSTLESS Capture", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_IN("SLIM7_DL_HL", "SLIMBUS7_HOSTLESS Playback", + 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("SLIM7_UL_HL", "SLIMBUS7_HOSTLESS Capture", + 0, 0, 0, 0), SND_SOC_DAPM_AIF_IN("SLIM8_DL_HL", "SLIMBUS8_HOSTLESS Playback", 0, 0, 0, 0), SND_SOC_DAPM_AIF_OUT("SLIM8_UL_HL", "SLIMBUS8_HOSTLESS Capture", @@ -8462,6 +8544,9 @@ static const struct snd_soc_dapm_widget msm_qdsp6_widgets[] = { 0, 0, 0, 0), SND_SOC_DAPM_AIF_OUT("MI2S_UL_HL", "MI2S_TX_HOSTLESS Capture", 0, 0, 0, 0), + SND_SOC_DAPM_AIF_OUT("INT3_MI2S_UL_HL", + "INT3 MI2S_TX Hostless Capture", + 0, 0, 0, 0), SND_SOC_DAPM_AIF_OUT("TERT_MI2S_UL_HL", "Tertiary MI2S_TX Hostless Capture", 0, 0, 0, 0), @@ -8971,6 +9056,8 @@ static const struct snd_soc_dapm_widget msm_qdsp6_widgets[] = { &hfp_aux_switch_mixer_controls), SND_SOC_DAPM_SWITCH("HFP_INT_UL_HL", SND_SOC_NOPM, 0, 0, &hfp_int_switch_mixer_controls), + SND_SOC_DAPM_SWITCH("HFP_SLIM7_UL_HL", SND_SOC_NOPM, 0, 0, + &hfp_slim7_switch_mixer_controls), /* Mux Definitions */ SND_SOC_DAPM_MUX("LSM1 MUX", SND_SOC_NOPM, 0, 0, &lsm1_mux), @@ -9241,6 +9328,12 @@ static const struct snd_soc_dapm_widget msm_qdsp6_widgets[] = { slimbus_8_rx_voice_mixer_controls, ARRAY_SIZE(slimbus_8_rx_voice_mixer_controls)), /* port mixer */ + SND_SOC_DAPM_MIXER("INT0_MI2S_RX Port Mixer", + SND_SOC_NOPM, 0, 0, int0_mi2s_rx_port_mixer_controls, + ARRAY_SIZE(int0_mi2s_rx_port_mixer_controls)), + SND_SOC_DAPM_MIXER("INT4_MI2S_RX Port Mixer", + SND_SOC_NOPM, 0, 0, int4_mi2s_rx_port_mixer_controls, + ARRAY_SIZE(int4_mi2s_rx_port_mixer_controls)), SND_SOC_DAPM_MIXER("SLIMBUS_0_RX Port Mixer", SND_SOC_NOPM, 0, 0, sbus_0_rx_port_mixer_controls, ARRAY_SIZE(sbus_0_rx_port_mixer_controls)), @@ -9318,6 +9411,12 @@ static const struct snd_soc_dapm_widget msm_qdsp6_widgets[] = { SND_SOC_DAPM_MIXER("QUAT_TDM_RX_3 Port Mixer", SND_SOC_NOPM, 0, 0, quat_tdm_rx_3_port_mixer_controls, ARRAY_SIZE(quat_tdm_rx_3_port_mixer_controls)), + SND_SOC_DAPM_MIXER("INT0_MI2S_RX Port Mixer", SND_SOC_NOPM, 0, 0, + int0_mi2s_rx_port_mixer_controls, + ARRAY_SIZE(int0_mi2s_rx_port_mixer_controls)), + SND_SOC_DAPM_MIXER("INT4_MI2S_RX Port Mixer", SND_SOC_NOPM, 0, 0, + int4_mi2s_rx_port_mixer_controls, + ARRAY_SIZE(int4_mi2s_rx_port_mixer_controls)), SND_SOC_DAPM_MIXER("QCHAT_Tx Mixer", SND_SOC_NOPM, 0, 0, tx_qchat_mixer_controls, ARRAY_SIZE(tx_qchat_mixer_controls)), @@ -9598,6 +9697,7 @@ static const struct snd_soc_dapm_route intercon[] = { {"MultiMedia18 Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, {"MultiMedia19 Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, {"MultiMedia8 Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"MultiMedia8 Mixer", "INT3_MI2S_TX", "INT3_MI2S_TX"}, {"MultiMedia3 Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, {"MultiMedia5 Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, {"MultiMedia5 Mixer", "SLIM_7_TX", "SLIMBUS_7_TX"}, @@ -10854,13 +10954,17 @@ static const struct snd_soc_dapm_route intercon[] = { {"HFP_AUX_UL_HL", "Switch", "SEC_AUX_PCM_TX"}, {"INTHFP_UL_HL", NULL, "HFP_INT_UL_HL"}, {"HFP_INT_UL_HL", "Switch", "INT_BT_SCO_TX"}, + {"SLIM7_UL_HL", NULL, "HFP_SLIM7_UL_HL"}, + {"HFP_SLIM7_UL_HL", "Switch", "SLIMBUS_7_TX"}, {"AUX_PCM_RX", NULL, "AUXPCM_DL_HL"}, {"AUXPCM_UL_HL", NULL, "AUX_PCM_TX"}, {"MI2S_RX", NULL, "MI2S_DL_HL"}, {"MI2S_UL_HL", NULL, "MI2S_TX"}, {"PCM_RX_DL_HL", "Switch", "SLIM0_DL_HL"}, {"PCM_RX", NULL, "PCM_RX_DL_HL"}, - {"INT0_MI2S_RX_DL_HL", "Switch", "INT0_MI2S_DL_HL"}, + + /* connect to INT4_MI2S_DL_HL since same pcm_id */ + {"INT0_MI2S_RX_DL_HL", "Switch", "INT4_MI2S_DL_HL"}, {"INT0_MI2S_RX", NULL, "INT0_MI2S_RX_DL_HL"}, {"INT4_MI2S_RX_DL_HL", "Switch", "INT4_MI2S_DL_HL"}, {"INT4_MI2S_RX", NULL, "INT4_MI2S_RX_DL_HL"}, @@ -10874,6 +10978,7 @@ static const struct snd_soc_dapm_route intercon[] = { {"QUAT_MI2S_RX_DL_HL", "Switch", "QUAT_MI2S_DL_HL"}, {"QUAT_MI2S_RX", NULL, "QUAT_MI2S_RX_DL_HL"}, {"MI2S_UL_HL", NULL, "TERT_MI2S_TX"}, + {"INT3_MI2S_UL_HL", NULL, "INT3_MI2S_TX"}, {"TERT_MI2S_UL_HL", NULL, "TERT_MI2S_TX"}, {"SEC_I2S_RX", NULL, "SEC_I2S_DL_HL"}, {"PRI_MI2S_UL_HL", NULL, "PRI_MI2S_TX"}, @@ -11047,6 +11152,28 @@ static const struct snd_soc_dapm_route intercon[] = { {"QUAT_TDM_RX_3 Port Mixer", "QUAT_TDM_TX_3", "QUAT_TDM_TX_3"}, {"QUAT_TDM_RX_3", NULL, "QUAT_TDM_RX_3 Port Mixer"}, + {"INT0_MI2S_RX Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"INT0_MI2S_RX Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"INT0_MI2S_RX Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, + {"INT0_MI2S_RX Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, + {"INT0_MI2S_RX Port Mixer", "INT3_MI2S_TX", "INT3_MI2S_TX"}, + {"INT0_MI2S_RX Port Mixer", "SLIM_7_TX", "SLIMBUS_7_TX"}, + {"INT0_MI2S_RX Port Mixer", "SLIM_8_TX", "SLIMBUS_8_TX"}, + {"INT0_MI2S_RX Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, + {"INT0_MI2S_RX Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"INT0_MI2S_RX", NULL, "INT0_MI2S_RX Port Mixer"}, + + {"INT4_MI2S_RX Port Mixer", "PRI_MI2S_TX", "PRI_MI2S_TX"}, + {"INT4_MI2S_RX Port Mixer", "SEC_MI2S_TX", "SEC_MI2S_TX"}, + {"INT4_MI2S_RX Port Mixer", "TERT_MI2S_TX", "TERT_MI2S_TX"}, + {"INT4_MI2S_RX Port Mixer", "QUAT_MI2S_TX", "QUAT_MI2S_TX"}, + {"INT4_MI2S_RX Port Mixer", "INT3_MI2S_TX", "INT3_MI2S_TX"}, + {"INT4_MI2S_RX Port Mixer", "SLIM_7_TX", "SLIMBUS_7_TX"}, + {"INT4_MI2S_RX Port Mixer", "SLIM_8_TX", "SLIMBUS_8_TX"}, + {"INT4_MI2S_RX Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, + {"INT4_MI2S_RX Port Mixer", "INTERNAL_BT_SCO_TX", "INT_BT_SCO_TX"}, + {"INT4_MI2S_RX", NULL, "INT4_MI2S_RX Port Mixer"}, + {"SLIMBUS_0_RX Port Mixer", "INTERNAL_FM_TX", "INT_FM_TX"}, {"SLIMBUS_0_RX Port Mixer", "SLIM_0_TX", "SLIMBUS_0_TX"}, {"SLIMBUS_0_RX Port Mixer", "SLIM_1_TX", "SLIMBUS_1_TX"}, |