diff options
| author | Benjamin Chan <bkchan@codeaurora.org> | 2017-04-25 15:17:36 -0400 |
|---|---|---|
| committer | Benjamin Chan <bkchan@codeaurora.org> | 2017-05-26 14:10:31 -0400 |
| commit | 792e8b4003e6e405e288ccde89ef97002cc540c2 (patch) | |
| tree | e55ff83149b7de5f2f70ac90b2b66051f965a98e | |
| parent | 3d82d66409abb91539bcb9d1f343fcb9d583f2b4 (diff) | |
msm: mdss: Fix QSEED3 MDP clock calculation for cmd mode panel
When calculates the MDP clock during downscale usecase for command
mode panel, it is necessary to calcuate the entire horizontal pixel
count of the panel including the front and back porch. The incorrect MDP
clock calculation will cause screen corruption, which usually show up in
the bottom half of the screen.
CRs-Fixed: 2039110
Change-Id: Id16abb645372ef5d21472839815b6ada502dc19b
Signed-off-by: Benjamin Chan <bkchan@codeaurora.org>
| -rw-r--r-- | drivers/video/fbdev/msm/mdss_mdp_ctl.c | 20 |
1 files changed, 19 insertions, 1 deletions
diff --git a/drivers/video/fbdev/msm/mdss_mdp_ctl.c b/drivers/video/fbdev/msm/mdss_mdp_ctl.c index c062de3c1e59..3b7af9d15a39 100644 --- a/drivers/video/fbdev/msm/mdss_mdp_ctl.c +++ b/drivers/video/fbdev/msm/mdss_mdp_ctl.c @@ -571,6 +571,9 @@ static u32 __calc_qseed3_mdp_clk_rate(struct mdss_mdp_pipe *pipe, u64 ver_dwnscale; u64 active_line; u64 backfill_line; + struct mdss_mdp_ctl *ctl = pipe->mixer_left->ctl; + u64 pclk_rate; + struct mdss_panel_info *pinfo = &ctl->panel_data->panel_info; ver_dwnscale = (u64)src_h << PHASE_STEP_SHIFT; do_div(ver_dwnscale, dst.h); @@ -596,12 +599,26 @@ static u32 __calc_qseed3_mdp_clk_rate(struct mdss_mdp_pipe *pipe, total_cycle = active_line_cycle + backfill_cycle; + /* + * MDP clkrate = total_cycle * PixelClock / Dest-width + * if pixelClock not available: + * = total_cycle * fps * v_total + */ + if ((pinfo->type == MIPI_CMD_PANEL) && dst.w) { + pclk_rate = (u64)mdss_panel_get_htotal(pinfo, false) * + v_total * fps; + do_div(pclk_rate, pinfo->xres); + total_cycle *= pclk_rate; + } else { + total_cycle *= (fps * v_total); + } + pr_debug("line: active=%lld backfill=%lld vds=%lld\n", active_line, backfill_line, ver_dwnscale); pr_debug("cycle: total=%lld active=%lld backfill=%lld\n", total_cycle, active_line_cycle, backfill_cycle); - return (u32)total_cycle * (fps * v_total); + return (u32)total_cycle; } static inline bool __is_vert_downscaling(u32 src_h, @@ -659,6 +676,7 @@ static u32 get_pipe_mdp_clk_rate(struct mdss_mdp_pipe *pipe, if (flags & PERF_CALC_PIPE_APPLY_CLK_FUDGE) rate = mdss_mdp_clk_fudge_factor(mixer, rate); + rate = min(mdata->max_mdp_clk_rate, rate); return rate; } |