Merge "msm: camera: Add regulator enable and disable independent of CSID"

3 files changed, 109 insertions, 23 deletions

diff --git a/arch/arm/boot/dts/qcom/msmcobalt-camera.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-camera.dtsi
index 154bc5b092df..467b2cbfcd7d 100644
--- a/arch/arm/boot/dts/qcom/msmcobalt-camera.dtsi
+++ b/arch/arm/boot/dts/qcom/msmcobalt-camera.dtsi
@@ -28,7 +28,10 @@
 		reg-names = "csiphy";
 		interrupts = <0 78 0>;
 		interrupt-names = "csiphy";
-		clocks = <&clock_mmss clk_mmss_mnoc_maxi_clk>,
+		gdscr-supply = <&gdsc_camss_top>;
+		bimc_smmu-supply = <&gdsc_bimc_smmu>;
+		qcom,cam-vreg-name = "gdscr", "bimc_smmu";
+		clocks = <&clock_gcc clk_mmssnoc_axi_clk>,
 			<&clock_mmss clk_mmss_mnoc_ahb_clk>,
 			<&clock_mmss clk_mmss_bimc_smmu_ahb_clk>,
 			<&clock_mmss clk_mmss_bimc_smmu_axi_clk>,
@@ -42,7 +45,7 @@
 			<&clock_mmss clk_mmss_camss_ispif_ahb_clk>,
 			<&clock_mmss clk_csiphy_clk_src>,
 			<&clock_mmss clk_mmss_camss_csiphy0_clk>;
-		clock-names = "mnoc_maxi", "mnoc_ahb",
+		clock-names = "mmssnoc_axi", "mnoc_ahb",
 			"bmic_smmu_ahb", "bmic_smmu_axi",
 			"camss_ahb_clk", "camss_top_ahb_clk",
 			"csi_src_clk", "csi_clk", "cphy_csid_clk",
@@ -60,7 +63,10 @@
 		reg-names = "csiphy";
 		interrupts = <0 79 0>;
 		interrupt-names = "csiphy";
-		clocks = <&clock_mmss clk_mmss_mnoc_maxi_clk>,
+		gdscr-supply = <&gdsc_camss_top>;
+		bimc_smmu-supply = <&gdsc_bimc_smmu>;
+		qcom,cam-vreg-name = "gdscr", "bimc_smmu";
+		clocks = <&clock_gcc clk_mmssnoc_axi_clk>,
 			<&clock_mmss clk_mmss_mnoc_ahb_clk>,
 			<&clock_mmss clk_mmss_bimc_smmu_ahb_clk>,
 			<&clock_mmss clk_mmss_bimc_smmu_axi_clk>,
@@ -74,7 +80,7 @@
 			<&clock_mmss clk_mmss_camss_ispif_ahb_clk>,
 			<&clock_mmss clk_csiphy_clk_src>,
 			<&clock_mmss clk_mmss_camss_csiphy1_clk>;
-		clock-names = "mnoc_maxi", "mnoc_ahb",
+		clock-names = "mmssnoc_axi", "mnoc_ahb",
 			"bmic_smmu_ahb", "bmic_smmu_axi",
 			"camss_ahb_clk", "camss_top_ahb_clk",
 			"csi_src_clk", "csi_clk", "cphy_csid_clk",
@@ -92,7 +98,10 @@
 		reg-names = "csiphy";
 		interrupts = <0 80 0>;
 		interrupt-names = "csiphy";
-		clocks = <&clock_mmss clk_mmss_mnoc_maxi_clk>,
+		gdscr-supply = <&gdsc_camss_top>;
+		bimc_smmu-supply = <&gdsc_bimc_smmu>;
+		qcom,cam-vreg-name = "gdscr", "bimc_smmu";
+		clocks = <&clock_gcc clk_mmssnoc_axi_clk>,
 			<&clock_mmss clk_mmss_mnoc_ahb_clk>,
 			<&clock_mmss clk_mmss_bimc_smmu_ahb_clk>,
 			<&clock_mmss clk_mmss_bimc_smmu_axi_clk>,
@@ -106,7 +115,7 @@
 			<&clock_mmss clk_mmss_camss_ispif_ahb_clk>,
 			<&clock_mmss clk_csiphy_clk_src>,
 			<&clock_mmss clk_mmss_camss_csiphy2_clk>;
-		clock-names = "mnoc_maxi", "mnoc_ahb",
+		clock-names = "mmssnoc_axi", "mnoc_ahb",
 			"bmic_smmu_ahb", "bmic_smmu_axi",
 			"camss_ahb_clk", "camss_top_ahb_clk",
 			"csi_src_clk", "csi_clk", "cphy_csid_clk",
@@ -128,8 +137,9 @@
 		qcom,mipi-csi-vdd-supply = <&pmcobalt_l2>;
 		gdscr-supply = <&gdsc_camss_top>;
 		vdd_sec-supply = <&pmcobalt_l1>;
-		qcom,cam-vreg-name = "vdd_sec", "gdscr";
-		clocks = <&clock_mmss clk_mmss_mnoc_maxi_clk>,
+		bimc_smmu-supply = <&gdsc_bimc_smmu>;
+		qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu";
+		clocks = <&clock_gcc clk_mmssnoc_axi_clk>,
 			<&clock_mmss clk_mmss_mnoc_ahb_clk>,
 			<&clock_mmss clk_mmss_bimc_smmu_ahb_clk>,
 			<&clock_mmss clk_mmss_bimc_smmu_axi_clk>,
@@ -144,7 +154,7 @@
 			<&clock_mmss clk_mmss_camss_csi0pix_clk>,
 			<&clock_mmss clk_mmss_camss_cphy_csid0_clk>,
 			<&clock_mmss clk_csiphy_clk_src>;
-		clock-names = "mnoc_maxi", "mnoc_ahb",
+		clock-names = "mmssnoc_axi", "mnoc_ahb",
 			"bmic_smmu_ahb", "bmic_smmu_axi",
 			"camss_ahb_clk", "camss_top_ahb_clk",
 			"ispif_ahb_clk", "csi_src_clk", "csi_clk",
@@ -166,8 +176,9 @@
 		qcom,mipi-csi-vdd-supply = <&pmcobalt_l2>;
 		gdscr-supply = <&gdsc_camss_top>;
 		vdd_sec-supply = <&pmcobalt_l1>;
-		qcom,cam-vreg-name = "vdd_sec", "gdscr";
-		clocks = <&clock_mmss clk_mmss_mnoc_maxi_clk>,
+		bimc_smmu-supply = <&gdsc_bimc_smmu>;
+		qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu";
+		clocks = <&clock_gcc clk_mmssnoc_axi_clk>,
 			<&clock_mmss clk_mmss_mnoc_ahb_clk>,
 			<&clock_mmss clk_mmss_bimc_smmu_ahb_clk>,
 			<&clock_mmss clk_mmss_bimc_smmu_axi_clk>,
@@ -182,7 +193,7 @@
 			<&clock_mmss clk_mmss_camss_csi1pix_clk>,
 			<&clock_mmss clk_mmss_camss_cphy_csid1_clk>,
 			<&clock_mmss clk_csiphy_clk_src>;
-		clock-names = "mnoc_maxi", "mnoc_ahb",
+		clock-names = "mmssnoc_axi", "mnoc_ahb",
 			"bmic_smmu_ahb", "bmic_smmu_axi",
 			"camss_ahb_clk", "camss_top_ahb_clk",
 			"ispif_ahb_clk", "csi_src_clk", "csi_clk",
@@ -204,8 +215,9 @@
 		qcom,mipi-csi-vdd-supply = <&pmcobalt_l2>;
 		gdscr-supply = <&gdsc_camss_top>;
 		vdd_sec-supply = <&pmcobalt_l1>;
-		qcom,cam-vreg-name = "vdd_sec", "gdscr";
-		clocks = <&clock_mmss clk_mmss_mnoc_maxi_clk>,
+		bimc_smmu-supply = <&gdsc_bimc_smmu>;
+		qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu";
+		clocks = <&clock_gcc clk_mmssnoc_axi_clk>,
 			<&clock_mmss clk_mmss_mnoc_ahb_clk>,
 			<&clock_mmss clk_mmss_bimc_smmu_ahb_clk>,
 			<&clock_mmss clk_mmss_bimc_smmu_axi_clk>,
@@ -220,7 +232,7 @@
 			<&clock_mmss clk_mmss_camss_csi2pix_clk>,
 			<&clock_mmss clk_mmss_camss_cphy_csid2_clk>,
 			<&clock_mmss clk_csiphy_clk_src>;
-		clock-names = "mnoc_maxi", "mnoc_ahb",
+		clock-names = "mmssnoc_axi", "mnoc_ahb",
 			"bmic_smmu_ahb", "bmic_smmu_axi",
 			"camss_ahb_clk", "camss_top_ahb_clk",
 			"ispif_ahb_clk", "csi_src_clk", "csi_clk",
@@ -242,8 +254,9 @@
 		qcom,mipi-csi-vdd-supply = <&pmcobalt_l2>;
 		gdscr-supply = <&gdsc_camss_top>;
 		vdd_sec-supply = <&pmcobalt_l1>;
-		qcom,cam-vreg-name = "vdd_sec", "gdscr";
-		clocks = <&clock_mmss clk_mmss_mnoc_maxi_clk>,
+		bimc_smmu-supply = <&gdsc_bimc_smmu>;
+		qcom,cam-vreg-name = "vdd_sec", "gdscr", "bimc_smmu";
+		clocks = <&clock_gcc clk_mmssnoc_axi_clk>,
 			<&clock_mmss clk_mmss_mnoc_ahb_clk>,
 			<&clock_mmss clk_mmss_bimc_smmu_ahb_clk>,
 			<&clock_mmss clk_mmss_bimc_smmu_axi_clk>,
@@ -257,7 +270,7 @@
 			<&clock_mmss clk_mmss_camss_csi3pix_clk>,
 			<&clock_mmss clk_mmss_camss_cphy_csid1_clk>,
 			<&clock_mmss clk_csiphy_clk_src>;
-		clock-names = "mnoc_maxi", "mnoc_ahb",
+		clock-names = "mmssnoc_axi", "mnoc_ahb",
 			"bmic_smmu_ahb", "bmic_smmu_axi",
 			"camss_ahb_clk", "camss_top_ahb_clk",
 			"ispif_ahb_clk", "csi_src_clk", "csi_clk",
@@ -687,7 +700,7 @@
 		mmagic-supply = <&gdsc_bimc_smmu>;
 		gdscr-supply = <&gdsc_camss_top>;
 		qcom,cam-vreg-name = "mmagic", "gdscr";
-		clocks = <&clock_mmss clk_mmss_mnoc_maxi_clk>,
+		clocks = <&clock_gcc clk_mmssnoc_axi_clk>,
 			<&clock_mmss clk_mmss_mnoc_ahb_clk>,
 			<&clock_mmss clk_mmss_bimc_smmu_ahb_clk>,
 			<&clock_mmss clk_mmss_bimc_smmu_axi_clk>,
@@ -696,7 +709,7 @@
 			<&clock_mmss clk_cci_clk_src>,
 			<&clock_mmss clk_mmss_camss_cci_ahb_clk>,
 			<&clock_mmss clk_mmss_camss_cci_clk>;
-		clock-names = "mnoc_axi", "mnoc_ahb", "smmu_ahb", "smmu_axi",
+		clock-names = "mmssnoc_axi", "mnoc_ahb", "smmu_ahb", "smmu_axi",
 			"camss_ahb_clk", "camss_top_ahb_clk",
 			"cci_src_clk", "cci_ahb_clk", "camss_cci_clk";
 		qcom,clock-rates = <0 0 0 0 0 0 19200000 0 0>,
diff --git a/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.c b/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.c
index 6a1b385c3d8b..e4cee1fa4ffc 100644
--- a/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.c
+++ b/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.c
@@ -1052,6 +1052,25 @@ static int msm_csiphy_init(struct csiphy_device *csiphy_dev)
 
 	CDBG("%s:%d called\n", __func__, __LINE__);
 
+	rc = msm_camera_config_vreg(&csiphy_dev->pdev->dev,
+		csiphy_dev->csiphy_vreg,
+		csiphy_dev->regulator_count, NULL, 0,
+		&csiphy_dev->csiphy_reg_ptr[0], 1);
+	if (rc < 0) {
+		pr_err("%s:%d csiphy config_vreg failed\n",
+			__func__, __LINE__);
+		goto csiphy_resource_fail;
+	}
+	rc = msm_camera_enable_vreg(&csiphy_dev->pdev->dev,
+		csiphy_dev->csiphy_vreg,
+		csiphy_dev->regulator_count, NULL, 0,
+		&csiphy_dev->csiphy_reg_ptr[0], 1);
+	if (rc < 0) {
+		pr_err("%s:%d csiphy enable_vreg failed\n",
+			__func__, __LINE__);
+		goto top_vreg_enable_failed;
+	}
+
 	rc = msm_camera_clk_enable(&csiphy_dev->pdev->dev,
 		csiphy_dev->csiphy_clk_info, csiphy_dev->csiphy_clk,
 		csiphy_dev->num_clk, true);
@@ -1088,6 +1107,11 @@ static int msm_csiphy_init(struct csiphy_device *csiphy_dev)
 	csiphy_dev->csiphy_state = CSIPHY_POWER_UP;
 	return 0;
 
+top_vreg_enable_failed:
+	msm_camera_config_vreg(&csiphy_dev->pdev->dev,
+		csiphy_dev->csiphy_vreg,
+		csiphy_dev->regulator_count, NULL, 0,
+		&csiphy_dev->csiphy_reg_ptr[0], 0);
 csiphy_resource_fail:
 	if (cam_config_ahb_clk(NULL, 0, CAM_AHB_CLIENT_CSIPHY,
 		CAM_AHB_SUSPEND_VOTE) < 0)
@@ -1128,6 +1152,24 @@ static int msm_csiphy_init(struct csiphy_device *csiphy_dev)
 		pr_err("%s: failed to vote for AHB\n", __func__);
 		return rc;
 	}
+	rc = msm_camera_config_vreg(&csiphy_dev->pdev->dev,
+		csiphy_dev->csiphy_vreg,
+		csiphy_dev->regulator_count, NULL, 0,
+		&csiphy_dev->csiphy_reg_ptr[0], 1);
+	if (rc < 0) {
+		pr_err("%s:%d csiphy config_vreg failed\n",
+			__func__, __LINE__);
+		goto csiphy_resource_fail;
+	}
+	rc = msm_camera_enable_vreg(&csiphy_dev->pdev->dev,
+		csiphy_dev->csiphy_vreg,
+		csiphy_dev->regulator_count, NULL, 0,
+		&csiphy_dev->csiphy_reg_ptr[0], 1);
+	if (rc < 0) {
+		pr_err("%s:%d csiphy enable_vreg failed\n",
+			__func__, __LINE__);
+		goto top_vreg_enable_failed;
+	}
 
 	rc = msm_camera_clk_enable(&csiphy_dev->pdev->dev,
 		csiphy_dev->csiphy_clk_info, csiphy_dev->csiphy_clk,
@@ -1139,7 +1181,7 @@ static int msm_csiphy_init(struct csiphy_device *csiphy_dev)
 		csiphy_dev->ref_count--;
 		goto csiphy_resource_fail;
 	}
-	CDBG("%s:%d called\n", __func__, __LINE__);
+	CDBG("%s:%d clk enable success\n", __func__, __LINE__);
 
 	if (csiphy_dev->csiphy_3phase == CSI_3PHASE_HW)
 		msm_csiphy_3ph_reset(csiphy_dev);
@@ -1161,7 +1203,11 @@ static int msm_csiphy_init(struct csiphy_device *csiphy_dev)
 		csiphy_dev->hw_version);
 	csiphy_dev->csiphy_state = CSIPHY_POWER_UP;
 	return 0;
-
+top_vreg_enable_failed:
+	msm_camera_config_vreg(&csiphy_dev->pdev->dev,
+		csiphy_dev->csiphy_vreg,
+		csiphy_dev->regulator_count, NULL, 0,
+		&csiphy_dev->csiphy_reg_ptr[0], 0);
 csiphy_resource_fail:
 	if (cam_config_ahb_clk(NULL, 0, CAM_AHB_CLIENT_CSIPHY,
 		CAM_AHB_SUSPEND_VOTE) < 0)
@@ -1275,6 +1321,14 @@ static int msm_csiphy_release(struct csiphy_device *csiphy_dev, void *arg)
 			csiphy_dev->csiphy_3p_clk, 2, false);
 	}
 
+	msm_camera_enable_vreg(&csiphy_dev->pdev->dev,
+		csiphy_dev->csiphy_vreg,
+		csiphy_dev->regulator_count, NULL, 0,
+		&csiphy_dev->csiphy_reg_ptr[0], 0);
+	msm_camera_config_vreg(&csiphy_dev->pdev->dev,
+		csiphy_dev->csiphy_vreg, csiphy_dev->regulator_count,
+		NULL, 0, &csiphy_dev->csiphy_reg_ptr[0], 0);
+
 	csiphy_dev->csiphy_state = CSIPHY_POWER_DOWN;
 
 	if (cam_config_ahb_clk(NULL, 0, CAM_AHB_CLIENT_CSIPHY,
@@ -1386,6 +1440,13 @@ static int msm_csiphy_release(struct csiphy_device *csiphy_dev, void *arg)
 			csiphy_dev->csiphy_3p_clk, 2, false);
 	}
 
+	msm_camera_enable_vreg(&csiphy_dev->pdev->dev,
+		csiphy_dev->csiphy_vreg, csiphy_dev->regulator_count,
+		NULL, 0, &csiphy_dev->csiphy_reg_ptr[0], 0);
+	msm_camera_config_vreg(&csiphy_dev->pdev->dev,
+		csiphy_dev->csiphy_vreg, csiphy_dev->regulator_count,
+		NULL, 0, &csiphy_dev->csiphy_reg_ptr[0], 0);
+
 	csiphy_dev->csiphy_state = CSIPHY_POWER_DOWN;
 
 	if (cam_config_ahb_clk(NULL, 0, CAM_AHB_CLIENT_CSIPHY,
@@ -1711,6 +1772,14 @@ static int csiphy_probe(struct platform_device *pdev)
 		goto csiphy_no_resource;
 	}
 
+	rc = msm_camera_get_dt_vreg_data(pdev->dev.of_node,
+		&(new_csiphy_dev->csiphy_vreg),
+		&(new_csiphy_dev->regulator_count));
+	if (rc < 0) {
+		pr_err("%s: get vreg data from dtsi fail\n", __func__);
+		rc = -EFAULT;
+		goto csiphy_no_resource;
+	}
 	/* ToDo: Enable 3phase clock for dynamic clock enable/disable */
 	rc = msm_csiphy_get_clk_info(new_csiphy_dev, pdev);
 	if (rc < 0) {
@@ -1781,7 +1850,7 @@ static int msm_csiphy_exit(struct platform_device *pdev)
 		&csiphy_dev->csiphy_all_clk,
 		csiphy_dev->num_all_clk);
 
-	msm_camera_put_reg_base(pdev, csiphy_dev->base, "csid", true);
+	msm_camera_put_reg_base(pdev, csiphy_dev->base, "csiphy", true);
 	if (csiphy_dev->hw_dts_version >= CSIPHY_VERSION_V30) {
 		msm_camera_put_reg_base(pdev, csiphy_dev->clk_mux_base,
 			"csiphy_clk_mux", true);
diff --git a/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.h b/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.h
index aba88da1157e..70462dcd3b12 100644
--- a/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.h
+++ b/drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.h
@@ -20,6 +20,7 @@
 #include <media/msm_cam_sensor.h>
 #include "msm_sd.h"
 #include "msm_camera_io_util.h"
+#include "msm_camera_dt_util.h"
 #include "cam_soc_api.h"
 
 #define MAX_CSIPHY 3
@@ -183,6 +184,9 @@ struct csiphy_device {
 	uint8_t num_irq_registers;
 	uint32_t csiphy_sof_debug;
 	uint32_t csiphy_sof_debug_count;
+	struct camera_vreg_t *csiphy_vreg;
+	struct regulator *csiphy_reg_ptr[MAX_REGULATOR];
+	int32_t regulator_count;
 };
 
 #define VIDIOC_MSM_CSIPHY_RELEASE \