diff options
| author | Ram Chandrasekar <rkumbako@codeaurora.org> | 2016-05-17 15:26:33 -0600 |
|---|---|---|
| committer | Kyle Yan <kyan@codeaurora.org> | 2016-06-07 11:56:22 -0700 |
| commit | 77fd5db7ee660916f6909a6e004e70e61a4bf5fe (patch) | |
| tree | 199b08d1fcfd9717717b26e588a428b5e95a0bb5 | |
| parent | 1884f6ccf95e6403ce9fb9f4c8d5e3b1be58bda8 (diff) | |
ARM: dts: msm: Add LMH DCVSh interrupt information for msmcobalt
Add information about the interrupt generated by the LMH DCVSh block for
msmcobalt.
This interrupt will be generated whenever the hardware makes a new
decision about the mitigation frequency.
Change-Id: I408fb7e62ef13b21dfea68bb6b878cdbeee411cd
Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
| -rw-r--r-- | arch/arm/boot/dts/qcom/msmcobalt.dtsi | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom/msmcobalt.dtsi b/arch/arm/boot/dts/qcom/msmcobalt.dtsi index 171a95afe5c6..b666f535a664 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt.dtsi @@ -2698,10 +2698,12 @@ &clock_cpu { lmh_dcvs0: qcom,limits-dcvs@0 { compatible = "qcom,msm-hw-limits"; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; }; lmh_dcvs1: qcom,limits-dcvs@1 { compatible = "qcom,msm-hw-limits"; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; }; }; |