diff options
| author | Vikram Mulukutla <markivx@codeaurora.org> | 2016-01-11 11:56:27 -0800 |
|---|---|---|
| committer | Gerrit - the friendly Code Review server <code-review@localhost> | 2017-03-21 03:01:51 -0700 |
| commit | 767c721b7c77b76ca4e49129dabeabd332bbdda7 (patch) | |
| tree | 5df78c2deea0a04fb7bb0cdc03600a379760a0fd | |
| parent | 936388f5f57d0f3c420db08140fa087d49da440c (diff) | |
clk: msm: clock-cpu-8996: Allow interrupts during alt_pll set_rate
The CPU that is disabling the alternate PLL may also need to
handle CPR interrupts. Allow the CPU to handle interrupts
during the set_rate operation.
CRs-Fixed: 960701
Change-Id: I63d7ce3e3dd2b559c4db383b64faa9335c404576
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
| -rw-r--r-- | drivers/clk/msm/clock-cpu-8996.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/msm/clock-cpu-8996.c b/drivers/clk/msm/clock-cpu-8996.c index 7e03a599fccc..bcda6f31d6f5 100644 --- a/drivers/clk/msm/clock-cpu-8996.c +++ b/drivers/clk/msm/clock-cpu-8996.c @@ -238,6 +238,7 @@ static struct alpha_pll_clk perfcl_alt_pll = { .post_div_config = 0x100, /* Div-2 */ .config_ctl_val = 0x4001051B, .offline_bit_workaround = true, + .no_irq_dis = true, .c = { .always_on = true, .parent = &alpha_xo_ao.c, @@ -300,6 +301,7 @@ static struct alpha_pll_clk pwrcl_alt_pll = { .post_div_config = 0x100, /* Div-2 */ .config_ctl_val = 0x4001051B, .offline_bit_workaround = true, + .no_irq_dis = true, .c = { .always_on = true, .dbg_name = "pwrcl_alt_pll", |