scsi: ufs: minimize exposure of ufs header files

Until now, the phy-qcom-ufs-*.* files used ufs data structures and
macros and thus, we had to expose most of them in include/linux/scsi/ufs
path. But now, after removing support for phy 28nm in apq8084 under
kernel 3.14, we can minimize the exposure of code to essential minimum.
To do that, we relocate the ufs.h, unipro.h, ufshcd.h and ufs-qcom.h
files back to reside internally in the driver.

Also this patch contains some very minor changes suggested by the
upstream checkpatch script.

Change-Id: Id2a923a6a0b1c76565c25f2797a666f3a0d1315f
Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org>
[subhashj@codeaurora.org: resolved merge conflicts]
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
[venkatg@codeaurora.org: fixed header includes and other
trivial merge conflicts]
Signed-off-by: Venkat Gopalakrishnan <venkatg@codeaurora.org>

18 files changed, 101 insertions, 117 deletions

diff --git a/drivers/scsi/ufs/ufs-debugfs.c b/drivers/scsi/ufs/ufs-debugfs.c
index 1567797d8796..d719f7b5fcae 100644
--- a/drivers/scsi/ufs/ufs-debugfs.c
+++ b/drivers/scsi/ufs/ufs-debugfs.c
@@ -19,7 +19,7 @@
 
 #include <linux/random.h>
 #include "ufs-debugfs.h"
-#include <linux/scsi/ufs/unipro.h>
+#include "unipro.h"
 #include "ufshci.h"
 
 enum field_width {
diff --git a/drivers/scsi/ufs/ufs-debugfs.h b/drivers/scsi/ufs/ufs-debugfs.h
index cf82be23fb47..f576571ee4db 100644
--- a/drivers/scsi/ufs/ufs-debugfs.h
+++ b/drivers/scsi/ufs/ufs-debugfs.h
@@ -21,7 +21,7 @@
 #define _UFS_DEBUGFS_H
 
 #include <linux/debugfs.h>
-#include <linux/scsi/ufs/ufshcd.h>
+#include "ufshcd.h"
 
 #ifdef CONFIG_DEBUG_FS
 void ufsdbg_add_debugfs(struct ufs_hba *hba);
diff --git a/drivers/scsi/ufs/ufs-qcom-debugfs.c b/drivers/scsi/ufs/ufs-qcom-debugfs.c
index f2ae82532da6..0368f9805b8c 100644
--- a/drivers/scsi/ufs/ufs-qcom-debugfs.c
+++ b/drivers/scsi/ufs/ufs-qcom-debugfs.c
@@ -13,7 +13,7 @@
  */
 
 #include <linux/debugfs.h>
-#include <linux/scsi/ufs/ufs-qcom.h>
+#include "ufs-qcom.h"
 #include "ufs-qcom-debugfs.h"
 #include "ufs-debugfs.h"
 
diff --git a/drivers/scsi/ufs/ufs-qcom-debugfs.h b/drivers/scsi/ufs/ufs-qcom-debugfs.h
index 03341711e11e..b693bfa84a71 100644
--- a/drivers/scsi/ufs/ufs-qcom-debugfs.h
+++ b/drivers/scsi/ufs/ufs-qcom-debugfs.h
@@ -15,7 +15,7 @@
 #ifndef QCOM_DEBUGFS_H_
 #define QCOM_DEBUGFS_H_
 
-#include <linux/scsi/ufs/ufshcd.h>
+#include "ufshcd.h"
 
 #ifdef CONFIG_DEBUG_FS
 void ufs_qcom_dbg_add_debugfs(struct ufs_hba *hba, struct dentry *root);
diff --git a/drivers/scsi/ufs/ufs-qcom-ice.c b/drivers/scsi/ufs/ufs-qcom-ice.c
index 2fe52b9e98b7..84a6cff5f97a 100644
--- a/drivers/scsi/ufs/ufs-qcom-ice.c
+++ b/drivers/scsi/ufs/ufs-qcom-ice.c
@@ -15,11 +15,11 @@
 #include <linux/of.h>
 #include <linux/async.h>
 #include <linux/blkdev.h>
-#include <linux/scsi/ufs/ufshcd.h>
 #include <crypto/ice.h>
 
 #include "ufs-qcom-ice.h"
 #include "ufs-qcom-debugfs.h"
+#include "ufshcd.h"
 
 #define UFS_QCOM_CRYPTO_LABEL "ufs-qcom-crypto"
 /* Timeout waiting for ICE initialization, that requires TZ access */
diff --git a/drivers/scsi/ufs/ufs-qcom-ice.h b/drivers/scsi/ufs/ufs-qcom-ice.h
index ae78a5120426..adadbe0b218b 100644
--- a/drivers/scsi/ufs/ufs-qcom-ice.h
+++ b/drivers/scsi/ufs/ufs-qcom-ice.h
@@ -17,7 +17,7 @@
 
 #include <scsi/scsi_cmnd.h>
 
-#include <linux/scsi/ufs/ufs-qcom.h>
+#include "ufs-qcom.h"
 
 /*
  * UFS host controller ICE registers. There are n [0..31]
diff --git a/drivers/scsi/ufs/ufs-qcom.c b/drivers/scsi/ufs/ufs-qcom.c
index 7e6a22930e5e..970e0cfa4e21 100644
--- a/drivers/scsi/ufs/ufs-qcom.c
+++ b/drivers/scsi/ufs/ufs-qcom.c
@@ -12,23 +12,15 @@
  *
  */
 
-#include <linux/io.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
 #include <linux/time.h>
-#include <linux/clk.h>
 #include <linux/of.h>
 #include <linux/iopoll.h>
 #include <linux/platform_device.h>
-
 #include <linux/msm-bus.h>
 #include <soc/qcom/scm.h>
 #include <linux/phy/phy.h>
-
-#include <linux/scsi/ufs/ufshcd.h>
-#include <linux/scsi/ufs/unipro.h>
-#include <linux/scsi/ufs/ufs-qcom.h>
 #include <linux/phy/phy-qcom-ufs.h>
+
 #include "ufshcd.h"
 #include "ufshcd-pltfrm.h"
 #include "unipro.h"
diff --git a/drivers/scsi/ufs/ufs-qcom.h b/drivers/scsi/ufs/ufs-qcom.h
index 36249b35f858..e734574c150a 100644
--- a/drivers/scsi/ufs/ufs-qcom.h
+++ b/drivers/scsi/ufs/ufs-qcom.h
@@ -14,6 +14,9 @@
 #ifndef UFS_QCOM_H_
 #define UFS_QCOM_H_
 
+#include <linux/phy/phy.h>
+#include "ufshcd.h"
+
 #define MAX_UFS_QCOM_HOSTS	1
 #define MAX_U32                 (~(u32)0)
 #define MPHY_TX_FSM_STATE       0x41
@@ -64,15 +67,6 @@ enum {
 	UFS_TEST_BUS_CTRL_2			= 0xF4,
 	UFS_UNIPRO_CFG				= 0xF8,
 
-	/*
-	 * QCOM UFS host controller vendor specific registers
-	 * added in HW Version 3.0.0
-	 */
-	UFS_AH8_CFG				= 0xFC,
-};
-
-/* QCOM UFS host controller vendor specific debug registers */
-enum {
 	UFS_DBG_RD_REG_UAWM			= 0x100,
 	UFS_DBG_RD_REG_UARM			= 0x200,
 	UFS_DBG_RD_REG_TXUC			= 0x300,
@@ -88,9 +82,6 @@ enum {
 	UFS_UFS_DBG_RD_EDTL_RAM			= 0x1900,
 };
 
-#define UFS_CNTLR_2_x_x_VEN_REGS_OFFSET(x)	(0x000 + x)
-#define UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(x)	(0x400 + x)
-
 /* bit definitions for REG_UFS_CFG1 register */
 #define QUNIPRO_SEL	UFS_BIT(0)
 #define TEST_BUS_EN		BIT(18)
@@ -192,6 +183,33 @@ struct ufs_qcom_bus_vote {
 	struct device_attribute max_bus_bw;
 };
 
+/**
+ * struct ufs_qcom_ice_data - ICE related information
+ * @vops:	pointer to variant operations of ICE
+ * @async_done:	completion for supporting ICE's driver asynchronous nature
+ * @pdev:	pointer to the proper ICE platform device
+ * @state:      UFS-ICE interface's internal state (see
+ *       ufs-qcom-ice.h for possible internal states)
+ * @quirks:     UFS-ICE interface related quirks
+ * @crypto_engine_err: crypto engine errors
+ */
+struct ufs_qcom_ice_data {
+	struct qcom_ice_variant_ops *vops;
+	struct completion async_done;
+	struct platform_device *pdev;
+	int state;
+
+	/*
+	 * If UFS host controller should handle cryptographic engine's
+	 * errors, enables this quirk.
+	 */
+	#define UFS_QCOM_ICE_QUIRK_HANDLE_CRYPTO_ENGINE_ERRORS	UFS_BIT(0)
+
+	u16 quirks;
+
+	bool crypto_engine_err;
+};
+
 /* Host controller hardware version: major.minor.step */
 struct ufs_hw_version {
 	u16 step;
@@ -199,6 +217,18 @@ struct ufs_hw_version {
 	u8 major;
 };
 
+#ifdef CONFIG_DEBUG_FS
+struct qcom_debugfs_files {
+	struct dentry *debugfs_root;
+	struct dentry *dbg_print_en;
+	struct dentry *testbus;
+	struct dentry *testbus_en;
+	struct dentry *testbus_cfg;
+	struct dentry *testbus_bus;
+	struct dentry *dbg_regs;
+};
+#endif
+
 struct ufs_qcom_testbus {
 	u8 select_major;
 	u8 select_minor;
@@ -212,12 +242,6 @@ struct ufs_qcom_host {
 	 * controller supports the QUniPro mode.
 	 */
 	#define UFS_QCOM_CAP_QUNIPRO	UFS_BIT(0)
-
-	/*
-	 * Set this capability if host controller can retain the secure
-	 * configuration even after UFS controller core power collapse.
-	 */
-	#define UFS_QCOM_CAP_RETAIN_SEC_CFG_AFTER_PWR_COLLAPSE	UFS_BIT(1)
 	u32 caps;
 
 	struct phy *generic_phy;
@@ -229,13 +253,15 @@ struct ufs_qcom_host {
 	struct clk *rx_l1_sync_clk;
 	struct clk *tx_l1_sync_clk;
 	bool is_lane_clks_enabled;
-
+	bool sec_cfg_updated;
+	struct ufs_qcom_ice_data ice;
 	void __iomem *dev_ref_clk_ctrl_mmio;
 	bool is_dev_ref_clk_enabled;
 	struct ufs_hw_version hw_ver;
-
 	u32 dev_ref_clk_en_mask;
-
+#ifdef CONFIG_DEBUG_FS
+	struct qcom_debugfs_files debugfs_files;
+#endif
 	/* Bitmask for enabling debug prints */
 	u32 dbg_print_en;
 	struct ufs_qcom_testbus testbus;
@@ -246,6 +272,9 @@ struct ufs_qcom_host {
 #define ufs_qcom_is_link_hibern8(hba) ufshcd_is_link_hibern8(hba)
 
 int ufs_qcom_testbus_config(struct ufs_qcom_host *host);
+void ufs_qcom_print_hw_debug_reg_all(struct ufs_hba *hba, void *priv,
+		void (*print_fn)(struct ufs_hba *hba, int offset, int num_regs,
+				char *str, void *priv));
 
 static inline bool ufs_qcom_cap_qunipro(struct ufs_qcom_host *host)
 {
diff --git a/include/linux/scsi/ufs/ufs-qcom.h b/drivers/scsi/ufs/ufs-qcom.h~HEAD
index c38ae5ed4965..36249b35f858 100644
--- a/include/linux/scsi/ufs/ufs-qcom.h
+++ b/drivers/scsi/ufs/ufs-qcom.h~HEAD
@@ -14,9 +14,6 @@
 #ifndef UFS_QCOM_H_
 #define UFS_QCOM_H_
 
-#include <linux/phy/phy.h>
-#include <linux/scsi/ufs/ufshcd.h>
-
 #define MAX_UFS_QCOM_HOSTS	1
 #define MAX_U32                 (~(u32)0)
 #define MPHY_TX_FSM_STATE       0x41
@@ -46,7 +43,7 @@
 #define UFS_QCOM_LIMIT_TX_PWR_PWM	SLOW_MODE
 #define UFS_QCOM_LIMIT_RX_PWR_HS	FAST_MODE
 #define UFS_QCOM_LIMIT_TX_PWR_HS	FAST_MODE
-#define UFS_QCOM_LIMIT_HS_RATE		PA_HS_MODE_A
+#define UFS_QCOM_LIMIT_HS_RATE		PA_HS_MODE_B
 #define UFS_QCOM_LIMIT_DESIRED_MODE	FAST
 
 /* QCOM UFS host controller vendor specific registers */
@@ -67,6 +64,15 @@ enum {
 	UFS_TEST_BUS_CTRL_2			= 0xF4,
 	UFS_UNIPRO_CFG				= 0xF8,
 
+	/*
+	 * QCOM UFS host controller vendor specific registers
+	 * added in HW Version 3.0.0
+	 */
+	UFS_AH8_CFG				= 0xFC,
+};
+
+/* QCOM UFS host controller vendor specific debug registers */
+enum {
 	UFS_DBG_RD_REG_UAWM			= 0x100,
 	UFS_DBG_RD_REG_UARM			= 0x200,
 	UFS_DBG_RD_REG_TXUC			= 0x300,
@@ -82,6 +88,9 @@ enum {
 	UFS_UFS_DBG_RD_EDTL_RAM			= 0x1900,
 };
 
+#define UFS_CNTLR_2_x_x_VEN_REGS_OFFSET(x)	(0x000 + x)
+#define UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(x)	(0x400 + x)
+
 /* bit definitions for REG_UFS_CFG1 register */
 #define QUNIPRO_SEL	UFS_BIT(0)
 #define TEST_BUS_EN		BIT(18)
@@ -123,15 +132,6 @@ enum ufs_qcom_phy_init_type {
 	UFS_PHY_INIT_CFG_RESTORE,
 };
 
-struct ufs_qcom_phy_vreg {
-	const char *name;
-	struct regulator *reg;
-	int max_uA;
-	int min_uV;
-	int max_uV;
-	bool enabled;
-};
-
 /* QCOM UFS debug print bit mask */
 #define UFS_QCOM_DBG_PRINT_REGS_EN	BIT(0)
 #define UFS_QCOM_DBG_PRINT_ICE_REGS_EN	BIT(1)
@@ -162,6 +162,11 @@ static inline void ufs_qcom_assert_reset(struct ufs_hba *hba)
 {
 	ufshcd_rmwl(hba, MASK_UFS_PHY_SOFT_RESET,
 			1 << OFFSET_UFS_PHY_SOFT_RESET, REG_UFS_CFG1);
+
+	/*
+	 * Make sure assertion of ufs phy reset is written to
+	 * register before returning
+	 */
 	mb();
 }
 
@@ -169,6 +174,11 @@ static inline void ufs_qcom_deassert_reset(struct ufs_hba *hba)
 {
 	ufshcd_rmwl(hba, MASK_UFS_PHY_SOFT_RESET,
 			0 << OFFSET_UFS_PHY_SOFT_RESET, REG_UFS_CFG1);
+
+	/*
+	 * Make sure de-assertion of ufs phy reset is written to
+	 * register before returning
+	 */
 	mb();
 }
 
@@ -182,33 +192,6 @@ struct ufs_qcom_bus_vote {
 	struct device_attribute max_bus_bw;
 };
 
-/**
- * struct ufs_qcom_ice_data - ICE related information
- * @vops:	pointer to variant operations of ICE
- * @async_done:	completion for supporting ICE's driver asynchronous nature
- * @pdev:	pointer to the proper ICE platform device
- * @state:      UFS-ICE interface's internal state (see
- *       ufs-qcom-ice.h for possible internal states)
- * @quirks:     UFS-ICE interface related quirks
- * @crypto_engine_err: crypto engine errors
- */
-struct ufs_qcom_ice_data {
-	struct qcom_ice_variant_ops *vops;
-	struct completion async_done;
-	struct platform_device *pdev;
-	int state;
-
-	/*
-	 * If UFS host controller should handle cryptographic engine's
-	 * errors, enables this quirk.
-	 */
-	#define UFS_QCOM_ICE_QUIRK_HANDLE_CRYPTO_ENGINE_ERRORS	UFS_BIT(0)
-
-	u16 quirks;
-
-	bool crypto_engine_err;
-};
-
 /* Host controller hardware version: major.minor.step */
 struct ufs_hw_version {
 	u16 step;
@@ -216,18 +199,6 @@ struct ufs_hw_version {
 	u8 major;
 };
 
-#ifdef CONFIG_DEBUG_FS
-struct qcom_debugfs_files {
-	struct dentry *debugfs_root;
-	struct dentry *dbg_print_en;
-	struct dentry *testbus;
-	struct dentry *testbus_en;
-	struct dentry *testbus_cfg;
-	struct dentry *testbus_bus;
-	struct dentry *dbg_regs;
-};
-#endif
-
 struct ufs_qcom_testbus {
 	u8 select_major;
 	u8 select_minor;
@@ -241,6 +212,12 @@ struct ufs_qcom_host {
 	 * controller supports the QUniPro mode.
 	 */
 	#define UFS_QCOM_CAP_QUNIPRO	UFS_BIT(0)
+
+	/*
+	 * Set this capability if host controller can retain the secure
+	 * configuration even after UFS controller core power collapse.
+	 */
+	#define UFS_QCOM_CAP_RETAIN_SEC_CFG_AFTER_PWR_COLLAPSE	UFS_BIT(1)
 	u32 caps;
 
 	struct phy *generic_phy;
@@ -252,15 +229,13 @@ struct ufs_qcom_host {
 	struct clk *rx_l1_sync_clk;
 	struct clk *tx_l1_sync_clk;
 	bool is_lane_clks_enabled;
-	bool sec_cfg_updated;
-	struct ufs_qcom_ice_data ice;
+
 	void __iomem *dev_ref_clk_ctrl_mmio;
 	bool is_dev_ref_clk_enabled;
 	struct ufs_hw_version hw_ver;
+
 	u32 dev_ref_clk_en_mask;
-#ifdef CONFIG_DEBUG_FS
-	struct qcom_debugfs_files debugfs_files;
-#endif
+
 	/* Bitmask for enabling debug prints */
 	u32 dbg_print_en;
 	struct ufs_qcom_testbus testbus;
@@ -271,15 +246,6 @@ struct ufs_qcom_host {
 #define ufs_qcom_is_link_hibern8(hba) ufshcd_is_link_hibern8(hba)
 
 int ufs_qcom_testbus_config(struct ufs_qcom_host *host);
-void ufs_qcom_print_hw_debug_reg_all(struct ufs_hba *hba, void *priv,
-		void (*print_fn)(struct ufs_hba *hba, int offset, int num_regs,
-				char *str, void *priv));
-
-#define MAX_PROP_NAME              32
-#define VDDA_PHY_MIN_UV            1000000
-#define VDDA_PHY_MAX_UV            1000000
-#define VDDA_PLL_MIN_UV            1800000
-#define VDDA_PLL_MAX_UV            1800000
 
 static inline bool ufs_qcom_cap_qunipro(struct ufs_qcom_host *host)
 {
diff --git a/include/linux/scsi/ufs/ufs.h b/drivers/scsi/ufs/ufs.h
index 58f3cb06a749..e4b2c95350ef 100644
--- a/include/linux/scsi/ufs/ufs.h
+++ b/drivers/scsi/ufs/ufs.h
@@ -81,7 +81,7 @@ enum {
  */
 static inline bool ufs_is_valid_unit_desc_lun(u8 lun)
 {
-	return (lun == UFS_UPIU_RPMB_WLUN || (lun < UFS_UPIU_MAX_GENERAL_LUN));
+	return lun == UFS_UPIU_RPMB_WLUN || (lun < UFS_UPIU_MAX_GENERAL_LUN);
 }
 
 /*
diff --git a/drivers/scsi/ufs/ufs_quirks.c b/drivers/scsi/ufs/ufs_quirks.c
index 7212d31d6d99..a47dfba3243c 100644
--- a/drivers/scsi/ufs/ufs_quirks.c
+++ b/drivers/scsi/ufs/ufs_quirks.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -11,7 +11,7 @@
  * GNU General Public License for more details.
  */
 
-#include <linux/scsi/ufs/ufshcd.h>
+#include "ufshcd.h"
 #include "ufs_quirks.h"
 
 
diff --git a/drivers/scsi/ufs/ufs_test.c b/drivers/scsi/ufs/ufs_test.c
index c23e09e7c225..09fd655d31b1 100644
--- a/drivers/scsi/ufs/ufs_test.c
+++ b/drivers/scsi/ufs/ufs_test.c
@@ -18,8 +18,8 @@
 #include <scsi/scsi_device.h>
 #include <scsi/scsi_cmnd.h>
 #include <scsi/scsi_host.h>
-#include <linux/scsi/ufs/ufshcd.h>
-#include <linux/scsi/ufs/ufs.h>
+#include "ufshcd.h"
+#include "ufs.h"
 
 #define MODULE_NAME "ufs_test"
 
diff --git a/drivers/scsi/ufs/ufshcd-pci.c b/drivers/scsi/ufs/ufshcd-pci.c
index 650517925d51..52b546fb509b 100644
--- a/drivers/scsi/ufs/ufshcd-pci.c
+++ b/drivers/scsi/ufs/ufshcd-pci.c
@@ -33,7 +33,7 @@
  * this program.
  */
 
-#include <linux/scsi/ufs/ufshcd.h>
+#include "ufshcd.h"
 #include <linux/pci.h>
 #include <linux/pm_runtime.h>
 
diff --git a/drivers/scsi/ufs/ufshcd-pltfrm.c b/drivers/scsi/ufs/ufshcd-pltfrm.c
index d80e837bfb88..ca3e899fd1b6 100644
--- a/drivers/scsi/ufs/ufshcd-pltfrm.c
+++ b/drivers/scsi/ufs/ufshcd-pltfrm.c
@@ -39,7 +39,6 @@
 
 #include "ufshcd.h"
 #include "ufshcd-pltfrm.h"
-#include <linux/scsi/ufs/ufshcd.h>
 
 static int ufshcd_parse_clock_info(struct ufs_hba *hba)
 {
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 7b9ca922c892..be896d233038 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -42,7 +42,7 @@
 #include <linux/devfreq.h>
 #include <linux/nls.h>
 #include <linux/of.h>
-#include <linux/scsi/ufs/ufshcd.h>
+#include "ufshcd.h"
 #include "ufshci.h"
 #include "ufs_quirks.h"
 #include "ufs-debugfs.h"
diff --git a/include/linux/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index a94e3f3f7e64..ea90bdf9e715 100644
--- a/include/linux/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -55,7 +55,7 @@
 #include <linux/completion.h>
 #include <linux/regulator/consumer.h>
 #include <linux/pm_qos.h>
-#include <linux/scsi/ufs/unipro.h>
+#include "unipro.h"
 
 #include <asm/irq.h>
 #include <asm/byteorder.h>
@@ -318,7 +318,7 @@ struct ufs_pwr_mode_info {
 struct ufs_hba_variant_ops {
 	const char *name;
 	int	(*init)(struct ufs_hba *);
-	void    (*exit)(struct ufs_hba *);
+	void	(*exit)(struct ufs_hba *);
 	u32	(*get_ufs_hci_version)(struct ufs_hba *);
 	int	(*clk_scale_notify)(struct ufs_hba *, bool,
 				    enum ufs_notify_change_status);
@@ -332,8 +332,8 @@ struct ufs_hba_variant_ops {
 					enum ufs_notify_change_status status,
 					struct ufs_pa_layer_attr *,
 					struct ufs_pa_layer_attr *);
-	int     (*suspend)(struct ufs_hba *, enum ufs_pm_op);
-	int     (*resume)(struct ufs_hba *, enum ufs_pm_op);
+	int	(*suspend)(struct ufs_hba *, enum ufs_pm_op);
+	int	(*resume)(struct ufs_hba *, enum ufs_pm_op);
 	int	(*update_sec_cfg)(struct ufs_hba *hba, bool restore_sec_cfg);
 	void	(*dbg_register_dump)(struct ufs_hba *hba);
 	int	(*crypto_engine_cfg)(struct ufs_hba *, unsigned int);
diff --git a/include/linux/scsi/ufs/unipro.h b/drivers/scsi/ufs/unipro.h
index 3fdd775ee306..3fdd775ee306 100644
--- a/include/linux/scsi/ufs/unipro.h
+++ b/drivers/scsi/ufs/unipro.h
diff --git a/include/linux/phy/phy-qcom-ufs.h b/include/linux/phy/phy-qcom-ufs.h
index e0695a9a8bec..97554cfe2512 100644
--- a/include/linux/phy/phy-qcom-ufs.h
+++ b/include/linux/phy/phy-qcom-ufs.h
@@ -15,9 +15,7 @@
 #ifndef PHY_QCOM_UFS_H_
 #define PHY_QCOM_UFS_H_
 
-#include <linux/scsi/ufs/ufshcd.h>
-#include <linux/scsi/ufs/unipro.h>
-#include <linux/scsi/ufs/ufs-qcom.h>
+#include "phy.h"
 
 /**
  * ufs_qcom_phy_enable_ref_clk() - Enable the phy