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authoransharma <ansharma@codeaurora.org>2016-09-23 17:34:11 +0530
committeransharma <ansharma@codeaurora.org>2016-09-29 22:36:08 +0530
commit69281944901c6f8b364cd4e2f80cc5ee95dc521f (patch)
tree22ddc2734c1c56e456e4a75f9e99ad65ea9b771e
parent626caf4e54864d90e8d104277f9a1446e487c7e1 (diff)
ARM: dts: msm: Add SPMI device node for MSMFALCON
Add the SPMI node for MSMFALCON with required configuration and keep it disabled. CRs-Fixed: 1070059 Change-Id: I06ff3f095344a240c3597c8a98bd8028ca491f03 Signed-off-by: ansharma <ansharma@codeaurora.org>
-rw-r--r--arch/arm/boot/dts/qcom/msmfalcon.dtsi21
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom/msmfalcon.dtsi b/arch/arm/boot/dts/qcom/msmfalcon.dtsi
index f5cabe910c93..9d49936d15d2 100644
--- a/arch/arm/boot/dts/qcom/msmfalcon.dtsi
+++ b/arch/arm/boot/dts/qcom/msmfalcon.dtsi
@@ -231,6 +231,27 @@
clock-frequency = <19200000>;
};
+ spmi_bus: qcom,spmi@800f000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0x800f000 0x1000>,
+ <0x8400000 0x1000000>,
+ <0x9400000 0x1000000>,
+ <0xa400000 0x220000>,
+ <0x800a000 0x3000>;
+ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+ interrupt-names = "periph_irq";
+ interrupts = <GIC_SPI 326 IRQ_TYPE_NONE>;
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ cell-index = <0>;
+ qcom,not-wakeup; /* Needed until Full-boot-chain enabled */
+ status = "ok";
+ };
+
qcom,sps {
compatible = "qcom,msm_sps_4k";
qcom,pipe-attr-ee;