iommu/arm-smmu: add DT option to avoid enabling translations on attach

There are certain use cases that require the stream matching table to be
programmed without actually enabling translations on the
SMMU (i.e. leaving SCR0.M=0).  For example, when a hypervisor is
controlling the stage-2 context bank of a nested configuration where
stage-1 needs to be bypassed.  This mode of operation is described in
the ARM SMMU spec as "stage 1 and stage 2 contexts are valid, but the
SMMU is not enabled for stage 1 translation" (Section 2.1: "Overview of
SMMU operation").

The easiest way to get the stream-matching table programmed correctly is
to program it as usual from Linux but just leave SCR0.M=0.  Add a DT
option to do this.

Change-Id: I065a38f845ae8873bc51221fe64a39b1908032d6
Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org>

2 files changed, 17 insertions, 1 deletions

diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
index 801e24c2d810..e1aaeb4a355c 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
@@ -92,6 +92,18 @@ conditions.
                   Thulium v1.  You *must* also set qcom,tz-device-id for
                   this to work.
 
+- qcom,no-mmu-enable : When attaching to this SMMU, program everything as
+                  usual (stream matching table, etc) but leave the SCTLR.M
+                  bit disabled, so that the SMMU doesn't actually perform
+                  translations.  This is needed in cases where the stream
+                  matching table needs to be set up without turning on SMMU
+                  translations (for example, when nested translations are
+                  used with a hypervisor controlling stage-2).  This mode of
+                  operation is described in the ARM SMMU spec as "stage 1
+                  and stage 2 contexts are valid, but the SMMU is not
+                  enabled for stage 1 translation" (Section 2.1: "Overview
+                  of SMMU operation").
+
 - clocks        : List of clocks to be used during SMMU register access. See
                   Documentation/devicetree/bindings/clock/clock-bindings.txt
                   for information about the format. For each clock specified
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index 6d2ed89baeed..07546313f5b9 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -431,6 +431,7 @@ struct arm_smmu_device {
 #define ARM_SMMU_OPT_ERRATA_CTX_FAULT_HANG (1 << 5)
 #define ARM_SMMU_OPT_FATAL_ASF		(1 << 6)
 #define ARM_SMMU_OPT_ERRATA_TZ_ATOS	(1 << 7)
+#define ARM_SMMU_OPT_NO_M		(1 << 8)
 	u32				options;
 	enum arm_smmu_arch_version	version;
 
@@ -503,6 +504,7 @@ static struct arm_smmu_option_prop arm_smmu_options[] = {
 	{ ARM_SMMU_OPT_ERRATA_CTX_FAULT_HANG, "qcom,errata-ctx-fault-hang" },
 	{ ARM_SMMU_OPT_FATAL_ASF, "qcom,fatal-asf" },
 	{ ARM_SMMU_OPT_ERRATA_TZ_ATOS, "qcom,errata-tz-atos" },
+	{ ARM_SMMU_OPT_NO_M, "qcom,no-mmu-enable" },
 	{ 0, NULL},
 };
 
@@ -1147,7 +1149,9 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain)
 	}
 
 	/* SCTLR */
-	reg = SCTLR_CFCFG | SCTLR_CFIE | SCTLR_CFRE | SCTLR_M | SCTLR_EAE_SBOP;
+	reg = SCTLR_CFCFG | SCTLR_CFIE | SCTLR_CFRE | SCTLR_EAE_SBOP;
+	if (!(smmu->options & ARM_SMMU_OPT_NO_M))
+		reg |= SCTLR_M;
 	if (stage1)
 		reg |= SCTLR_S1_ASIDPNE;
 #ifdef __BIG_ENDIAN