diff options
| author | Dhaval Patel <pdhaval@codeaurora.org> | 2015-02-15 15:31:05 -0800 |
|---|---|---|
| committer | David Keitel <dkeitel@codeaurora.org> | 2016-03-23 20:38:02 -0700 |
| commit | 6339a9f6561388eadb2d07a32a58b3877fc8ac87 (patch) | |
| tree | 0193bbec40db104a9b0e1790bec124694ad780c7 | |
| parent | 9382fb049fa58e4aab1da95767c64450cd8a56ef (diff) | |
msm: mdss: handle mmagic mdss axi clock for thulium target
MDSS module needs turn on mmagic AXI clock on thulium target
when it tries to fetch data or write data to output buffers.
This change adds that support.
Change-Id: I3e84046274d377c30028608217247bdfb32bc341
[veeras@codeaurora.org: As part of 3.18 upgrade,
remove msmthulium-mdss.dtsi changes from this commit]
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
| -rw-r--r-- | drivers/video/fbdev/msm/mdss.h | 1 | ||||
| -rw-r--r-- | drivers/video/fbdev/msm/mdss_mdp.c | 4 |
2 files changed, 5 insertions, 0 deletions
diff --git a/drivers/video/fbdev/msm/mdss.h b/drivers/video/fbdev/msm/mdss.h index 7c19e5d6c41c..1a24a2de4b1d 100644 --- a/drivers/video/fbdev/msm/mdss.h +++ b/drivers/video/fbdev/msm/mdss.h @@ -38,6 +38,7 @@ enum mdss_mdp_clk_type { MDSS_CLK_MDP_CORE, MDSS_CLK_MDP_LUT, MDSS_CLK_MDP_VSYNC, + MDSS_CLK_MMAGIC_AXI, MDSS_MAX_CLK }; diff --git a/drivers/video/fbdev/msm/mdss_mdp.c b/drivers/video/fbdev/msm/mdss_mdp.c index 9bf3079006ba..fef1ca18b1ee 100644 --- a/drivers/video/fbdev/msm/mdss_mdp.c +++ b/drivers/video/fbdev/msm/mdss_mdp.c @@ -783,6 +783,7 @@ void mdss_mdp_clk_ctrl(int enable) mdss_mdp_clk_update(MDSS_CLK_AXI, enable); mdss_mdp_clk_update(MDSS_CLK_MDP_CORE, enable); mdss_mdp_clk_update(MDSS_CLK_MDP_LUT, enable); + mdss_mdp_clk_update(MDSS_CLK_MMAGIC_AXI, enable); if (mdata->vsync_ena) mdss_mdp_clk_update(MDSS_CLK_MDP_VSYNC, enable); @@ -910,6 +911,9 @@ static int mdss_mdp_irq_clk_setup(struct mdss_data_type *mdata) /* vsync_clk is optional for non-smart panels */ mdss_mdp_irq_clk_register(mdata, "vsync_clk", MDSS_CLK_MDP_VSYNC); + mdss_mdp_irq_clk_register(mdata, "mmagic_mdss_axi_clk", + MDSS_CLK_MMAGIC_AXI); + /* Setting the default clock rate to the max supported.*/ mdss_mdp_set_clk_rate(mdata->max_mdp_clk_rate); pr_debug("mdp clk rate=%ld\n", mdss_mdp_get_clk_rate(MDSS_CLK_MDP_SRC)); |