diff options
| author | Osvaldo Banuelos <osvaldob@codeaurora.org> | 2016-09-09 13:42:02 -0700 |
|---|---|---|
| committer | Gerrit - the friendly Code Review server <code-review@localhost> | 2016-10-25 15:44:15 -0700 |
| commit | 5d5c259608fe3dcafc63bfd2ea45645acc5635f8 (patch) | |
| tree | 1d98492797892360142c13dc7518a622543c5317 | |
| parent | 18e1eb265e1bb25cb9cafb2f728c3d9026ca9d3d (diff) | |
ARM: dts: msm: Enable ACD on msmcobalt v2
Add the necessary configuration to the OSM clock device in
msmcobalt v2 to initialize ACD.
CRs-Fixed: 1053383
Change-Id: I77eae2675e92447287bad05280cf32fc3c5b0fdd
Signed-off-by: Osvaldo Banuelos <osvaldob@codeaurora.org>
| -rw-r--r-- | arch/arm/boot/dts/qcom/msmcobalt-v2.dtsi | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom/msmcobalt-v2.dtsi b/arch/arm/boot/dts/qcom/msmcobalt-v2.dtsi index 81e2203a5e61..f1f074caaf85 100644 --- a/arch/arm/boot/dts/qcom/msmcobalt-v2.dtsi +++ b/arch/arm/boot/dts/qcom/msmcobalt-v2.dtsi @@ -26,6 +26,25 @@ &clock_cpu { compatible = "qcom,cpu-clock-osm-msmcobalt-v2"; + reg = <0x179c0000 0x4000>, + <0x17916000 0x1000>, + <0x17816000 0x1000>, + <0x179d1000 0x1000>, + <0x17914800 0x800>, + <0x17814800 0x800>, + <0x00784130 0x8>, + <0x1791101c 0x8>; + reg-names = "osm", "pwrcl_pll", "perfcl_pll", + "apcs_common", "pwrcl_acd", "perfcl_acd", + "perfcl_efuse", "debug"; + + qcom,acdtd-val = <0x00009611 0x00009611>; + qcom,acdcr-val = <0x002b5ffd 0x002b5ffd>; + qcom,acdsscr-val = <0x00000501 0x00000501>; + qcom,acdextint0-val = <0x2cf9ae8 0x2cf9ae8>; + qcom,acdextint1-val = <0x2cf9afc 0x2cf9afc>; + qcom,acdautoxfer-val = <0x00000015 0x00000015>; + /delete-property/ qcom,llm-sw-overr; qcom,pwrcl-speedbin0-v0 = < 300000000 0x0004000f 0x01200020 0x1 1 >, |