ARM: dts: msm: Add USB2 device node for SDM660

Add USB2 device node for SDM660 for using secondary USB2 port
in host only mode.

Change-Id: I8ff06411902bcafbb5b3f429634760d4c44a7b20
Signed-off-by: Vijayavardhan Vennapusa <vvreddy@codeaurora.org>

2 files changed, 58 insertions, 4 deletions

diff --git a/arch/arm/boot/dts/qcom/sdm660-common.dtsi b/arch/arm/boot/dts/qcom/sdm660-common.dtsi
index e5adf168a477..f511e4d80c9d 100644
--- a/arch/arm/boot/dts/qcom/sdm660-common.dtsi
+++ b/arch/arm/boot/dts/qcom/sdm660-common.dtsi
@@ -450,6 +450,54 @@
 		qcom,reset-ep-after-lpm-resume;
 	};
 
+       usb2s: hsusb@c200000 {
+		compatible = "qcom,dwc-usb3-msm";
+		reg = <0x0c200000 0xfc000>,
+			<0x0c016000 0x400>;
+		reg-names = "core_base",
+			"ahb2phy_base";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		interrupts = <0 348 0>, <0 144 0>;
+		interrupt-names = "hs_phy_irq", "pwr_event_irq";
+
+		qcom,msm-bus,name = "usb-hs";
+		qcom,msm-bus,num-cases = <2>;
+		qcom,msm-bus,num-paths = <1>;
+		qcom,msm-bus,vectors-KBps =
+			<87 512 0 0>,
+			<87 512 60000 800000>;
+
+		qcom,pm-qos-latency = <52>; /* CPU-CLUSTER-WFI-LVL latency +1 */
+		clocks = <&clock_gcc GCC_USB20_MASTER_CLK>,
+			<&clock_gcc GCC_CFG_NOC_USB2_AXI_CLK>,
+			<&clock_gcc GCC_USB20_MOCK_UTMI_CLK>,
+			<&clock_gcc GCC_USB20_SLEEP_CLK>,
+			<&clock_rpmcc CXO_DWC3_CLK>,
+			<&clock_gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
+		clock-names = "core_clk", "iface_clk", "utmi_clk", "sleep_clk",
+				"xo", "cfg_ahb_clk";
+		qcom,core-clk-rate = <60000000>;
+		resets = <&clock_gcc GCC_USB_20_BCR>;
+		reset-names = "core_reset";
+
+		status = "disabled";
+		dwc3@c200000 {
+			compatible = "snps,dwc3";
+			reg = <0x0c200000 0xc8d0>;
+			interrupt-parent = <&intc>;
+			interrupts = <0 143 0>;
+			usb-phy = <&qusb_phy1>, <&usb_nop_phy>;
+			maximum-speed = "high-speed";
+			snps,nominal-elastic-buffer;
+			snps,is-utmi-l1-suspend;
+			snps,hird-threshold = /bits/ 8 <0x0>;
+			dr_mode = "host";
+		};
+	};
+
 	qusb_phy1: qusb@c014000 {
 		compatible = "qcom,qusb2phy";
 		reg = <0x0c014000 0x180>,
@@ -459,7 +507,7 @@
 		vdd-supply = <&pm660l_l1>;
 		vdda18-supply = <&pm660_l10>;
 		vdda33-supply = <&pm660l_l7>;
-		qcom,vdd-voltage-level = <1 5 7>;
+		qcom,vdd-voltage-level = <0 925000 925000>;
 		qcom,qusb-phy-init-seq = <0xF8 0x80
 					0xB3 0x84
 					0x83 0x88
@@ -484,6 +532,10 @@
 		reset-names = "phy_reset";
 	};
 
+	usb_nop_phy: usb_nop_phy {
+		compatible = "usb-nop-xceiv";
+	};
+
 	sdhc_1: sdhci@c0c4000 {
 		compatible = "qcom,sdhci-msm-v5";
 		reg = <0xc0c4000 0x1000>, <0xc0c5000 0x1000>;
diff --git a/arch/arm/boot/dts/qcom/sdm660-pm.dtsi b/arch/arm/boot/dts/qcom/sdm660-pm.dtsi
index 1624975028c5..21fab4923331 100644
--- a/arch/arm/boot/dts/qcom/sdm660-pm.dtsi
+++ b/arch/arm/boot/dts/qcom/sdm660-pm.dtsi
@@ -341,8 +341,10 @@
 		qcom,gic-map =
 			<0x02 216>, /* tsens1_tsens_upper_lower_int */
 			<0x34 275>, /* qmp_usb3_lfps_rxterm_irq_cx */
-			<0x4f 379>, /* qusb2phy_intr */
-			<0x51 379>, /* qusb2phy_intr */
+			<0x4f 379>, /* qusb2phy_intr for Dm */
+			<0x50 380>, /* qusb2phy_intr for Dm for secondary PHY */
+			<0x51 379>, /* qusb2phy_intr for Dp */
+			<0x52 380>, /* qusb2phy_intr for Dp for secondary PHY */
 			<0x57 358>, /* ee0_apps_hlos_spmi_periph_irq */
 			<0x5b 519>, /* lpass_pmu_tmr_timeout_irq_cx */
 			<0xff 16>,  /* APC[0-7]_qgicQTmrHypPhysIrptReq */
@@ -484,6 +486,7 @@
 			<0xff 208>, /* lpi_dir_conn_irq_apps[0] */
 			<0xff 209>, /* lpi_dir_conn_irq_apps[1] */
 			<0xff 210>, /* lpi_dir_conn_irq_apps[2] */
+			<0xff 212>, /* usb30s_power_event_irq */
 			<0xff 213>, /* secure_wdog_bark_irq */
 			<0xff 214>, /* tsens1_tsens_max_min_int */
 			<0xff 215>, /* o_bimc_intr[0] */
@@ -610,7 +613,6 @@
 			<0xff 364>, /* osmmu_CIrpt[3] */
 			<0xff 365>, /* ipa_irq[0] */
 			<0xff 366>, /* osmmu_PMIrpt */
-			<0xff 380>, /* qusb2phy_intr */
 			<0xff 381>, /* osmmu_CIrpt[6] */
 			<0xff 382>, /* osmmu_CIrpt[7] */
 			<0xff 385>, /* osmmu_CIrpt[12] */